1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 crypto: crypto@ff060000 { 190 compatible = "rockchip,rk322x-crypto"; 191 reg = <0x0 0xff060000 0x0 0x10000>; 192 clock-names = "sclk_crypto"; 193 clocks = <&cru SCLK_CRYPTO>; 194 status = "disabled"; 195 }; 196 197 grf: syscon@ff100000 { 198 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 199 reg = <0x0 0xff100000 0x0 0x1000>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 203 io_domains: io-domains { 204 compatible = "rockchip,rk3328-io-voltage-domain"; 205 status = "disabled"; 206 }; 207 }; 208 209 uart0: serial@ff110000 { 210 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 211 reg = <0x0 0xff110000 0x0 0x100>; 212 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 214 clock-names = "baudclk", "apb_pclk"; 215 reg-shift = <2>; 216 reg-io-width = <4>; 217 dmas = <&dmac 2>, <&dmac 3>; 218 #dma-cells = <2>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 221 status = "disabled"; 222 }; 223 224 uart1: serial@ff120000 { 225 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 226 reg = <0x0 0xff120000 0x0 0x100>; 227 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 229 clock-names = "sclk_uart", "pclk_uart"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 dmas = <&dmac 4>, <&dmac 5>; 233 #dma-cells = <2>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 236 status = "disabled"; 237 }; 238 239 uart2: serial@ff130000 { 240 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 241 reg = <0x0 0xff130000 0x0 0x100>; 242 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 244 clock-names = "baudclk", "apb_pclk"; 245 clock-frequency = <24000000>; 246 reg-shift = <2>; 247 reg-io-width = <4>; 248 dmas = <&dmac 6>, <&dmac 7>; 249 #dma-cells = <2>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&uart2m1_xfer>; 252 status = "disabled"; 253 }; 254 255 pmu: power-management@ff140000 { 256 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 257 reg = <0x0 0xff140000 0x0 0x1000>; 258 }; 259 260 i2c0: i2c@ff150000 { 261 compatible = "rockchip,rk3328-i2c"; 262 reg = <0x0 0xff150000 0x0 0x1000>; 263 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 267 clock-names = "i2c", "pclk"; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&i2c0_xfer>; 270 status = "disabled"; 271 }; 272 273 i2c1: i2c@ff160000 { 274 compatible = "rockchip,rk3328-i2c"; 275 reg = <0x0 0xff160000 0x0 0x1000>; 276 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 280 clock-names = "i2c", "pclk"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2c1_xfer>; 283 status = "disabled"; 284 }; 285 286 i2c2: i2c@ff170000 { 287 compatible = "rockchip,rk3328-i2c"; 288 reg = <0x0 0xff170000 0x0 0x1000>; 289 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 293 clock-names = "i2c", "pclk"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c2_xfer>; 296 status = "disabled"; 297 }; 298 299 i2c3: i2c@ff180000 { 300 compatible = "rockchip,rk3328-i2c"; 301 reg = <0x0 0xff180000 0x0 0x1000>; 302 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 306 clock-names = "i2c", "pclk"; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c3_xfer>; 309 status = "disabled"; 310 }; 311 312 spi0: spi@ff190000 { 313 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 314 reg = <0x0 0xff190000 0x0 0x1000>; 315 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 319 clock-names = "spiclk", "apb_pclk"; 320 dmas = <&dmac 8>, <&dmac 9>; 321 #dma-cells = <2>; 322 dma-names = "tx", "rx"; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 325 status = "disabled"; 326 }; 327 328 wdt: watchdog@ff1a0000 { 329 compatible = "snps,dw-wdt"; 330 reg = <0x0 0xff1a0000 0x0 0x100>; 331 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 332 status = "disabled"; 333 }; 334 335 amba { 336 compatible = "simple-bus"; 337 #address-cells = <2>; 338 #size-cells = <2>; 339 ranges; 340 341 dmac: dmac@ff1f0000 { 342 compatible = "arm,pl330", "arm,primecell"; 343 reg = <0x0 0xff1f0000 0x0 0x4000>; 344 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cru ACLK_DMAC>; 347 clock-names = "apb_pclk"; 348 #dma-cells = <1>; 349 }; 350 }; 351 352 saradc: saradc@ff280000 { 353 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 354 reg = <0x0 0xff280000 0x0 0x100>; 355 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 356 #io-channel-cells = <1>; 357 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 358 clock-names = "saradc", "apb_pclk"; 359 resets = <&cru SRST_SARADC_P>; 360 reset-names = "saradc-apb"; 361 status = "disabled"; 362 }; 363 364 dmc: dmc { 365 compatible = "rockchip,rk3328-dmc"; 366 reg = <0x0 0xff400000 0x0 0x1000 367 0x0 0xff780000 0x0 0x3000 368 0x0 0xff100000 0x0 0x1000 369 0x0 0xff440000 0x0 0x1000 370 0x0 0xff720000 0x0 0x1000 371 0x0 0xff798000 0x0 0x1000>; 372 }; 373 374 cru: clock-controller@ff440000 { 375 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 376 reg = <0x0 0xff440000 0x0 0x1000>; 377 rockchip,grf = <&grf>; 378 #clock-cells = <1>; 379 #reset-cells = <1>; 380 assigned-clocks = 381 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 382 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 383 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 384 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 385 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 386 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 387 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 388 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 389 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 390 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 391 <&cru SCLK_WIFI>, <&cru ARMCLK>, 392 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 393 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 394 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 395 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 396 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 397 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 398 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 399 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 400 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 401 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 402 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 403 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 404 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 405 assigned-clock-parents = 406 <&cru HDMIPHY>, <&cru PLL_APLL>, 407 <&cru PLL_GPLL>, <&xin24m>, 408 <&xin24m>, <&xin24m>; 409 assigned-clock-rates = 410 <0>, <61440000>, 411 <0>, <24000000>, 412 <24000000>, <24000000>, 413 <150000000>, <150000000>, 414 <100000000>, <100000000>, 415 <100000000>, <100000000>, 416 <50000000>, <100000000>, 417 <100000000>, <100000000>, 418 <50000000>, <50000000>, 419 <50000000>, <50000000>, 420 <24000000>, <600000000>, 421 <491520000>, <1200000000>, 422 <150000000>, <75000000>, 423 <75000000>, <150000000>, 424 <75000000>, <75000000>, 425 <300000000>, <100000000>, 426 <300000000>, <200000000>, 427 <400000000>, <500000000>, 428 <200000000>, <300000000>, 429 <300000000>, <250000000>, 430 <200000000>, <100000000>, 431 <24000000>, <100000000>, 432 <150000000>, <50000000>, 433 <32768>, <32768>; 434 }; 435 436 usb2phy_grf: syscon-usb@ff450000 { 437 compatible = "rockchip,rk3328-usb2phy-grf", 438 "simple-mfd", "syscon"; 439 reg = <0x0 0xff450000 0x0 0x10000>; 440 #address-cells = <1>; 441 #size-cells = <1>; 442 443 u2phy: usb2-phy@100 { 444 compatible = "rockchip,rk3328-usb2phy"; 445 reg = <0x100 0x10>; 446 #phy-cells = <1>; 447 status = "disabled"; 448 449 u2phy_otg: otg-port { 450 #phy-cells = <0>; 451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "otg-bvalid", "otg-id", 455 "linestate"; 456 status = "disabled"; 457 }; 458 459 u2phy_host: host-port { 460 #phy-cells = <0>; 461 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "linestate"; 463 status = "disabled"; 464 }; 465 }; 466 }; 467 468 sdmmc: rksdmmc@ff500000 { 469 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 470 reg = <0x0 0xff500000 0x0 0x4000>; 471 max-frequency = <150000000>; 472 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 473 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 474 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 475 fifo-depth = <0x100>; 476 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 477 status = "disabled"; 478 }; 479 480 sdio: dwmmc@ff510000 { 481 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 482 reg = <0x0 0xff510000 0x0 0x4000>; 483 max-frequency = <150000000>; 484 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 485 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 486 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 487 fifo-depth = <0x100>; 488 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 489 status = "disabled"; 490 }; 491 492 emmc: rksdmmc@ff520000 { 493 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 494 reg = <0x0 0xff520000 0x0 0x4000>; 495 max-frequency = <150000000>; 496 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 497 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 498 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 499 fifo-depth = <0x100>; 500 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 501 status = "disabled"; 502 }; 503 504 gmac2io: ethernet@ff540000 { 505 compatible = "rockchip,rk3328-gmac"; 506 reg = <0x0 0xff540000 0x0 0x10000>; 507 rockchip,grf = <&grf>; 508 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 509 interrupt-names = "macirq"; 510 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 511 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 512 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 513 <&cru PCLK_MAC2IO>; 514 clock-names = "stmmaceth", "mac_clk_rx", 515 "mac_clk_tx", "clk_mac_ref", 516 "clk_mac_refout", "aclk_mac", 517 "pclk_mac"; 518 resets = <&cru SRST_GMAC2IO_A>; 519 reset-names = "stmmaceth"; 520 status = "disabled"; 521 }; 522 523 usb_host0_ehci: usb@ff5c0000 { 524 compatible = "generic-ehci"; 525 reg = <0x0 0xff5c0000 0x0 0x10000>; 526 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 527 phys = <&u2phy_host>; 528 phy-names = "usb"; 529 status = "disabled"; 530 }; 531 532 usb_host0_ohci: usb@ff5d0000 { 533 compatible = "generic-ohci"; 534 reg = <0x0 0xff5d0000 0x0 0x10000>; 535 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 536 phys = <&u2phy_host>; 537 phy-names = "usb"; 538 status = "disabled"; 539 }; 540 541 usb20_otg: usb@ff580000 { 542 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 543 "snps,dwc2"; 544 reg = <0x0 0xff580000 0x0 0x40000>; 545 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 546 hnp-srp-disable; 547 dr_mode = "otg"; 548 phys = <&u2phy_otg>; 549 phy-names = "usb"; 550 status = "disabled"; 551 }; 552 553 sdmmc_ext: rksdmmc@ff5f0000 { 554 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 555 reg = <0x0 0xff5f0000 0x0 0x4000>; 556 max-frequency = <150000000>; 557 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 558 clock-names = "biu", "ciu"; 559 fifo-depth = <0x100>; 560 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 561 status = "disabled"; 562 }; 563 564 usb_host0_xhci: usb@ff600000 { 565 compatible = "rockchip,rk3328-xhci"; 566 reg = <0x0 0xff600000 0x0 0x100000>; 567 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 568 snps,dis-enblslpm-quirk; 569 snps,phyif-utmi-bits = <16>; 570 snps,dis-u2-freeclk-exists-quirk; 571 snps,dis-u2-susphy-quirk; 572 status = "disabled"; 573 }; 574 575 gic: interrupt-controller@ffb70000 { 576 compatible = "arm,gic-400"; 577 #interrupt-cells = <3>; 578 #address-cells = <0>; 579 interrupt-controller; 580 reg = <0x0 0xff811000 0 0x1000>, 581 <0x0 0xff812000 0 0x2000>, 582 <0x0 0xff814000 0 0x2000>, 583 <0x0 0xff816000 0 0x2000>; 584 interrupts = <GIC_PPI 9 585 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 586 }; 587 588 pinctrl: pinctrl { 589 compatible = "rockchip,rk3328-pinctrl"; 590 rockchip,grf = <&grf>; 591 #address-cells = <2>; 592 #size-cells = <2>; 593 ranges; 594 595 gpio0: gpio0@ff210000 { 596 compatible = "rockchip,gpio-bank"; 597 reg = <0x0 0xff210000 0x0 0x100>; 598 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&cru PCLK_GPIO0>; 600 601 gpio-controller; 602 #gpio-cells = <2>; 603 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 }; 607 608 gpio1: gpio1@ff220000 { 609 compatible = "rockchip,gpio-bank"; 610 reg = <0x0 0xff220000 0x0 0x100>; 611 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cru PCLK_GPIO1>; 613 614 gpio-controller; 615 #gpio-cells = <2>; 616 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 }; 620 621 gpio2: gpio2@ff230000 { 622 compatible = "rockchip,gpio-bank"; 623 reg = <0x0 0xff230000 0x0 0x100>; 624 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&cru PCLK_GPIO2>; 626 627 gpio-controller; 628 #gpio-cells = <2>; 629 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 }; 633 634 gpio3: gpio3@ff240000 { 635 compatible = "rockchip,gpio-bank"; 636 reg = <0x0 0xff240000 0x0 0x100>; 637 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&cru PCLK_GPIO3>; 639 640 gpio-controller; 641 #gpio-cells = <2>; 642 643 interrupt-controller; 644 #interrupt-cells = <2>; 645 }; 646 647 pcfg_pull_up: pcfg-pull-up { 648 bias-pull-up; 649 }; 650 651 pcfg_pull_down: pcfg-pull-down { 652 bias-pull-down; 653 }; 654 655 pcfg_pull_none: pcfg-pull-none { 656 bias-disable; 657 }; 658 659 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 660 bias-disable; 661 drive-strength = <2>; 662 }; 663 664 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 665 bias-pull-up; 666 drive-strength = <2>; 667 }; 668 669 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 670 bias-pull-up; 671 drive-strength = <4>; 672 }; 673 674 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 675 bias-disable; 676 drive-strength = <4>; 677 }; 678 679 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 680 bias-pull-down; 681 drive-strength = <4>; 682 }; 683 684 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 685 bias-disable; 686 drive-strength = <8>; 687 }; 688 689 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 690 bias-pull-up; 691 drive-strength = <8>; 692 }; 693 694 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 695 bias-disable; 696 drive-strength = <12>; 697 }; 698 699 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 700 bias-pull-up; 701 drive-strength = <12>; 702 }; 703 704 pcfg_output_high: pcfg-output-high { 705 output-high; 706 }; 707 708 pcfg_output_low: pcfg-output-low { 709 output-low; 710 }; 711 712 pcfg_input_high: pcfg-input-high { 713 bias-pull-up; 714 input-enable; 715 }; 716 717 pcfg_input: pcfg-input { 718 input-enable; 719 }; 720 721 i2c0 { 722 i2c0_xfer: i2c0-xfer { 723 rockchip,pins = 724 <2 24 RK_FUNC_1 &pcfg_pull_none>, 725 <2 25 RK_FUNC_1 &pcfg_pull_none>; 726 }; 727 }; 728 729 i2c1 { 730 i2c1_xfer: i2c1-xfer { 731 rockchip,pins = 732 <2 4 RK_FUNC_2 &pcfg_pull_none>, 733 <2 5 RK_FUNC_2 &pcfg_pull_none>; 734 }; 735 }; 736 737 i2c2 { 738 i2c2_xfer: i2c2-xfer { 739 rockchip,pins = 740 <2 13 RK_FUNC_1 &pcfg_pull_none>, 741 <2 14 RK_FUNC_1 &pcfg_pull_none>; 742 }; 743 }; 744 745 i2c3 { 746 i2c3_xfer: i2c3-xfer { 747 rockchip,pins = 748 <0 5 RK_FUNC_2 &pcfg_pull_none>, 749 <0 6 RK_FUNC_2 &pcfg_pull_none>; 750 }; 751 i2c3_gpio: i2c3-gpio { 752 rockchip,pins = 753 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 754 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 755 }; 756 }; 757 758 hdmi_i2c { 759 hdmii2c_xfer: hdmii2c-xfer { 760 rockchip,pins = 761 <0 5 RK_FUNC_1 &pcfg_pull_none>, 762 <0 6 RK_FUNC_1 &pcfg_pull_none>; 763 }; 764 }; 765 766 uart0 { 767 uart0_xfer: uart0-xfer { 768 rockchip,pins = 769 <1 9 RK_FUNC_1 &pcfg_pull_up>, 770 <1 8 RK_FUNC_1 &pcfg_pull_up>; 771 }; 772 773 uart0_cts: uart0-cts { 774 rockchip,pins = 775 <1 11 RK_FUNC_1 &pcfg_pull_none>; 776 }; 777 778 uart0_rts: uart0-rts { 779 rockchip,pins = 780 <1 10 RK_FUNC_1 &pcfg_pull_none>; 781 }; 782 783 uart0_rts_gpio: uart0-rts-gpio { 784 rockchip,pins = 785 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 786 }; 787 }; 788 789 uart1 { 790 uart1_xfer: uart1-xfer { 791 rockchip,pins = 792 <3 4 RK_FUNC_4 &pcfg_pull_up>, 793 <3 6 RK_FUNC_4 &pcfg_pull_up>; 794 }; 795 796 uart1_cts: uart1-cts { 797 rockchip,pins = 798 <3 7 RK_FUNC_4 &pcfg_pull_none>; 799 }; 800 801 uart1_rts: uart1-rts { 802 rockchip,pins = 803 <3 5 RK_FUNC_4 &pcfg_pull_none>; 804 }; 805 806 uart1_rts_gpio: uart1-rts-gpio { 807 rockchip,pins = 808 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 809 }; 810 }; 811 812 uart2-0 { 813 uart2m0_xfer: uart2m0-xfer { 814 rockchip,pins = 815 <1 0 RK_FUNC_2 &pcfg_pull_up>, 816 <1 1 RK_FUNC_2 &pcfg_pull_up>; 817 }; 818 }; 819 820 uart2-1 { 821 uart2m1_xfer: uart2m1-xfer { 822 rockchip,pins = 823 <2 0 RK_FUNC_1 &pcfg_pull_up>, 824 <2 1 RK_FUNC_1 &pcfg_pull_up>; 825 }; 826 }; 827 828 spi0-0 { 829 spi0m0_clk: spi0m0-clk { 830 rockchip,pins = 831 <2 8 RK_FUNC_1 &pcfg_pull_up>; 832 }; 833 834 spi0m0_cs0: spi0m0-cs0 { 835 rockchip,pins = 836 <2 11 RK_FUNC_1 &pcfg_pull_up>; 837 }; 838 839 spi0m0_tx: spi0m0-tx { 840 rockchip,pins = 841 <2 9 RK_FUNC_1 &pcfg_pull_up>; 842 }; 843 844 spi0m0_rx: spi0m0-rx { 845 rockchip,pins = 846 <2 10 RK_FUNC_1 &pcfg_pull_up>; 847 }; 848 849 spi0m0_cs1: spi0m0-cs1 { 850 rockchip,pins = 851 <2 12 RK_FUNC_1 &pcfg_pull_up>; 852 }; 853 }; 854 855 spi0-1 { 856 spi0m1_clk: spi0m1-clk { 857 rockchip,pins = 858 <3 23 RK_FUNC_2 &pcfg_pull_up>; 859 }; 860 861 spi0m1_cs0: spi0m1-cs0 { 862 rockchip,pins = 863 <3 26 RK_FUNC_2 &pcfg_pull_up>; 864 }; 865 866 spi0m1_tx: spi0m1-tx { 867 rockchip,pins = 868 <3 25 RK_FUNC_2 &pcfg_pull_up>; 869 }; 870 871 spi0m1_rx: spi0m1-rx { 872 rockchip,pins = 873 <3 24 RK_FUNC_2 &pcfg_pull_up>; 874 }; 875 876 spi0m1_cs1: spi0m1-cs1 { 877 rockchip,pins = 878 <3 27 RK_FUNC_2 &pcfg_pull_up>; 879 }; 880 }; 881 882 spi0-2 { 883 spi0m2_clk: spi0m2-clk { 884 rockchip,pins = 885 <3 0 RK_FUNC_4 &pcfg_pull_up>; 886 }; 887 888 spi0m2_cs0: spi0m2-cs0 { 889 rockchip,pins = 890 <3 8 RK_FUNC_3 &pcfg_pull_up>; 891 }; 892 893 spi0m2_tx: spi0m2-tx { 894 rockchip,pins = 895 <3 1 RK_FUNC_4 &pcfg_pull_up>; 896 }; 897 898 spi0m2_rx: spi0m2-rx { 899 rockchip,pins = 900 <3 2 RK_FUNC_4 &pcfg_pull_up>; 901 }; 902 }; 903 904 i2s1 { 905 i2s1_mclk: i2s1-mclk { 906 rockchip,pins = 907 <2 15 RK_FUNC_1 &pcfg_pull_none>; 908 }; 909 910 i2s1_sclk: i2s1-sclk { 911 rockchip,pins = 912 <2 18 RK_FUNC_1 &pcfg_pull_none>; 913 }; 914 915 i2s1_lrckrx: i2s1-lrckrx { 916 rockchip,pins = 917 <2 16 RK_FUNC_1 &pcfg_pull_none>; 918 }; 919 920 i2s1_lrcktx: i2s1-lrcktx { 921 rockchip,pins = 922 <2 17 RK_FUNC_1 &pcfg_pull_none>; 923 }; 924 925 i2s1_sdi: i2s1-sdi { 926 rockchip,pins = 927 <2 19 RK_FUNC_1 &pcfg_pull_none>; 928 }; 929 930 i2s1_sdo: i2s1-sdo { 931 rockchip,pins = 932 <2 23 RK_FUNC_1 &pcfg_pull_none>; 933 }; 934 935 i2s1_sdio1: i2s1-sdio1 { 936 rockchip,pins = 937 <2 20 RK_FUNC_1 &pcfg_pull_none>; 938 }; 939 940 i2s1_sdio2: i2s1-sdio2 { 941 rockchip,pins = 942 <2 21 RK_FUNC_1 &pcfg_pull_none>; 943 }; 944 945 i2s1_sdio3: i2s1-sdio3 { 946 rockchip,pins = 947 <2 22 RK_FUNC_1 &pcfg_pull_none>; 948 }; 949 950 i2s1_sleep: i2s1-sleep { 951 rockchip,pins = 952 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 953 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 954 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 955 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 956 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 957 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 958 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 959 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 960 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 961 }; 962 }; 963 964 i2s2-0 { 965 i2s2m0_mclk: i2s2m0-mclk { 966 rockchip,pins = 967 <1 21 RK_FUNC_1 &pcfg_pull_none>; 968 }; 969 970 i2s2m0_sclk: i2s2m0-sclk { 971 rockchip,pins = 972 <1 22 RK_FUNC_1 &pcfg_pull_none>; 973 }; 974 975 i2s2m0_lrckrx: i2s2m0-lrckrx { 976 rockchip,pins = 977 <1 26 RK_FUNC_1 &pcfg_pull_none>; 978 }; 979 980 i2s2m0_lrcktx: i2s2m0-lrcktx { 981 rockchip,pins = 982 <1 23 RK_FUNC_1 &pcfg_pull_none>; 983 }; 984 985 i2s2m0_sdi: i2s2m0-sdi { 986 rockchip,pins = 987 <1 24 RK_FUNC_1 &pcfg_pull_none>; 988 }; 989 990 i2s2m0_sdo: i2s2m0-sdo { 991 rockchip,pins = 992 <1 25 RK_FUNC_1 &pcfg_pull_none>; 993 }; 994 995 i2s2m0_sleep: i2s2m0-sleep { 996 rockchip,pins = 997 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 998 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 999 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 1000 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 1001 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 1002 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 1003 }; 1004 }; 1005 1006 i2s2-1 { 1007 i2s2m1_mclk: i2s2m1-mclk { 1008 rockchip,pins = 1009 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1010 }; 1011 1012 i2s2m1_sclk: i2s2m1-sclk { 1013 rockchip,pins = 1014 <3 0 RK_FUNC_6 &pcfg_pull_none>; 1015 }; 1016 1017 i2s2m1_lrckrx: i2sm1-lrckrx { 1018 rockchip,pins = 1019 <3 8 RK_FUNC_6 &pcfg_pull_none>; 1020 }; 1021 1022 i2s2m1_lrcktx: i2s2m1-lrcktx { 1023 rockchip,pins = 1024 <3 8 RK_FUNC_4 &pcfg_pull_none>; 1025 }; 1026 1027 i2s2m1_sdi: i2s2m1-sdi { 1028 rockchip,pins = 1029 <3 2 RK_FUNC_6 &pcfg_pull_none>; 1030 }; 1031 1032 i2s2m1_sdo: i2s2m1-sdo { 1033 rockchip,pins = 1034 <3 1 RK_FUNC_6 &pcfg_pull_none>; 1035 }; 1036 1037 i2s2m1_sleep: i2s2m1-sleep { 1038 rockchip,pins = 1039 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1040 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 1041 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 1042 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 1043 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 1044 }; 1045 }; 1046 1047 spdif-0 { 1048 spdifm0_tx: spdifm0-tx { 1049 rockchip,pins = 1050 <0 27 RK_FUNC_1 &pcfg_pull_none>; 1051 }; 1052 }; 1053 1054 spdif-1 { 1055 spdifm1_tx: spdifm1-tx { 1056 rockchip,pins = 1057 <2 17 RK_FUNC_2 &pcfg_pull_none>; 1058 }; 1059 }; 1060 1061 spdif-2 { 1062 spdifm2_tx: spdifm2-tx { 1063 rockchip,pins = 1064 <0 2 RK_FUNC_2 &pcfg_pull_none>; 1065 }; 1066 }; 1067 1068 sdmmc0-0 { 1069 sdmmc0m0_pwren: sdmmc0m0-pwren { 1070 rockchip,pins = 1071 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1072 }; 1073 1074 sdmmc0m0_gpio: sdmmc0m0-gpio { 1075 rockchip,pins = 1076 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1077 }; 1078 }; 1079 1080 sdmmc0-1 { 1081 sdmmc0m1_pwren: sdmmc0m1-pwren { 1082 rockchip,pins = 1083 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1084 }; 1085 1086 sdmmc0m1_gpio: sdmmc0m1-gpio { 1087 rockchip,pins = 1088 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1089 }; 1090 }; 1091 1092 sdmmc0 { 1093 sdmmc0_clk: sdmmc0-clk { 1094 rockchip,pins = 1095 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1096 }; 1097 1098 sdmmc0_cmd: sdmmc0-cmd { 1099 rockchip,pins = 1100 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1101 }; 1102 1103 sdmmc0_dectn: sdmmc0-dectn { 1104 rockchip,pins = 1105 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1106 }; 1107 1108 sdmmc0_wrprt: sdmmc0-wrprt { 1109 rockchip,pins = 1110 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1111 }; 1112 1113 sdmmc0_bus1: sdmmc0-bus1 { 1114 rockchip,pins = 1115 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1116 }; 1117 1118 sdmmc0_bus4: sdmmc0-bus4 { 1119 rockchip,pins = 1120 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1121 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1122 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1123 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1124 }; 1125 1126 sdmmc0_gpio: sdmmc0-gpio { 1127 rockchip,pins = 1128 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1129 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1130 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1131 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1132 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1133 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1134 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1135 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1136 }; 1137 }; 1138 1139 sdmmc0ext { 1140 sdmmc0ext_clk: sdmmc0ext-clk { 1141 rockchip,pins = 1142 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1143 }; 1144 1145 sdmmc0ext_cmd: sdmmc0ext-cmd { 1146 rockchip,pins = 1147 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1148 }; 1149 1150 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1151 rockchip,pins = 1152 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1153 }; 1154 1155 sdmmc0ext_dectn: sdmmc0ext-dectn { 1156 rockchip,pins = 1157 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1158 }; 1159 1160 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1161 rockchip,pins = 1162 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1163 }; 1164 1165 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1166 rockchip,pins = 1167 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1168 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1169 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1170 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1171 }; 1172 1173 sdmmc0ext_gpio: sdmmc0ext-gpio { 1174 rockchip,pins = 1175 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1176 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1177 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1178 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1179 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1180 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1181 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1182 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1183 }; 1184 }; 1185 1186 sdmmc1 { 1187 sdmmc1_clk: sdmmc1-clk { 1188 rockchip,pins = 1189 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1190 }; 1191 1192 sdmmc1_cmd: sdmmc1-cmd { 1193 rockchip,pins = 1194 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1195 }; 1196 1197 sdmmc1_pwren: sdmmc1-pwren { 1198 rockchip,pins = 1199 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1200 }; 1201 1202 sdmmc1_wrprt: sdmmc1-wrprt { 1203 rockchip,pins = 1204 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1205 }; 1206 1207 sdmmc1_dectn: sdmmc1-dectn { 1208 rockchip,pins = 1209 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1210 }; 1211 1212 sdmmc1_bus1: sdmmc1-bus1 { 1213 rockchip,pins = 1214 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1215 }; 1216 1217 sdmmc1_bus4: sdmmc1-bus4 { 1218 rockchip,pins = 1219 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1220 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1221 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1222 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1223 }; 1224 1225 sdmmc1_gpio: sdmmc1-gpio { 1226 rockchip,pins = 1227 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1228 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1229 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1230 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1231 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1232 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1233 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1234 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1235 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1236 }; 1237 }; 1238 1239 emmc { 1240 emmc_clk: emmc-clk { 1241 rockchip,pins = 1242 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1243 }; 1244 1245 emmc_cmd: emmc-cmd { 1246 rockchip,pins = 1247 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1248 }; 1249 1250 emmc_pwren: emmc-pwren { 1251 rockchip,pins = 1252 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1253 }; 1254 1255 emmc_rstnout: emmc-rstnout { 1256 rockchip,pins = 1257 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1258 }; 1259 1260 emmc_bus1: emmc-bus1 { 1261 rockchip,pins = 1262 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1263 }; 1264 1265 emmc_bus4: emmc-bus4 { 1266 rockchip,pins = 1267 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1268 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1269 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1270 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1271 }; 1272 1273 emmc_bus8: emmc-bus8 { 1274 rockchip,pins = 1275 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1276 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1277 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1278 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1279 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1280 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1281 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1282 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1283 }; 1284 }; 1285 1286 pwm0 { 1287 pwm0_pin: pwm0-pin { 1288 rockchip,pins = 1289 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1290 }; 1291 }; 1292 1293 pwm1 { 1294 pwm1_pin: pwm1-pin { 1295 rockchip,pins = 1296 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1297 }; 1298 }; 1299 1300 pwm2 { 1301 pwm2_pin: pwm2-pin { 1302 rockchip,pins = 1303 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1304 }; 1305 }; 1306 1307 pwmir { 1308 pwmir_pin: pwmir-pin { 1309 rockchip,pins = 1310 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1311 }; 1312 }; 1313 1314 gmac-0 { 1315 rgmiim0_pins: rgmiim0-pins { 1316 rockchip,pins = 1317 /* mac_txclk */ 1318 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1319 /* mac_rxclk */ 1320 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1321 /* mac_mdio */ 1322 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1323 /* mac_txen */ 1324 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1325 /* mac_clk */ 1326 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1327 /* mac_rxdv */ 1328 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1329 /* mac_mdc */ 1330 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1331 /* mac_rxd1 */ 1332 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1333 /* mac_rxd0 */ 1334 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1335 /* mac_txd1 */ 1336 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1337 /* mac_txd0 */ 1338 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1339 /* mac_rxd3 */ 1340 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1341 /* mac_rxd2 */ 1342 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1343 /* mac_txd3 */ 1344 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1345 /* mac_txd2 */ 1346 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1347 }; 1348 1349 rmiim0_pins: rmiim0-pins { 1350 rockchip,pins = 1351 /* mac_mdio */ 1352 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1353 /* mac_txen */ 1354 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1355 /* mac_clk */ 1356 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1357 /* mac_rxer */ 1358 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1359 /* mac_rxdv */ 1360 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1361 /* mac_mdc */ 1362 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1363 /* mac_rxd1 */ 1364 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1365 /* mac_rxd0 */ 1366 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1367 /* mac_txd1 */ 1368 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1369 /* mac_txd0 */ 1370 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1371 }; 1372 }; 1373 1374 gmac-1 { 1375 rgmiim1_pins: rgmiim1-pins { 1376 rockchip,pins = 1377 /* mac_txclk */ 1378 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1379 /* mac_rxclk */ 1380 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1381 /* mac_mdio */ 1382 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1383 /* mac_txen */ 1384 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1385 /* mac_clk */ 1386 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1387 /* mac_rxdv */ 1388 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1389 /* mac_mdc */ 1390 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1391 /* mac_rxd1 */ 1392 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1393 /* mac_rxd0 */ 1394 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1395 /* mac_txd1 */ 1396 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1397 /* mac_txd0 */ 1398 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1399 /* mac_rxd3 */ 1400 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1401 /* mac_rxd2 */ 1402 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1403 /* mac_txd3 */ 1404 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1405 /* mac_txd2 */ 1406 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1407 1408 /* mac_txclk */ 1409 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1410 /* mac_txen */ 1411 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1412 /* mac_clk */ 1413 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1414 /* mac_txd1 */ 1415 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1416 /* mac_txd0 */ 1417 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1418 /* mac_txd3 */ 1419 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1420 /* mac_txd2 */ 1421 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1422 }; 1423 1424 rmiim1_pins: rmiim1-pins { 1425 rockchip,pins = 1426 /* mac_mdio */ 1427 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1428 /* mac_txen */ 1429 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1430 /* mac_clk */ 1431 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1432 /* mac_rxer */ 1433 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1434 /* mac_rxdv */ 1435 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1436 /* mac_mdc */ 1437 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1438 /* mac_rxd1 */ 1439 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1440 /* mac_rxd0 */ 1441 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1442 /* mac_txd1 */ 1443 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1444 /* mac_txd0 */ 1445 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1446 1447 /* mac_mdio */ 1448 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1449 /* mac_txen */ 1450 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1451 /* mac_clk */ 1452 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1453 /* mac_mdc */ 1454 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1455 /* mac_txd1 */ 1456 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1457 /* mac_txd0 */ 1458 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1459 }; 1460 }; 1461 1462 gmac2phy { 1463 fephyled_speed100: fephyled-speed100 { 1464 rockchip,pins = 1465 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1466 }; 1467 1468 fephyled_speed10: fephyled-speed10 { 1469 rockchip,pins = 1470 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1471 }; 1472 1473 fephyled_duplex: fephyled-duplex { 1474 rockchip,pins = 1475 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1476 }; 1477 1478 fephyled_rxm0: fephyled-rxm0 { 1479 rockchip,pins = 1480 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1481 }; 1482 1483 fephyled_txm0: fephyled-txm0 { 1484 rockchip,pins = 1485 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1486 }; 1487 1488 fephyled_linkm0: fephyled-linkm0 { 1489 rockchip,pins = 1490 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1491 }; 1492 1493 fephyled_rxm1: fephyled-rxm1 { 1494 rockchip,pins = 1495 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1496 }; 1497 1498 fephyled_txm1: fephyled-txm1 { 1499 rockchip,pins = 1500 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1501 }; 1502 1503 fephyled_linkm1: fephyled-linkm1 { 1504 rockchip,pins = 1505 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1506 }; 1507 }; 1508 1509 tsadc_pin { 1510 tsadc_int: tsadc-int { 1511 rockchip,pins = 1512 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1513 }; 1514 tsadc_gpio: tsadc-gpio { 1515 rockchip,pins = 1516 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1517 }; 1518 }; 1519 1520 hdmi_pin { 1521 hdmi_cec: hdmi-cec { 1522 rockchip,pins = 1523 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1524 }; 1525 1526 hdmi_hpd: hdmi-hpd { 1527 rockchip,pins = 1528 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1529 }; 1530 }; 1531 1532 cif-0 { 1533 dvp_d2d9_m0:dvp-d2d9-m0 { 1534 rockchip,pins = 1535 /* cif_d0 */ 1536 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1537 /* cif_d1 */ 1538 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1539 /* cif_d2 */ 1540 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1541 /* cif_d3 */ 1542 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1543 /* cif_d4 */ 1544 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1545 /* cif_d5m0 */ 1546 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1547 /* cif_d6m0 */ 1548 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1549 /* cif_d7m0 */ 1550 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1551 /* cif_href */ 1552 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1553 /* cif_vsync */ 1554 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1555 /* cif_clkoutm0 */ 1556 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1557 /* cif_clkin */ 1558 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1559 }; 1560 }; 1561 1562 cif-1 { 1563 dvp_d2d9_m1:dvp-d2d9-m1 { 1564 rockchip,pins = 1565 /* cif_d0 */ 1566 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1567 /* cif_d1 */ 1568 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1569 /* cif_d2 */ 1570 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1571 /* cif_d3 */ 1572 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1573 /* cif_d4 */ 1574 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1575 /* cif_d5m1 */ 1576 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1577 /* cif_d6m1 */ 1578 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1579 /* cif_d7m1 */ 1580 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1581 /* cif_href */ 1582 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1583 /* cif_vsync */ 1584 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1585 /* cif_clkoutm1 */ 1586 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1587 /* cif_clkin */ 1588 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1589 }; 1590 }; 1591 }; 1592}; 1593