1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 grf: syscon@ff100000 { 190 u-boot,dm-pre-reloc; 191 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 192 reg = <0x0 0xff100000 0x0 0x1000>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 196 io_domains: io-domains { 197 compatible = "rockchip,rk3328-io-voltage-domain"; 198 status = "disabled"; 199 }; 200 }; 201 202 uart0: serial@ff110000 { 203 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 204 reg = <0x0 0xff110000 0x0 0x100>; 205 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 207 clock-names = "baudclk", "apb_pclk"; 208 reg-shift = <2>; 209 reg-io-width = <4>; 210 dmas = <&dmac 2>, <&dmac 3>; 211 #dma-cells = <2>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 214 status = "disabled"; 215 }; 216 217 uart1: serial@ff120000 { 218 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 219 reg = <0x0 0xff120000 0x0 0x100>; 220 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 222 clock-names = "sclk_uart", "pclk_uart"; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 dmas = <&dmac 4>, <&dmac 5>; 226 #dma-cells = <2>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 229 status = "disabled"; 230 }; 231 232 uart2: serial@ff130000 { 233 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 234 reg = <0x0 0xff130000 0x0 0x100>; 235 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 237 clock-names = "baudclk", "apb_pclk"; 238 clock-frequency = <24000000>; 239 reg-shift = <2>; 240 reg-io-width = <4>; 241 dmas = <&dmac 6>, <&dmac 7>; 242 #dma-cells = <2>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&uart2m1_xfer>; 245 status = "disabled"; 246 }; 247 248 pmu: power-management@ff140000 { 249 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 250 reg = <0x0 0xff140000 0x0 0x1000>; 251 }; 252 253 i2c0: i2c@ff150000 { 254 compatible = "rockchip,rk3328-i2c"; 255 reg = <0x0 0xff150000 0x0 0x1000>; 256 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 260 clock-names = "i2c", "pclk"; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&i2c0_xfer>; 263 status = "disabled"; 264 }; 265 266 i2c1: i2c@ff160000 { 267 compatible = "rockchip,rk3328-i2c"; 268 reg = <0x0 0xff160000 0x0 0x1000>; 269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 273 clock-names = "i2c", "pclk"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&i2c1_xfer>; 276 status = "disabled"; 277 }; 278 279 i2c2: i2c@ff170000 { 280 compatible = "rockchip,rk3328-i2c"; 281 reg = <0x0 0xff170000 0x0 0x1000>; 282 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 286 clock-names = "i2c", "pclk"; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&i2c2_xfer>; 289 status = "disabled"; 290 }; 291 292 i2c3: i2c@ff180000 { 293 compatible = "rockchip,rk3328-i2c"; 294 reg = <0x0 0xff180000 0x0 0x1000>; 295 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 299 clock-names = "i2c", "pclk"; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c3_xfer>; 302 status = "disabled"; 303 }; 304 305 spi0: spi@ff190000 { 306 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 307 reg = <0x0 0xff190000 0x0 0x1000>; 308 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 312 clock-names = "spiclk", "apb_pclk"; 313 dmas = <&dmac 8>, <&dmac 9>; 314 #dma-cells = <2>; 315 dma-names = "tx", "rx"; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 318 status = "disabled"; 319 }; 320 321 wdt: watchdog@ff1a0000 { 322 compatible = "snps,dw-wdt"; 323 reg = <0x0 0xff1a0000 0x0 0x100>; 324 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 325 status = "disabled"; 326 }; 327 328 amba { 329 compatible = "simple-bus"; 330 #address-cells = <2>; 331 #size-cells = <2>; 332 ranges; 333 334 dmac: dmac@ff1f0000 { 335 compatible = "arm,pl330", "arm,primecell"; 336 reg = <0x0 0xff1f0000 0x0 0x4000>; 337 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&cru ACLK_DMAC>; 340 clock-names = "apb_pclk"; 341 #dma-cells = <1>; 342 }; 343 }; 344 345 saradc: saradc@ff280000 { 346 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 347 reg = <0x0 0xff280000 0x0 0x100>; 348 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 349 #io-channel-cells = <1>; 350 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 351 clock-names = "saradc", "apb_pclk"; 352 resets = <&cru SRST_SARADC_P>; 353 reset-names = "saradc-apb"; 354 status = "disabled"; 355 }; 356 357 dmc: dmc { 358 u-boot,dm-pre-reloc; 359 compatible = "rockchip,rk3328-dmc"; 360 reg = <0x0 0xff400000 0x0 0x1000 361 0x0 0xff780000 0x0 0x3000 362 0x0 0xff100000 0x0 0x1000 363 0x0 0xff440000 0x0 0x1000 364 0x0 0xff720000 0x0 0x1000 365 0x0 0xff798000 0x0 0x1000>; 366 }; 367 368 cru: clock-controller@ff440000 { 369 u-boot,dm-pre-reloc; 370 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 371 reg = <0x0 0xff440000 0x0 0x1000>; 372 rockchip,grf = <&grf>; 373 #clock-cells = <1>; 374 #reset-cells = <1>; 375 assigned-clocks = 376 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 377 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 378 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 379 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 380 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 381 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 382 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 383 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 384 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 385 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 386 <&cru SCLK_WIFI>, <&cru ARMCLK>, 387 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 388 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 389 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 390 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 391 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 392 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 393 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 394 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 395 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 396 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 397 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 398 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 399 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 400 assigned-clock-parents = 401 <&cru HDMIPHY>, <&cru PLL_APLL>, 402 <&cru PLL_GPLL>, <&xin24m>, 403 <&xin24m>, <&xin24m>; 404 assigned-clock-rates = 405 <0>, <61440000>, 406 <0>, <24000000>, 407 <24000000>, <24000000>, 408 <15000000>, <15000000>, 409 <100000000>, <100000000>, 410 <100000000>, <100000000>, 411 <50000000>, <100000000>, 412 <100000000>, <100000000>, 413 <50000000>, <50000000>, 414 <50000000>, <50000000>, 415 <24000000>, <600000000>, 416 <491520000>, <1200000000>, 417 <150000000>, <75000000>, 418 <75000000>, <150000000>, 419 <75000000>, <75000000>, 420 <300000000>, <100000000>, 421 <300000000>, <200000000>, 422 <400000000>, <500000000>, 423 <200000000>, <300000000>, 424 <300000000>, <250000000>, 425 <200000000>, <100000000>, 426 <24000000>, <100000000>, 427 <150000000>, <50000000>, 428 <32768>, <32768>; 429 }; 430 431 usb2phy_grf: syscon-usb@ff450000 { 432 compatible = "rockchip,rk3328-usb2phy-grf", 433 "simple-mfd", "syscon"; 434 reg = <0x0 0xff450000 0x0 0x10000>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 438 u2phy: usb2-phy@100 { 439 compatible = "rockchip,rk3328-usb2phy"; 440 reg = <0x100 0x10>; 441 clocks = <&xin24m>; 442 clock-names = "phyclk"; 443 clock-output-names = "usb480m_phy"; 444 #clock-cells = <0>; 445 assigned-clocks = <&cru USB480M>; 446 assigned-clock-parents = <&u2phy>; 447 #phy-cells = <1>; 448 status = "disabled"; 449 450 u2phy_otg: otg-port { 451 #phy-cells = <0>; 452 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 455 interrupt-names = "otg-bvalid", "otg-id", 456 "linestate"; 457 status = "disabled"; 458 }; 459 460 u2phy_host: host-port { 461 #phy-cells = <0>; 462 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "linestate"; 464 status = "disabled"; 465 }; 466 }; 467 }; 468 469 sdmmc: rksdmmc@ff500000 { 470 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 471 reg = <0x0 0xff500000 0x0 0x4000>; 472 max-frequency = <150000000>; 473 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 474 clock-names = "biu", "ciu"; 475 fifo-depth = <0x100>; 476 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 477 status = "disabled"; 478 }; 479 480 sdio: dwmmc@ff510000 { 481 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 482 reg = <0x0 0xff510000 0x0 0x4000>; 483 max-frequency = <150000000>; 484 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 485 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 486 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 487 fifo-depth = <0x100>; 488 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 489 status = "disabled"; 490 }; 491 492 emmc: rksdmmc@ff520000 { 493 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 494 reg = <0x0 0xff520000 0x0 0x4000>; 495 max-frequency = <150000000>; 496 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 497 clock-names = "biu", "ciu"; 498 fifo-depth = <0x100>; 499 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 500 status = "disabled"; 501 }; 502 503 usb_host0_ehci: usb@ff5c0000 { 504 compatible = "generic-ehci"; 505 reg = <0x0 0xff5c0000 0x0 0x10000>; 506 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 507 phys = <&u2phy 1>; 508 phy-names = "usb"; 509 status = "disabled"; 510 }; 511 512 usb_host0_ohci: usb@ff5d0000 { 513 compatible = "generic-ohci"; 514 reg = <0x0 0xff5d0000 0x0 0x10000>; 515 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 516 phys = <&u2phy 1>; 517 phy-names = "usb"; 518 status = "disabled"; 519 }; 520 521 usb20_otg: usb@ff580000 { 522 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 523 "snps,dwc2"; 524 reg = <0x0 0xff580000 0x0 0x40000>; 525 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 526 hnp-srp-disable; 527 dr_mode = "otg"; 528 phys = <&u2phy 0>; 529 phy-names = "usb"; 530 status = "disabled"; 531 }; 532 533 sdmmc_ext: rksdmmc@ff5f0000 { 534 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 535 reg = <0x0 0xff5f0000 0x0 0x4000>; 536 max-frequency = <150000000>; 537 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 538 clock-names = "biu", "ciu"; 539 fifo-depth = <0x100>; 540 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 541 status = "disabled"; 542 }; 543 544 usb_host0_xhci: usb@ff600000 { 545 compatible = "rockchip,rk3328-xhci"; 546 reg = <0x0 0xff600000 0x0 0x100000>; 547 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 548 snps,dis-enblslpm-quirk; 549 snps,phyif-utmi-bits = <16>; 550 snps,dis-u2-freeclk-exists-quirk; 551 snps,dis-u2-susphy-quirk; 552 status = "disabled"; 553 }; 554 555 gic: interrupt-controller@ffb70000 { 556 compatible = "arm,gic-400"; 557 #interrupt-cells = <3>; 558 #address-cells = <0>; 559 interrupt-controller; 560 reg = <0x0 0xff811000 0 0x1000>, 561 <0x0 0xff812000 0 0x2000>, 562 <0x0 0xff814000 0 0x2000>, 563 <0x0 0xff816000 0 0x2000>; 564 interrupts = <GIC_PPI 9 565 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 566 }; 567 568 pinctrl: pinctrl { 569 compatible = "rockchip,rk3328-pinctrl"; 570 rockchip,grf = <&grf>; 571 #address-cells = <2>; 572 #size-cells = <2>; 573 ranges; 574 575 gpio0: gpio0@ff210000 { 576 compatible = "rockchip,gpio-bank"; 577 reg = <0x0 0xff210000 0x0 0x100>; 578 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&cru PCLK_GPIO0>; 580 581 gpio-controller; 582 #gpio-cells = <2>; 583 584 interrupt-controller; 585 #interrupt-cells = <2>; 586 }; 587 588 gpio1: gpio1@ff220000 { 589 compatible = "rockchip,gpio-bank"; 590 reg = <0x0 0xff220000 0x0 0x100>; 591 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cru PCLK_GPIO1>; 593 594 gpio-controller; 595 #gpio-cells = <2>; 596 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 }; 600 601 gpio2: gpio2@ff230000 { 602 compatible = "rockchip,gpio-bank"; 603 reg = <0x0 0xff230000 0x0 0x100>; 604 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cru PCLK_GPIO2>; 606 607 gpio-controller; 608 #gpio-cells = <2>; 609 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 }; 613 614 gpio3: gpio3@ff240000 { 615 compatible = "rockchip,gpio-bank"; 616 reg = <0x0 0xff240000 0x0 0x100>; 617 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&cru PCLK_GPIO3>; 619 620 gpio-controller; 621 #gpio-cells = <2>; 622 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 }; 626 627 pcfg_pull_up: pcfg-pull-up { 628 bias-pull-up; 629 }; 630 631 pcfg_pull_down: pcfg-pull-down { 632 bias-pull-down; 633 }; 634 635 pcfg_pull_none: pcfg-pull-none { 636 bias-disable; 637 }; 638 639 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 640 bias-disable; 641 drive-strength = <2>; 642 }; 643 644 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 645 bias-pull-up; 646 drive-strength = <2>; 647 }; 648 649 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 650 bias-pull-up; 651 drive-strength = <4>; 652 }; 653 654 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 655 bias-disable; 656 drive-strength = <4>; 657 }; 658 659 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 660 bias-pull-down; 661 drive-strength = <4>; 662 }; 663 664 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 665 bias-disable; 666 drive-strength = <8>; 667 }; 668 669 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 670 bias-pull-up; 671 drive-strength = <8>; 672 }; 673 674 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 675 bias-disable; 676 drive-strength = <12>; 677 }; 678 679 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 680 bias-pull-up; 681 drive-strength = <12>; 682 }; 683 684 pcfg_output_high: pcfg-output-high { 685 output-high; 686 }; 687 688 pcfg_output_low: pcfg-output-low { 689 output-low; 690 }; 691 692 pcfg_input_high: pcfg-input-high { 693 bias-pull-up; 694 input-enable; 695 }; 696 697 pcfg_input: pcfg-input { 698 input-enable; 699 }; 700 701 i2c0 { 702 i2c0_xfer: i2c0-xfer { 703 rockchip,pins = 704 <2 24 RK_FUNC_1 &pcfg_pull_none>, 705 <2 25 RK_FUNC_1 &pcfg_pull_none>; 706 }; 707 }; 708 709 i2c1 { 710 i2c1_xfer: i2c1-xfer { 711 rockchip,pins = 712 <2 4 RK_FUNC_2 &pcfg_pull_none>, 713 <2 5 RK_FUNC_2 &pcfg_pull_none>; 714 }; 715 }; 716 717 i2c2 { 718 i2c2_xfer: i2c2-xfer { 719 rockchip,pins = 720 <2 13 RK_FUNC_1 &pcfg_pull_none>, 721 <2 14 RK_FUNC_1 &pcfg_pull_none>; 722 }; 723 }; 724 725 i2c3 { 726 i2c3_xfer: i2c3-xfer { 727 rockchip,pins = 728 <0 5 RK_FUNC_2 &pcfg_pull_none>, 729 <0 6 RK_FUNC_2 &pcfg_pull_none>; 730 }; 731 i2c3_gpio: i2c3-gpio { 732 rockchip,pins = 733 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 734 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 735 }; 736 }; 737 738 hdmi_i2c { 739 hdmii2c_xfer: hdmii2c-xfer { 740 rockchip,pins = 741 <0 5 RK_FUNC_1 &pcfg_pull_none>, 742 <0 6 RK_FUNC_1 &pcfg_pull_none>; 743 }; 744 }; 745 746 uart0 { 747 uart0_xfer: uart0-xfer { 748 rockchip,pins = 749 <1 9 RK_FUNC_1 &pcfg_pull_up>, 750 <1 8 RK_FUNC_1 &pcfg_pull_none>; 751 }; 752 753 uart0_cts: uart0-cts { 754 rockchip,pins = 755 <1 11 RK_FUNC_1 &pcfg_pull_none>; 756 }; 757 758 uart0_rts: uart0-rts { 759 rockchip,pins = 760 <1 10 RK_FUNC_1 &pcfg_pull_none>; 761 }; 762 763 uart0_rts_gpio: uart0-rts-gpio { 764 rockchip,pins = 765 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 766 }; 767 }; 768 769 uart1 { 770 uart1_xfer: uart1-xfer { 771 rockchip,pins = 772 <3 4 RK_FUNC_4 &pcfg_pull_up>, 773 <3 6 RK_FUNC_4 &pcfg_pull_none>; 774 }; 775 776 uart1_cts: uart1-cts { 777 rockchip,pins = 778 <3 7 RK_FUNC_4 &pcfg_pull_none>; 779 }; 780 781 uart1_rts: uart1-rts { 782 rockchip,pins = 783 <3 5 RK_FUNC_4 &pcfg_pull_none>; 784 }; 785 786 uart1_rts_gpio: uart1-rts-gpio { 787 rockchip,pins = 788 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 789 }; 790 }; 791 792 uart2-0 { 793 uart2m0_xfer: uart2m0-xfer { 794 rockchip,pins = 795 <1 0 RK_FUNC_2 &pcfg_pull_up>, 796 <1 1 RK_FUNC_2 &pcfg_pull_none>; 797 }; 798 }; 799 800 uart2-1 { 801 uart2m1_xfer: uart2m1-xfer { 802 rockchip,pins = 803 <2 0 RK_FUNC_1 &pcfg_pull_up>, 804 <2 1 RK_FUNC_1 &pcfg_pull_none>; 805 }; 806 }; 807 808 spi0-0 { 809 spi0m0_clk: spi0m0-clk { 810 rockchip,pins = 811 <2 8 RK_FUNC_1 &pcfg_pull_up>; 812 }; 813 814 spi0m0_cs0: spi0m0-cs0 { 815 rockchip,pins = 816 <2 11 RK_FUNC_1 &pcfg_pull_up>; 817 }; 818 819 spi0m0_tx: spi0m0-tx { 820 rockchip,pins = 821 <2 9 RK_FUNC_1 &pcfg_pull_up>; 822 }; 823 824 spi0m0_rx: spi0m0-rx { 825 rockchip,pins = 826 <2 10 RK_FUNC_1 &pcfg_pull_up>; 827 }; 828 829 spi0m0_cs1: spi0m0-cs1 { 830 rockchip,pins = 831 <2 12 RK_FUNC_1 &pcfg_pull_up>; 832 }; 833 }; 834 835 spi0-1 { 836 spi0m1_clk: spi0m1-clk { 837 rockchip,pins = 838 <3 23 RK_FUNC_2 &pcfg_pull_up>; 839 }; 840 841 spi0m1_cs0: spi0m1-cs0 { 842 rockchip,pins = 843 <3 26 RK_FUNC_2 &pcfg_pull_up>; 844 }; 845 846 spi0m1_tx: spi0m1-tx { 847 rockchip,pins = 848 <3 25 RK_FUNC_2 &pcfg_pull_up>; 849 }; 850 851 spi0m1_rx: spi0m1-rx { 852 rockchip,pins = 853 <3 24 RK_FUNC_2 &pcfg_pull_up>; 854 }; 855 856 spi0m1_cs1: spi0m1-cs1 { 857 rockchip,pins = 858 <3 27 RK_FUNC_2 &pcfg_pull_up>; 859 }; 860 }; 861 862 spi0-2 { 863 spi0m2_clk: spi0m2-clk { 864 rockchip,pins = 865 <3 0 RK_FUNC_4 &pcfg_pull_up>; 866 }; 867 868 spi0m2_cs0: spi0m2-cs0 { 869 rockchip,pins = 870 <3 8 RK_FUNC_3 &pcfg_pull_up>; 871 }; 872 873 spi0m2_tx: spi0m2-tx { 874 rockchip,pins = 875 <3 1 RK_FUNC_4 &pcfg_pull_up>; 876 }; 877 878 spi0m2_rx: spi0m2-rx { 879 rockchip,pins = 880 <3 2 RK_FUNC_4 &pcfg_pull_up>; 881 }; 882 }; 883 884 i2s1 { 885 i2s1_mclk: i2s1-mclk { 886 rockchip,pins = 887 <2 15 RK_FUNC_1 &pcfg_pull_none>; 888 }; 889 890 i2s1_sclk: i2s1-sclk { 891 rockchip,pins = 892 <2 18 RK_FUNC_1 &pcfg_pull_none>; 893 }; 894 895 i2s1_lrckrx: i2s1-lrckrx { 896 rockchip,pins = 897 <2 16 RK_FUNC_1 &pcfg_pull_none>; 898 }; 899 900 i2s1_lrcktx: i2s1-lrcktx { 901 rockchip,pins = 902 <2 17 RK_FUNC_1 &pcfg_pull_none>; 903 }; 904 905 i2s1_sdi: i2s1-sdi { 906 rockchip,pins = 907 <2 19 RK_FUNC_1 &pcfg_pull_none>; 908 }; 909 910 i2s1_sdo: i2s1-sdo { 911 rockchip,pins = 912 <2 23 RK_FUNC_1 &pcfg_pull_none>; 913 }; 914 915 i2s1_sdio1: i2s1-sdio1 { 916 rockchip,pins = 917 <2 20 RK_FUNC_1 &pcfg_pull_none>; 918 }; 919 920 i2s1_sdio2: i2s1-sdio2 { 921 rockchip,pins = 922 <2 21 RK_FUNC_1 &pcfg_pull_none>; 923 }; 924 925 i2s1_sdio3: i2s1-sdio3 { 926 rockchip,pins = 927 <2 22 RK_FUNC_1 &pcfg_pull_none>; 928 }; 929 930 i2s1_sleep: i2s1-sleep { 931 rockchip,pins = 932 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 933 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 934 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 935 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 936 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 937 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 938 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 939 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 940 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 941 }; 942 }; 943 944 i2s2-0 { 945 i2s2m0_mclk: i2s2m0-mclk { 946 rockchip,pins = 947 <1 21 RK_FUNC_1 &pcfg_pull_none>; 948 }; 949 950 i2s2m0_sclk: i2s2m0-sclk { 951 rockchip,pins = 952 <1 22 RK_FUNC_1 &pcfg_pull_none>; 953 }; 954 955 i2s2m0_lrckrx: i2s2m0-lrckrx { 956 rockchip,pins = 957 <1 26 RK_FUNC_1 &pcfg_pull_none>; 958 }; 959 960 i2s2m0_lrcktx: i2s2m0-lrcktx { 961 rockchip,pins = 962 <1 23 RK_FUNC_1 &pcfg_pull_none>; 963 }; 964 965 i2s2m0_sdi: i2s2m0-sdi { 966 rockchip,pins = 967 <1 24 RK_FUNC_1 &pcfg_pull_none>; 968 }; 969 970 i2s2m0_sdo: i2s2m0-sdo { 971 rockchip,pins = 972 <1 25 RK_FUNC_1 &pcfg_pull_none>; 973 }; 974 975 i2s2m0_sleep: i2s2m0-sleep { 976 rockchip,pins = 977 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 978 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 979 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 980 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 981 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 982 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 983 }; 984 }; 985 986 i2s2-1 { 987 i2s2m1_mclk: i2s2m1-mclk { 988 rockchip,pins = 989 <1 21 RK_FUNC_1 &pcfg_pull_none>; 990 }; 991 992 i2s2m1_sclk: i2s2m1-sclk { 993 rockchip,pins = 994 <3 0 RK_FUNC_6 &pcfg_pull_none>; 995 }; 996 997 i2s2m1_lrckrx: i2sm1-lrckrx { 998 rockchip,pins = 999 <3 8 RK_FUNC_6 &pcfg_pull_none>; 1000 }; 1001 1002 i2s2m1_lrcktx: i2s2m1-lrcktx { 1003 rockchip,pins = 1004 <3 8 RK_FUNC_4 &pcfg_pull_none>; 1005 }; 1006 1007 i2s2m1_sdi: i2s2m1-sdi { 1008 rockchip,pins = 1009 <3 2 RK_FUNC_6 &pcfg_pull_none>; 1010 }; 1011 1012 i2s2m1_sdo: i2s2m1-sdo { 1013 rockchip,pins = 1014 <3 1 RK_FUNC_6 &pcfg_pull_none>; 1015 }; 1016 1017 i2s2m1_sleep: i2s2m1-sleep { 1018 rockchip,pins = 1019 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1020 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 1021 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 1022 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 1023 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 1024 }; 1025 }; 1026 1027 spdif-0 { 1028 spdifm0_tx: spdifm0-tx { 1029 rockchip,pins = 1030 <0 27 RK_FUNC_1 &pcfg_pull_none>; 1031 }; 1032 }; 1033 1034 spdif-1 { 1035 spdifm1_tx: spdifm1-tx { 1036 rockchip,pins = 1037 <2 17 RK_FUNC_2 &pcfg_pull_none>; 1038 }; 1039 }; 1040 1041 spdif-2 { 1042 spdifm2_tx: spdifm2-tx { 1043 rockchip,pins = 1044 <0 2 RK_FUNC_2 &pcfg_pull_none>; 1045 }; 1046 }; 1047 1048 sdmmc0-0 { 1049 sdmmc0m0_pwren: sdmmc0m0-pwren { 1050 rockchip,pins = 1051 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1052 }; 1053 1054 sdmmc0m0_gpio: sdmmc0m0-gpio { 1055 rockchip,pins = 1056 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1057 }; 1058 }; 1059 1060 sdmmc0-1 { 1061 sdmmc0m1_pwren: sdmmc0m1-pwren { 1062 rockchip,pins = 1063 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1064 }; 1065 1066 sdmmc0m1_gpio: sdmmc0m1-gpio { 1067 rockchip,pins = 1068 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1069 }; 1070 }; 1071 1072 sdmmc0 { 1073 sdmmc0_clk: sdmmc0-clk { 1074 rockchip,pins = 1075 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1076 }; 1077 1078 sdmmc0_cmd: sdmmc0-cmd { 1079 rockchip,pins = 1080 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1081 }; 1082 1083 sdmmc0_dectn: sdmmc0-dectn { 1084 rockchip,pins = 1085 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1086 }; 1087 1088 sdmmc0_wrprt: sdmmc0-wrprt { 1089 rockchip,pins = 1090 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1091 }; 1092 1093 sdmmc0_bus1: sdmmc0-bus1 { 1094 rockchip,pins = 1095 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1096 }; 1097 1098 sdmmc0_bus4: sdmmc0-bus4 { 1099 rockchip,pins = 1100 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1101 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1102 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1103 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1104 }; 1105 1106 sdmmc0_gpio: sdmmc0-gpio { 1107 rockchip,pins = 1108 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1109 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1110 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1111 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1112 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1113 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1114 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1115 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1116 }; 1117 }; 1118 1119 sdmmc0ext { 1120 sdmmc0ext_clk: sdmmc0ext-clk { 1121 rockchip,pins = 1122 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1123 }; 1124 1125 sdmmc0ext_cmd: sdmmc0ext-cmd { 1126 rockchip,pins = 1127 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1128 }; 1129 1130 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1131 rockchip,pins = 1132 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1133 }; 1134 1135 sdmmc0ext_dectn: sdmmc0ext-dectn { 1136 rockchip,pins = 1137 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1138 }; 1139 1140 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1141 rockchip,pins = 1142 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1143 }; 1144 1145 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1146 rockchip,pins = 1147 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1148 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1149 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1150 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1151 }; 1152 1153 sdmmc0ext_gpio: sdmmc0ext-gpio { 1154 rockchip,pins = 1155 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1156 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1157 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1158 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1159 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1160 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1161 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1162 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1163 }; 1164 }; 1165 1166 sdmmc1 { 1167 sdmmc1_clk: sdmmc1-clk { 1168 rockchip,pins = 1169 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1170 }; 1171 1172 sdmmc1_cmd: sdmmc1-cmd { 1173 rockchip,pins = 1174 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1175 }; 1176 1177 sdmmc1_pwren: sdmmc1-pwren { 1178 rockchip,pins = 1179 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1180 }; 1181 1182 sdmmc1_wrprt: sdmmc1-wrprt { 1183 rockchip,pins = 1184 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1185 }; 1186 1187 sdmmc1_dectn: sdmmc1-dectn { 1188 rockchip,pins = 1189 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1190 }; 1191 1192 sdmmc1_bus1: sdmmc1-bus1 { 1193 rockchip,pins = 1194 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1195 }; 1196 1197 sdmmc1_bus4: sdmmc1-bus4 { 1198 rockchip,pins = 1199 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1200 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1201 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1202 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1203 }; 1204 1205 sdmmc1_gpio: sdmmc1-gpio { 1206 rockchip,pins = 1207 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1208 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1209 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1210 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1211 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1212 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1213 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1214 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1215 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1216 }; 1217 }; 1218 1219 emmc { 1220 emmc_clk: emmc-clk { 1221 rockchip,pins = 1222 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1223 }; 1224 1225 emmc_cmd: emmc-cmd { 1226 rockchip,pins = 1227 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1228 }; 1229 1230 emmc_pwren: emmc-pwren { 1231 rockchip,pins = 1232 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1233 }; 1234 1235 emmc_rstnout: emmc-rstnout { 1236 rockchip,pins = 1237 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1238 }; 1239 1240 emmc_bus1: emmc-bus1 { 1241 rockchip,pins = 1242 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1243 }; 1244 1245 emmc_bus4: emmc-bus4 { 1246 rockchip,pins = 1247 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1248 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1249 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1250 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1251 }; 1252 1253 emmc_bus8: emmc-bus8 { 1254 rockchip,pins = 1255 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1256 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1257 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1258 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1259 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1260 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1261 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1262 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1263 }; 1264 }; 1265 1266 pwm0 { 1267 pwm0_pin: pwm0-pin { 1268 rockchip,pins = 1269 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1270 }; 1271 }; 1272 1273 pwm1 { 1274 pwm1_pin: pwm1-pin { 1275 rockchip,pins = 1276 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1277 }; 1278 }; 1279 1280 pwm2 { 1281 pwm2_pin: pwm2-pin { 1282 rockchip,pins = 1283 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1284 }; 1285 }; 1286 1287 pwmir { 1288 pwmir_pin: pwmir-pin { 1289 rockchip,pins = 1290 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1291 }; 1292 }; 1293 1294 gmac-0 { 1295 rgmiim0_pins: rgmiim0-pins { 1296 rockchip,pins = 1297 /* mac_txclk */ 1298 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1299 /* mac_rxclk */ 1300 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1301 /* mac_mdio */ 1302 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1303 /* mac_txen */ 1304 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1305 /* mac_clk */ 1306 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1307 /* mac_rxdv */ 1308 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1309 /* mac_mdc */ 1310 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1311 /* mac_rxd1 */ 1312 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1313 /* mac_rxd0 */ 1314 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1315 /* mac_txd1 */ 1316 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1317 /* mac_txd0 */ 1318 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1319 /* mac_rxd3 */ 1320 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1321 /* mac_rxd2 */ 1322 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1323 /* mac_txd3 */ 1324 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1325 /* mac_txd2 */ 1326 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1327 }; 1328 1329 rmiim0_pins: rmiim0-pins { 1330 rockchip,pins = 1331 /* mac_mdio */ 1332 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1333 /* mac_txen */ 1334 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1335 /* mac_clk */ 1336 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1337 /* mac_rxer */ 1338 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1339 /* mac_rxdv */ 1340 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1341 /* mac_mdc */ 1342 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1343 /* mac_rxd1 */ 1344 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1345 /* mac_rxd0 */ 1346 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1347 /* mac_txd1 */ 1348 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1349 /* mac_txd0 */ 1350 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1351 }; 1352 }; 1353 1354 gmac-1 { 1355 rgmiim1_pins: rgmiim1-pins { 1356 rockchip,pins = 1357 /* mac_txclk */ 1358 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1359 /* mac_rxclk */ 1360 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1361 /* mac_mdio */ 1362 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1363 /* mac_txen */ 1364 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1365 /* mac_clk */ 1366 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1367 /* mac_rxdv */ 1368 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1369 /* mac_mdc */ 1370 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1371 /* mac_rxd1 */ 1372 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1373 /* mac_rxd0 */ 1374 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1375 /* mac_txd1 */ 1376 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1377 /* mac_txd0 */ 1378 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1379 /* mac_rxd3 */ 1380 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1381 /* mac_rxd2 */ 1382 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1383 /* mac_txd3 */ 1384 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1385 /* mac_txd2 */ 1386 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1387 1388 /* mac_txclk */ 1389 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1390 /* mac_txen */ 1391 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1392 /* mac_clk */ 1393 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1394 /* mac_txd1 */ 1395 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1396 /* mac_txd0 */ 1397 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1398 /* mac_txd3 */ 1399 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1400 /* mac_txd2 */ 1401 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1402 }; 1403 1404 rmiim1_pins: rmiim1-pins { 1405 rockchip,pins = 1406 /* mac_mdio */ 1407 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1408 /* mac_txen */ 1409 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1410 /* mac_clk */ 1411 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1412 /* mac_rxer */ 1413 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1414 /* mac_rxdv */ 1415 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1416 /* mac_mdc */ 1417 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1418 /* mac_rxd1 */ 1419 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1420 /* mac_rxd0 */ 1421 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1422 /* mac_txd1 */ 1423 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1424 /* mac_txd0 */ 1425 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1426 1427 /* mac_mdio */ 1428 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1429 /* mac_txen */ 1430 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1431 /* mac_clk */ 1432 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1433 /* mac_mdc */ 1434 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1435 /* mac_txd1 */ 1436 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1437 /* mac_txd0 */ 1438 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1439 }; 1440 }; 1441 1442 gmac2phy { 1443 fephyled_speed100: fephyled-speed100 { 1444 rockchip,pins = 1445 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1446 }; 1447 1448 fephyled_speed10: fephyled-speed10 { 1449 rockchip,pins = 1450 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1451 }; 1452 1453 fephyled_duplex: fephyled-duplex { 1454 rockchip,pins = 1455 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1456 }; 1457 1458 fephyled_rxm0: fephyled-rxm0 { 1459 rockchip,pins = 1460 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1461 }; 1462 1463 fephyled_txm0: fephyled-txm0 { 1464 rockchip,pins = 1465 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1466 }; 1467 1468 fephyled_linkm0: fephyled-linkm0 { 1469 rockchip,pins = 1470 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1471 }; 1472 1473 fephyled_rxm1: fephyled-rxm1 { 1474 rockchip,pins = 1475 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1476 }; 1477 1478 fephyled_txm1: fephyled-txm1 { 1479 rockchip,pins = 1480 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1481 }; 1482 1483 fephyled_linkm1: fephyled-linkm1 { 1484 rockchip,pins = 1485 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1486 }; 1487 }; 1488 1489 tsadc_pin { 1490 tsadc_int: tsadc-int { 1491 rockchip,pins = 1492 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1493 }; 1494 tsadc_gpio: tsadc-gpio { 1495 rockchip,pins = 1496 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1497 }; 1498 }; 1499 1500 hdmi_pin { 1501 hdmi_cec: hdmi-cec { 1502 rockchip,pins = 1503 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1504 }; 1505 1506 hdmi_hpd: hdmi-hpd { 1507 rockchip,pins = 1508 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1509 }; 1510 }; 1511 1512 cif-0 { 1513 dvp_d2d9_m0:dvp-d2d9-m0 { 1514 rockchip,pins = 1515 /* cif_d0 */ 1516 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1517 /* cif_d1 */ 1518 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1519 /* cif_d2 */ 1520 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1521 /* cif_d3 */ 1522 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1523 /* cif_d4 */ 1524 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1525 /* cif_d5m0 */ 1526 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1527 /* cif_d6m0 */ 1528 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1529 /* cif_d7m0 */ 1530 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1531 /* cif_href */ 1532 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1533 /* cif_vsync */ 1534 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1535 /* cif_clkoutm0 */ 1536 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1537 /* cif_clkin */ 1538 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1539 }; 1540 }; 1541 1542 cif-1 { 1543 dvp_d2d9_m1:dvp-d2d9-m1 { 1544 rockchip,pins = 1545 /* cif_d0 */ 1546 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1547 /* cif_d1 */ 1548 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1549 /* cif_d2 */ 1550 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1551 /* cif_d3 */ 1552 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1553 /* cif_d4 */ 1554 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1555 /* cif_d5m1 */ 1556 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1557 /* cif_d6m1 */ 1558 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1559 /* cif_d7m1 */ 1560 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1561 /* cif_href */ 1562 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1563 /* cif_vsync */ 1564 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1565 /* cif_clkoutm1 */ 1566 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1567 /* cif_clkin */ 1568 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1569 }; 1570 }; 1571 }; 1572}; 1573