1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 crypto: crypto@ff060000 { 190 compatible = "rockchip,rk322x-crypto"; 191 reg = <0x0 0xff060000 0x0 0x10000>; 192 clock-names = "sclk_crypto"; 193 clocks = <&cru SCLK_CRYPTO>; 194 status = "disabled"; 195 }; 196 197 grf: syscon@ff100000 { 198 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 199 reg = <0x0 0xff100000 0x0 0x1000>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 203 io_domains: io-domains { 204 compatible = "rockchip,rk3328-io-voltage-domain"; 205 status = "disabled"; 206 }; 207 }; 208 209 uart0: serial@ff110000 { 210 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 211 reg = <0x0 0xff110000 0x0 0x100>; 212 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 214 clock-names = "baudclk", "apb_pclk"; 215 reg-shift = <2>; 216 reg-io-width = <4>; 217 dmas = <&dmac 2>, <&dmac 3>; 218 #dma-cells = <2>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 221 status = "disabled"; 222 }; 223 224 uart1: serial@ff120000 { 225 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 226 reg = <0x0 0xff120000 0x0 0x100>; 227 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 229 clock-names = "sclk_uart", "pclk_uart"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 dmas = <&dmac 4>, <&dmac 5>; 233 #dma-cells = <2>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 236 status = "disabled"; 237 }; 238 239 uart2: serial@ff130000 { 240 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 241 reg = <0x0 0xff130000 0x0 0x100>; 242 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 244 clock-names = "baudclk", "apb_pclk"; 245 clock-frequency = <24000000>; 246 reg-shift = <2>; 247 reg-io-width = <4>; 248 dmas = <&dmac 6>, <&dmac 7>; 249 #dma-cells = <2>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&uart2m1_xfer>; 252 status = "disabled"; 253 }; 254 255 pmu: power-management@ff140000 { 256 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 257 reg = <0x0 0xff140000 0x0 0x1000>; 258 }; 259 260 i2c0: i2c@ff150000 { 261 compatible = "rockchip,rk3328-i2c"; 262 reg = <0x0 0xff150000 0x0 0x1000>; 263 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 267 clock-names = "i2c", "pclk"; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&i2c0_xfer>; 270 status = "disabled"; 271 }; 272 273 i2c1: i2c@ff160000 { 274 compatible = "rockchip,rk3328-i2c"; 275 reg = <0x0 0xff160000 0x0 0x1000>; 276 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 280 clock-names = "i2c", "pclk"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2c1_xfer>; 283 status = "disabled"; 284 }; 285 286 i2c2: i2c@ff170000 { 287 compatible = "rockchip,rk3328-i2c"; 288 reg = <0x0 0xff170000 0x0 0x1000>; 289 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 293 clock-names = "i2c", "pclk"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c2_xfer>; 296 status = "disabled"; 297 }; 298 299 i2c3: i2c@ff180000 { 300 compatible = "rockchip,rk3328-i2c"; 301 reg = <0x0 0xff180000 0x0 0x1000>; 302 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 306 clock-names = "i2c", "pclk"; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c3_xfer>; 309 status = "disabled"; 310 }; 311 312 spi0: spi@ff190000 { 313 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 314 reg = <0x0 0xff190000 0x0 0x1000>; 315 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 319 clock-names = "spiclk", "apb_pclk"; 320 dmas = <&dmac 8>, <&dmac 9>; 321 #dma-cells = <2>; 322 dma-names = "tx", "rx"; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 325 status = "disabled"; 326 }; 327 328 wdt: watchdog@ff1a0000 { 329 compatible = "snps,dw-wdt"; 330 reg = <0x0 0xff1a0000 0x0 0x100>; 331 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 332 status = "disabled"; 333 }; 334 335 amba { 336 compatible = "simple-bus"; 337 #address-cells = <2>; 338 #size-cells = <2>; 339 ranges; 340 341 dmac: dmac@ff1f0000 { 342 compatible = "arm,pl330", "arm,primecell"; 343 reg = <0x0 0xff1f0000 0x0 0x4000>; 344 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cru ACLK_DMAC>; 347 clock-names = "apb_pclk"; 348 #dma-cells = <1>; 349 }; 350 }; 351 352 saradc: saradc@ff280000 { 353 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 354 reg = <0x0 0xff280000 0x0 0x100>; 355 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 356 #io-channel-cells = <1>; 357 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 358 clock-names = "saradc", "apb_pclk"; 359 resets = <&cru SRST_SARADC_P>; 360 reset-names = "saradc-apb"; 361 status = "disabled"; 362 }; 363 364 dmc: dmc { 365 compatible = "rockchip,rk3328-dmc"; 366 reg = <0x0 0xff400000 0x0 0x1000 367 0x0 0xff780000 0x0 0x3000 368 0x0 0xff100000 0x0 0x1000 369 0x0 0xff440000 0x0 0x1000 370 0x0 0xff720000 0x0 0x1000 371 0x0 0xff798000 0x0 0x1000>; 372 }; 373 374 cru: clock-controller@ff440000 { 375 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 376 reg = <0x0 0xff440000 0x0 0x1000>; 377 rockchip,grf = <&grf>; 378 #clock-cells = <1>; 379 #reset-cells = <1>; 380 assigned-clocks = 381 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 382 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 383 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 384 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 385 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 386 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 387 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 388 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 389 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 390 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 391 <&cru SCLK_WIFI>, <&cru ARMCLK>, 392 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 393 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 394 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 395 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 396 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 397 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 398 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 399 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 400 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 401 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 402 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 403 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 404 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 405 assigned-clock-parents = 406 <&cru HDMIPHY>, <&cru PLL_APLL>, 407 <&cru PLL_GPLL>, <&xin24m>, 408 <&xin24m>, <&xin24m>; 409 assigned-clock-rates = 410 <0>, <61440000>, 411 <0>, <24000000>, 412 <24000000>, <24000000>, 413 <150000000>, <150000000>, 414 <100000000>, <100000000>, 415 <100000000>, <100000000>, 416 <50000000>, <100000000>, 417 <100000000>, <100000000>, 418 <50000000>, <50000000>, 419 <50000000>, <50000000>, 420 <24000000>, <600000000>, 421 <491520000>, <1200000000>, 422 <150000000>, <75000000>, 423 <75000000>, <150000000>, 424 <75000000>, <75000000>, 425 <300000000>, <100000000>, 426 <300000000>, <200000000>, 427 <400000000>, <500000000>, 428 <200000000>, <300000000>, 429 <300000000>, <250000000>, 430 <200000000>, <100000000>, 431 <24000000>, <100000000>, 432 <150000000>, <50000000>, 433 <32768>, <32768>; 434 }; 435 436 usb2phy_grf: syscon@ff450000 { 437 compatible = "rockchip,rk3328-usb2phy-grf", 438 "simple-mfd", "syscon"; 439 reg = <0x0 0xff450000 0x0 0x10000>; 440 #address-cells = <1>; 441 #size-cells = <1>; 442 443 u2phy: usb2-phy@100 { 444 compatible = "rockchip,rk3328-usb2phy"; 445 reg = <0x100 0x10>; 446 #phy-cells = <1>; 447 status = "disabled"; 448 449 u2phy_host: host-port { 450 #phy-cells = <0>; 451 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 452 interrupt-names = "linestate"; 453 status = "disabled"; 454 }; 455 456 u2phy_otg: otg-port { 457 #phy-cells = <0>; 458 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "otg-bvalid", "otg-id", 462 "linestate"; 463 status = "disabled"; 464 }; 465 }; 466 }; 467 468 usb3phy_grf: syscon@ff460000 { 469 compatible = "rockchip,usb3phy-grf", "syscon"; 470 reg = <0x0 0xff460000 0x0 0x1000>; 471 }; 472 473 u3phy: usb3-phy@ff470000 { 474 compatible = "rockchip,rk3328-u3phy"; 475 reg = <0x0 0xff470000 0x0 0x0>; 476 rockchip,u3phygrf = <&usb3phy_grf>; 477 rockchip,grf = <&grf>; 478 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "linestate"; 480 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; 481 clock-names = "u3phy-otg", "u3phy-pipe"; 482 resets = <&cru SRST_USB3PHY_U2>, 483 <&cru SRST_USB3PHY_U3>, 484 <&cru SRST_USB3PHY_PIPE>, 485 <&cru SRST_USB3OTG_UTMI>, 486 <&cru SRST_USB3PHY_OTG_P>, 487 <&cru SRST_USB3PHY_PIPE_P>; 488 reset-names = "u3phy-u2-por", "u3phy-u3-por", 489 "u3phy-pipe-mac", "u3phy-utmi-mac", 490 "u3phy-utmi-apb", "u3phy-pipe-apb"; 491 #address-cells = <2>; 492 #size-cells = <2>; 493 ranges; 494 status = "disabled"; 495 496 u3phy_utmi: utmi@ff470000 { 497 reg = <0x0 0xff470000 0x0 0x8000>; 498 #phy-cells = <0>; 499 status = "disabled"; 500 }; 501 502 u3phy_pipe: pipe@ff478000 { 503 reg = <0x0 0xff478000 0x0 0x8000>; 504 #phy-cells = <0>; 505 status = "disabled"; 506 }; 507 }; 508 509 sdmmc: rksdmmc@ff500000 { 510 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 511 reg = <0x0 0xff500000 0x0 0x4000>; 512 max-frequency = <150000000>; 513 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 514 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 515 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 516 fifo-depth = <0x100>; 517 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 518 status = "disabled"; 519 }; 520 521 sdio: dwmmc@ff510000 { 522 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 523 reg = <0x0 0xff510000 0x0 0x4000>; 524 max-frequency = <150000000>; 525 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 526 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 527 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 528 fifo-depth = <0x100>; 529 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 530 status = "disabled"; 531 }; 532 533 emmc: rksdmmc@ff520000 { 534 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 535 reg = <0x0 0xff520000 0x0 0x4000>; 536 max-frequency = <150000000>; 537 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 538 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 539 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 540 fifo-depth = <0x100>; 541 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 542 status = "disabled"; 543 }; 544 545 gmac2io: ethernet@ff540000 { 546 compatible = "rockchip,rk3328-gmac"; 547 reg = <0x0 0xff540000 0x0 0x10000>; 548 rockchip,grf = <&grf>; 549 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 550 interrupt-names = "macirq"; 551 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 552 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 553 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 554 <&cru PCLK_MAC2IO>; 555 clock-names = "stmmaceth", "mac_clk_rx", 556 "mac_clk_tx", "clk_mac_ref", 557 "clk_mac_refout", "aclk_mac", 558 "pclk_mac"; 559 resets = <&cru SRST_GMAC2IO_A>; 560 reset-names = "stmmaceth"; 561 status = "disabled"; 562 }; 563 564 usb_host0_ehci: usb@ff5c0000 { 565 compatible = "generic-ehci"; 566 reg = <0x0 0xff5c0000 0x0 0x10000>; 567 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 568 phys = <&u2phy_host>; 569 phy-names = "usb"; 570 status = "disabled"; 571 }; 572 573 usb_host0_ohci: usb@ff5d0000 { 574 compatible = "generic-ohci"; 575 reg = <0x0 0xff5d0000 0x0 0x10000>; 576 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 577 phys = <&u2phy_host>; 578 phy-names = "usb"; 579 status = "disabled"; 580 }; 581 582 usb20_otg: usb@ff580000 { 583 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 584 "snps,dwc2"; 585 reg = <0x0 0xff580000 0x0 0x40000>; 586 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 587 hnp-srp-disable; 588 dr_mode = "otg"; 589 phys = <&u2phy_otg>; 590 phy-names = "usb"; 591 status = "disabled"; 592 }; 593 594 sdmmc_ext: rksdmmc@ff5f0000 { 595 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 596 reg = <0x0 0xff5f0000 0x0 0x4000>; 597 max-frequency = <150000000>; 598 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 599 clock-names = "biu", "ciu"; 600 fifo-depth = <0x100>; 601 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 602 status = "disabled"; 603 }; 604 605 usbdrd3: usb@ff600000 { 606 compatible = "rockchip,rk3328-dwc3"; 607 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 608 <&cru ACLK_USB3OTG>; 609 clock-names = "ref_clk", "suspend_clk", 610 "bus_clk"; 611 #address-cells = <2>; 612 #size-cells = <2>; 613 ranges; 614 status = "disabled"; 615 616 usbdrd_dwc3: dwc3@ff600000 { 617 compatible = "snps,dwc3"; 618 reg = <0x0 0xff600000 0x0 0x100000>; 619 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 620 dr_mode = "host"; 621 phys = <&u3phy_utmi>, <&u3phy_pipe>; 622 phy-names = "usb2-phy", "usb3-phy"; 623 phy_type = "utmi_wide"; 624 snps,dis_enblslpm_quirk; 625 snps,dis-u2-freeclk-exists-quirk; 626 snps,dis_u2_susphy_quirk; 627 snps,dis-u3-autosuspend-quirk; 628 snps,dis_u3_susphy_quirk; 629 snps,dis-del-phy-power-chg-quirk; 630 snps,tx-ipgap-linecheck-dis-quirk; 631 snps,xhci-trb-ent-quirk; 632 status = "disabled"; 633 }; 634 }; 635 636 gic: interrupt-controller@ffb70000 { 637 compatible = "arm,gic-400"; 638 #interrupt-cells = <3>; 639 #address-cells = <0>; 640 interrupt-controller; 641 reg = <0x0 0xff811000 0 0x1000>, 642 <0x0 0xff812000 0 0x2000>, 643 <0x0 0xff814000 0 0x2000>, 644 <0x0 0xff816000 0 0x2000>; 645 interrupts = <GIC_PPI 9 646 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 647 }; 648 649 pinctrl: pinctrl { 650 compatible = "rockchip,rk3328-pinctrl"; 651 rockchip,grf = <&grf>; 652 #address-cells = <2>; 653 #size-cells = <2>; 654 ranges; 655 656 gpio0: gpio0@ff210000 { 657 compatible = "rockchip,gpio-bank"; 658 reg = <0x0 0xff210000 0x0 0x100>; 659 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&cru PCLK_GPIO0>; 661 662 gpio-controller; 663 #gpio-cells = <2>; 664 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 }; 668 669 gpio1: gpio1@ff220000 { 670 compatible = "rockchip,gpio-bank"; 671 reg = <0x0 0xff220000 0x0 0x100>; 672 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru PCLK_GPIO1>; 674 675 gpio-controller; 676 #gpio-cells = <2>; 677 678 interrupt-controller; 679 #interrupt-cells = <2>; 680 }; 681 682 gpio2: gpio2@ff230000 { 683 compatible = "rockchip,gpio-bank"; 684 reg = <0x0 0xff230000 0x0 0x100>; 685 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&cru PCLK_GPIO2>; 687 688 gpio-controller; 689 #gpio-cells = <2>; 690 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 695 gpio3: gpio3@ff240000 { 696 compatible = "rockchip,gpio-bank"; 697 reg = <0x0 0xff240000 0x0 0x100>; 698 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru PCLK_GPIO3>; 700 701 gpio-controller; 702 #gpio-cells = <2>; 703 704 interrupt-controller; 705 #interrupt-cells = <2>; 706 }; 707 708 pcfg_pull_up: pcfg-pull-up { 709 bias-pull-up; 710 }; 711 712 pcfg_pull_down: pcfg-pull-down { 713 bias-pull-down; 714 }; 715 716 pcfg_pull_none: pcfg-pull-none { 717 bias-disable; 718 }; 719 720 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 721 bias-disable; 722 drive-strength = <2>; 723 }; 724 725 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 726 bias-pull-up; 727 drive-strength = <2>; 728 }; 729 730 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 731 bias-pull-up; 732 drive-strength = <4>; 733 }; 734 735 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 736 bias-disable; 737 drive-strength = <4>; 738 }; 739 740 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 741 bias-pull-down; 742 drive-strength = <4>; 743 }; 744 745 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 746 bias-disable; 747 drive-strength = <8>; 748 }; 749 750 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 751 bias-pull-up; 752 drive-strength = <8>; 753 }; 754 755 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 756 bias-disable; 757 drive-strength = <12>; 758 }; 759 760 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 761 bias-pull-up; 762 drive-strength = <12>; 763 }; 764 765 pcfg_output_high: pcfg-output-high { 766 output-high; 767 }; 768 769 pcfg_output_low: pcfg-output-low { 770 output-low; 771 }; 772 773 pcfg_input_high: pcfg-input-high { 774 bias-pull-up; 775 input-enable; 776 }; 777 778 pcfg_input: pcfg-input { 779 input-enable; 780 }; 781 782 i2c0 { 783 i2c0_xfer: i2c0-xfer { 784 rockchip,pins = 785 <2 24 RK_FUNC_1 &pcfg_pull_none>, 786 <2 25 RK_FUNC_1 &pcfg_pull_none>; 787 }; 788 }; 789 790 i2c1 { 791 i2c1_xfer: i2c1-xfer { 792 rockchip,pins = 793 <2 4 RK_FUNC_2 &pcfg_pull_none>, 794 <2 5 RK_FUNC_2 &pcfg_pull_none>; 795 }; 796 }; 797 798 i2c2 { 799 i2c2_xfer: i2c2-xfer { 800 rockchip,pins = 801 <2 13 RK_FUNC_1 &pcfg_pull_none>, 802 <2 14 RK_FUNC_1 &pcfg_pull_none>; 803 }; 804 }; 805 806 i2c3 { 807 i2c3_xfer: i2c3-xfer { 808 rockchip,pins = 809 <0 5 RK_FUNC_2 &pcfg_pull_none>, 810 <0 6 RK_FUNC_2 &pcfg_pull_none>; 811 }; 812 i2c3_gpio: i2c3-gpio { 813 rockchip,pins = 814 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 815 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 816 }; 817 }; 818 819 hdmi_i2c { 820 hdmii2c_xfer: hdmii2c-xfer { 821 rockchip,pins = 822 <0 5 RK_FUNC_1 &pcfg_pull_none>, 823 <0 6 RK_FUNC_1 &pcfg_pull_none>; 824 }; 825 }; 826 827 uart0 { 828 uart0_xfer: uart0-xfer { 829 rockchip,pins = 830 <1 9 RK_FUNC_1 &pcfg_pull_up>, 831 <1 8 RK_FUNC_1 &pcfg_pull_up>; 832 }; 833 834 uart0_cts: uart0-cts { 835 rockchip,pins = 836 <1 11 RK_FUNC_1 &pcfg_pull_none>; 837 }; 838 839 uart0_rts: uart0-rts { 840 rockchip,pins = 841 <1 10 RK_FUNC_1 &pcfg_pull_none>; 842 }; 843 844 uart0_rts_gpio: uart0-rts-gpio { 845 rockchip,pins = 846 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 847 }; 848 }; 849 850 uart1 { 851 uart1_xfer: uart1-xfer { 852 rockchip,pins = 853 <3 4 RK_FUNC_4 &pcfg_pull_up>, 854 <3 6 RK_FUNC_4 &pcfg_pull_up>; 855 }; 856 857 uart1_cts: uart1-cts { 858 rockchip,pins = 859 <3 7 RK_FUNC_4 &pcfg_pull_none>; 860 }; 861 862 uart1_rts: uart1-rts { 863 rockchip,pins = 864 <3 5 RK_FUNC_4 &pcfg_pull_none>; 865 }; 866 867 uart1_rts_gpio: uart1-rts-gpio { 868 rockchip,pins = 869 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 870 }; 871 }; 872 873 uart2-0 { 874 uart2m0_xfer: uart2m0-xfer { 875 rockchip,pins = 876 <1 0 RK_FUNC_2 &pcfg_pull_up>, 877 <1 1 RK_FUNC_2 &pcfg_pull_up>; 878 }; 879 }; 880 881 uart2-1 { 882 uart2m1_xfer: uart2m1-xfer { 883 rockchip,pins = 884 <2 0 RK_FUNC_1 &pcfg_pull_up>, 885 <2 1 RK_FUNC_1 &pcfg_pull_up>; 886 }; 887 }; 888 889 spi0-0 { 890 spi0m0_clk: spi0m0-clk { 891 rockchip,pins = 892 <2 8 RK_FUNC_1 &pcfg_pull_up>; 893 }; 894 895 spi0m0_cs0: spi0m0-cs0 { 896 rockchip,pins = 897 <2 11 RK_FUNC_1 &pcfg_pull_up>; 898 }; 899 900 spi0m0_tx: spi0m0-tx { 901 rockchip,pins = 902 <2 9 RK_FUNC_1 &pcfg_pull_up>; 903 }; 904 905 spi0m0_rx: spi0m0-rx { 906 rockchip,pins = 907 <2 10 RK_FUNC_1 &pcfg_pull_up>; 908 }; 909 910 spi0m0_cs1: spi0m0-cs1 { 911 rockchip,pins = 912 <2 12 RK_FUNC_1 &pcfg_pull_up>; 913 }; 914 }; 915 916 spi0-1 { 917 spi0m1_clk: spi0m1-clk { 918 rockchip,pins = 919 <3 23 RK_FUNC_2 &pcfg_pull_up>; 920 }; 921 922 spi0m1_cs0: spi0m1-cs0 { 923 rockchip,pins = 924 <3 26 RK_FUNC_2 &pcfg_pull_up>; 925 }; 926 927 spi0m1_tx: spi0m1-tx { 928 rockchip,pins = 929 <3 25 RK_FUNC_2 &pcfg_pull_up>; 930 }; 931 932 spi0m1_rx: spi0m1-rx { 933 rockchip,pins = 934 <3 24 RK_FUNC_2 &pcfg_pull_up>; 935 }; 936 937 spi0m1_cs1: spi0m1-cs1 { 938 rockchip,pins = 939 <3 27 RK_FUNC_2 &pcfg_pull_up>; 940 }; 941 }; 942 943 spi0-2 { 944 spi0m2_clk: spi0m2-clk { 945 rockchip,pins = 946 <3 0 RK_FUNC_4 &pcfg_pull_up>; 947 }; 948 949 spi0m2_cs0: spi0m2-cs0 { 950 rockchip,pins = 951 <3 8 RK_FUNC_3 &pcfg_pull_up>; 952 }; 953 954 spi0m2_tx: spi0m2-tx { 955 rockchip,pins = 956 <3 1 RK_FUNC_4 &pcfg_pull_up>; 957 }; 958 959 spi0m2_rx: spi0m2-rx { 960 rockchip,pins = 961 <3 2 RK_FUNC_4 &pcfg_pull_up>; 962 }; 963 }; 964 965 i2s1 { 966 i2s1_mclk: i2s1-mclk { 967 rockchip,pins = 968 <2 15 RK_FUNC_1 &pcfg_pull_none>; 969 }; 970 971 i2s1_sclk: i2s1-sclk { 972 rockchip,pins = 973 <2 18 RK_FUNC_1 &pcfg_pull_none>; 974 }; 975 976 i2s1_lrckrx: i2s1-lrckrx { 977 rockchip,pins = 978 <2 16 RK_FUNC_1 &pcfg_pull_none>; 979 }; 980 981 i2s1_lrcktx: i2s1-lrcktx { 982 rockchip,pins = 983 <2 17 RK_FUNC_1 &pcfg_pull_none>; 984 }; 985 986 i2s1_sdi: i2s1-sdi { 987 rockchip,pins = 988 <2 19 RK_FUNC_1 &pcfg_pull_none>; 989 }; 990 991 i2s1_sdo: i2s1-sdo { 992 rockchip,pins = 993 <2 23 RK_FUNC_1 &pcfg_pull_none>; 994 }; 995 996 i2s1_sdio1: i2s1-sdio1 { 997 rockchip,pins = 998 <2 20 RK_FUNC_1 &pcfg_pull_none>; 999 }; 1000 1001 i2s1_sdio2: i2s1-sdio2 { 1002 rockchip,pins = 1003 <2 21 RK_FUNC_1 &pcfg_pull_none>; 1004 }; 1005 1006 i2s1_sdio3: i2s1-sdio3 { 1007 rockchip,pins = 1008 <2 22 RK_FUNC_1 &pcfg_pull_none>; 1009 }; 1010 1011 i2s1_sleep: i2s1-sleep { 1012 rockchip,pins = 1013 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 1014 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 1015 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 1016 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 1017 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 1018 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 1019 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 1020 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 1021 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 1022 }; 1023 }; 1024 1025 i2s2-0 { 1026 i2s2m0_mclk: i2s2m0-mclk { 1027 rockchip,pins = 1028 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1029 }; 1030 1031 i2s2m0_sclk: i2s2m0-sclk { 1032 rockchip,pins = 1033 <1 22 RK_FUNC_1 &pcfg_pull_none>; 1034 }; 1035 1036 i2s2m0_lrckrx: i2s2m0-lrckrx { 1037 rockchip,pins = 1038 <1 26 RK_FUNC_1 &pcfg_pull_none>; 1039 }; 1040 1041 i2s2m0_lrcktx: i2s2m0-lrcktx { 1042 rockchip,pins = 1043 <1 23 RK_FUNC_1 &pcfg_pull_none>; 1044 }; 1045 1046 i2s2m0_sdi: i2s2m0-sdi { 1047 rockchip,pins = 1048 <1 24 RK_FUNC_1 &pcfg_pull_none>; 1049 }; 1050 1051 i2s2m0_sdo: i2s2m0-sdo { 1052 rockchip,pins = 1053 <1 25 RK_FUNC_1 &pcfg_pull_none>; 1054 }; 1055 1056 i2s2m0_sleep: i2s2m0-sleep { 1057 rockchip,pins = 1058 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1059 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 1060 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 1061 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 1062 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 1063 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 1064 }; 1065 }; 1066 1067 i2s2-1 { 1068 i2s2m1_mclk: i2s2m1-mclk { 1069 rockchip,pins = 1070 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1071 }; 1072 1073 i2s2m1_sclk: i2s2m1-sclk { 1074 rockchip,pins = 1075 <3 0 RK_FUNC_6 &pcfg_pull_none>; 1076 }; 1077 1078 i2s2m1_lrckrx: i2sm1-lrckrx { 1079 rockchip,pins = 1080 <3 8 RK_FUNC_6 &pcfg_pull_none>; 1081 }; 1082 1083 i2s2m1_lrcktx: i2s2m1-lrcktx { 1084 rockchip,pins = 1085 <3 8 RK_FUNC_4 &pcfg_pull_none>; 1086 }; 1087 1088 i2s2m1_sdi: i2s2m1-sdi { 1089 rockchip,pins = 1090 <3 2 RK_FUNC_6 &pcfg_pull_none>; 1091 }; 1092 1093 i2s2m1_sdo: i2s2m1-sdo { 1094 rockchip,pins = 1095 <3 1 RK_FUNC_6 &pcfg_pull_none>; 1096 }; 1097 1098 i2s2m1_sleep: i2s2m1-sleep { 1099 rockchip,pins = 1100 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1101 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 1102 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 1103 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 1104 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 1105 }; 1106 }; 1107 1108 spdif-0 { 1109 spdifm0_tx: spdifm0-tx { 1110 rockchip,pins = 1111 <0 27 RK_FUNC_1 &pcfg_pull_none>; 1112 }; 1113 }; 1114 1115 spdif-1 { 1116 spdifm1_tx: spdifm1-tx { 1117 rockchip,pins = 1118 <2 17 RK_FUNC_2 &pcfg_pull_none>; 1119 }; 1120 }; 1121 1122 spdif-2 { 1123 spdifm2_tx: spdifm2-tx { 1124 rockchip,pins = 1125 <0 2 RK_FUNC_2 &pcfg_pull_none>; 1126 }; 1127 }; 1128 1129 sdmmc0-0 { 1130 sdmmc0m0_pwren: sdmmc0m0-pwren { 1131 rockchip,pins = 1132 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1133 }; 1134 1135 sdmmc0m0_gpio: sdmmc0m0-gpio { 1136 rockchip,pins = 1137 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1138 }; 1139 }; 1140 1141 sdmmc0-1 { 1142 sdmmc0m1_pwren: sdmmc0m1-pwren { 1143 rockchip,pins = 1144 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1145 }; 1146 1147 sdmmc0m1_gpio: sdmmc0m1-gpio { 1148 rockchip,pins = 1149 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1150 }; 1151 }; 1152 1153 sdmmc0 { 1154 sdmmc0_clk: sdmmc0-clk { 1155 rockchip,pins = 1156 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1157 }; 1158 1159 sdmmc0_cmd: sdmmc0-cmd { 1160 rockchip,pins = 1161 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1162 }; 1163 1164 sdmmc0_dectn: sdmmc0-dectn { 1165 rockchip,pins = 1166 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1167 }; 1168 1169 sdmmc0_wrprt: sdmmc0-wrprt { 1170 rockchip,pins = 1171 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1172 }; 1173 1174 sdmmc0_bus1: sdmmc0-bus1 { 1175 rockchip,pins = 1176 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1177 }; 1178 1179 sdmmc0_bus4: sdmmc0-bus4 { 1180 rockchip,pins = 1181 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1182 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1183 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1184 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1185 }; 1186 1187 sdmmc0_gpio: sdmmc0-gpio { 1188 rockchip,pins = 1189 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1190 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1191 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1192 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1193 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1194 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1195 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1196 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1197 }; 1198 }; 1199 1200 sdmmc0ext { 1201 sdmmc0ext_clk: sdmmc0ext-clk { 1202 rockchip,pins = 1203 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1204 }; 1205 1206 sdmmc0ext_cmd: sdmmc0ext-cmd { 1207 rockchip,pins = 1208 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1209 }; 1210 1211 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1212 rockchip,pins = 1213 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1214 }; 1215 1216 sdmmc0ext_dectn: sdmmc0ext-dectn { 1217 rockchip,pins = 1218 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1219 }; 1220 1221 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1222 rockchip,pins = 1223 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1224 }; 1225 1226 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1227 rockchip,pins = 1228 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1229 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1230 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1231 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1232 }; 1233 1234 sdmmc0ext_gpio: sdmmc0ext-gpio { 1235 rockchip,pins = 1236 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1237 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1238 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1239 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1240 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1241 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1242 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1243 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1244 }; 1245 }; 1246 1247 sdmmc1 { 1248 sdmmc1_clk: sdmmc1-clk { 1249 rockchip,pins = 1250 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1251 }; 1252 1253 sdmmc1_cmd: sdmmc1-cmd { 1254 rockchip,pins = 1255 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1256 }; 1257 1258 sdmmc1_pwren: sdmmc1-pwren { 1259 rockchip,pins = 1260 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1261 }; 1262 1263 sdmmc1_wrprt: sdmmc1-wrprt { 1264 rockchip,pins = 1265 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1266 }; 1267 1268 sdmmc1_dectn: sdmmc1-dectn { 1269 rockchip,pins = 1270 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1271 }; 1272 1273 sdmmc1_bus1: sdmmc1-bus1 { 1274 rockchip,pins = 1275 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1276 }; 1277 1278 sdmmc1_bus4: sdmmc1-bus4 { 1279 rockchip,pins = 1280 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1281 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1282 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1283 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1284 }; 1285 1286 sdmmc1_gpio: sdmmc1-gpio { 1287 rockchip,pins = 1288 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1289 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1290 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1291 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1292 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1293 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1294 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1295 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1296 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1297 }; 1298 }; 1299 1300 emmc { 1301 emmc_clk: emmc-clk { 1302 rockchip,pins = 1303 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1304 }; 1305 1306 emmc_cmd: emmc-cmd { 1307 rockchip,pins = 1308 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1309 }; 1310 1311 emmc_pwren: emmc-pwren { 1312 rockchip,pins = 1313 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1314 }; 1315 1316 emmc_rstnout: emmc-rstnout { 1317 rockchip,pins = 1318 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1319 }; 1320 1321 emmc_bus1: emmc-bus1 { 1322 rockchip,pins = 1323 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1324 }; 1325 1326 emmc_bus4: emmc-bus4 { 1327 rockchip,pins = 1328 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1329 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1330 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1331 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1332 }; 1333 1334 emmc_bus8: emmc-bus8 { 1335 rockchip,pins = 1336 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1337 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1338 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1339 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1340 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1341 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1342 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1343 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1344 }; 1345 }; 1346 1347 pwm0 { 1348 pwm0_pin: pwm0-pin { 1349 rockchip,pins = 1350 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1351 }; 1352 }; 1353 1354 pwm1 { 1355 pwm1_pin: pwm1-pin { 1356 rockchip,pins = 1357 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1358 }; 1359 }; 1360 1361 pwm2 { 1362 pwm2_pin: pwm2-pin { 1363 rockchip,pins = 1364 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1365 }; 1366 }; 1367 1368 pwmir { 1369 pwmir_pin: pwmir-pin { 1370 rockchip,pins = 1371 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1372 }; 1373 }; 1374 1375 gmac-0 { 1376 rgmiim0_pins: rgmiim0-pins { 1377 rockchip,pins = 1378 /* mac_txclk */ 1379 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1380 /* mac_rxclk */ 1381 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1382 /* mac_mdio */ 1383 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1384 /* mac_txen */ 1385 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1386 /* mac_clk */ 1387 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1388 /* mac_rxdv */ 1389 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1390 /* mac_mdc */ 1391 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1392 /* mac_rxd1 */ 1393 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1394 /* mac_rxd0 */ 1395 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1396 /* mac_txd1 */ 1397 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1398 /* mac_txd0 */ 1399 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1400 /* mac_rxd3 */ 1401 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1402 /* mac_rxd2 */ 1403 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1404 /* mac_txd3 */ 1405 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1406 /* mac_txd2 */ 1407 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1408 }; 1409 1410 rmiim0_pins: rmiim0-pins { 1411 rockchip,pins = 1412 /* mac_mdio */ 1413 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1414 /* mac_txen */ 1415 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1416 /* mac_clk */ 1417 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1418 /* mac_rxer */ 1419 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1420 /* mac_rxdv */ 1421 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1422 /* mac_mdc */ 1423 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1424 /* mac_rxd1 */ 1425 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1426 /* mac_rxd0 */ 1427 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1428 /* mac_txd1 */ 1429 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1430 /* mac_txd0 */ 1431 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1432 }; 1433 }; 1434 1435 gmac-1 { 1436 rgmiim1_pins: rgmiim1-pins { 1437 rockchip,pins = 1438 /* mac_txclk */ 1439 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1440 /* mac_rxclk */ 1441 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1442 /* mac_mdio */ 1443 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1444 /* mac_txen */ 1445 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1446 /* mac_clk */ 1447 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1448 /* mac_rxdv */ 1449 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1450 /* mac_mdc */ 1451 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1452 /* mac_rxd1 */ 1453 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1454 /* mac_rxd0 */ 1455 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1456 /* mac_txd1 */ 1457 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1458 /* mac_txd0 */ 1459 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1460 /* mac_rxd3 */ 1461 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1462 /* mac_rxd2 */ 1463 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1464 /* mac_txd3 */ 1465 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1466 /* mac_txd2 */ 1467 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1468 1469 /* mac_txclk */ 1470 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1471 /* mac_txen */ 1472 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1473 /* mac_clk */ 1474 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1475 /* mac_txd1 */ 1476 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1477 /* mac_txd0 */ 1478 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1479 /* mac_txd3 */ 1480 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1481 /* mac_txd2 */ 1482 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1483 }; 1484 1485 rmiim1_pins: rmiim1-pins { 1486 rockchip,pins = 1487 /* mac_mdio */ 1488 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1489 /* mac_txen */ 1490 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1491 /* mac_clk */ 1492 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1493 /* mac_rxer */ 1494 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1495 /* mac_rxdv */ 1496 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1497 /* mac_mdc */ 1498 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1499 /* mac_rxd1 */ 1500 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1501 /* mac_rxd0 */ 1502 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1503 /* mac_txd1 */ 1504 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1505 /* mac_txd0 */ 1506 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1507 1508 /* mac_mdio */ 1509 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1510 /* mac_txen */ 1511 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1512 /* mac_clk */ 1513 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1514 /* mac_mdc */ 1515 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1516 /* mac_txd1 */ 1517 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1518 /* mac_txd0 */ 1519 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1520 }; 1521 }; 1522 1523 gmac2phy { 1524 fephyled_speed100: fephyled-speed100 { 1525 rockchip,pins = 1526 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1527 }; 1528 1529 fephyled_speed10: fephyled-speed10 { 1530 rockchip,pins = 1531 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1532 }; 1533 1534 fephyled_duplex: fephyled-duplex { 1535 rockchip,pins = 1536 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1537 }; 1538 1539 fephyled_rxm0: fephyled-rxm0 { 1540 rockchip,pins = 1541 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1542 }; 1543 1544 fephyled_txm0: fephyled-txm0 { 1545 rockchip,pins = 1546 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1547 }; 1548 1549 fephyled_linkm0: fephyled-linkm0 { 1550 rockchip,pins = 1551 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1552 }; 1553 1554 fephyled_rxm1: fephyled-rxm1 { 1555 rockchip,pins = 1556 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1557 }; 1558 1559 fephyled_txm1: fephyled-txm1 { 1560 rockchip,pins = 1561 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1562 }; 1563 1564 fephyled_linkm1: fephyled-linkm1 { 1565 rockchip,pins = 1566 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1567 }; 1568 }; 1569 1570 tsadc_pin { 1571 tsadc_int: tsadc-int { 1572 rockchip,pins = 1573 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1574 }; 1575 tsadc_gpio: tsadc-gpio { 1576 rockchip,pins = 1577 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1578 }; 1579 }; 1580 1581 hdmi_pin { 1582 hdmi_cec: hdmi-cec { 1583 rockchip,pins = 1584 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1585 }; 1586 1587 hdmi_hpd: hdmi-hpd { 1588 rockchip,pins = 1589 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1590 }; 1591 }; 1592 1593 cif-0 { 1594 dvp_d2d9_m0:dvp-d2d9-m0 { 1595 rockchip,pins = 1596 /* cif_d0 */ 1597 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1598 /* cif_d1 */ 1599 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1600 /* cif_d2 */ 1601 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1602 /* cif_d3 */ 1603 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1604 /* cif_d4 */ 1605 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1606 /* cif_d5m0 */ 1607 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1608 /* cif_d6m0 */ 1609 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1610 /* cif_d7m0 */ 1611 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1612 /* cif_href */ 1613 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1614 /* cif_vsync */ 1615 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1616 /* cif_clkoutm0 */ 1617 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1618 /* cif_clkin */ 1619 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1620 }; 1621 }; 1622 1623 cif-1 { 1624 dvp_d2d9_m1:dvp-d2d9-m1 { 1625 rockchip,pins = 1626 /* cif_d0 */ 1627 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1628 /* cif_d1 */ 1629 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1630 /* cif_d2 */ 1631 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1632 /* cif_d3 */ 1633 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1634 /* cif_d4 */ 1635 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1636 /* cif_d5m1 */ 1637 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1638 /* cif_d6m1 */ 1639 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1640 /* cif_d7m1 */ 1641 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1642 /* cif_href */ 1643 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1644 /* cif_vsync */ 1645 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1646 /* cif_clkoutm1 */ 1647 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1648 /* cif_clkin */ 1649 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1650 }; 1651 }; 1652 }; 1653}; 1654