1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 mmc0 = &emmc; 27 mmc1 = &sdmmc; 28 spi0 = &spi0; 29 spi1 = &spi1; 30 spi2 = &spi2; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a35", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35", "arm,armv8"; 47 reg = <0x0 0x1>; 48 enable-method = "psci"; 49 }; 50 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 58 cpu3: cpu@3 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a35", "arm,armv8"; 61 reg = <0x0 0x3>; 62 enable-method = "psci"; 63 }; 64 }; 65 66 arm-pmu { 67 compatible = "arm,cortex-a53-pmu"; 68 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 72 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 73 }; 74 75 mac_clkin: external-mac-clock { 76 compatible = "fixed-clock"; 77 clock-frequency = <50000000>; 78 clock-output-names = "mac_clkin"; 79 #clock-cells = <0>; 80 }; 81 82 display_subsystem: display-subsystem { 83 compatible = "rockchip,display-subsystem"; 84 ports = <&vop_out>; 85 status = "disabled"; 86 87 route { 88 route_rgb: route-rgb { 89 status = "okay"; 90 logo,uboot = "logo.bmp"; 91 logo,kernel = "logo_kernel.bmp"; 92 logo,mode = "center"; 93 charge_logo,mode = "center"; 94 connect = <&vop_out_rgb>; 95 }; 96 }; 97 }; 98 99 dmc: dmc@20004000 { 100 compatible = "rockchip,rk3308-dmc"; 101 reg = <0x0 0xff010000 0x0 0x10000>; 102 }; 103 104 psci { 105 compatible = "arm,psci-1.0"; 106 method = "smc"; 107 }; 108 109 timer { 110 compatible = "arm,armv8-timer"; 111 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 114 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 115 clock-frequency = <24000000>; 116 }; 117 118 clocks { 119 xin24m: xin24m { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <24000000>; 123 clock-output-names = "xin24m"; 124 }; 125 }; 126 127 grf: grf@ff000000 { 128 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 129 reg = <0x0 0xff000000 0x0 0x10000>; 130 }; 131 132 usb2phy_grf: syscon@ff008000 { 133 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 134 "simple-mfd"; 135 reg = <0x0 0xff008000 0x0 0x4000>; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 139 u2phy: usb2-phy@100 { 140 compatible = "rockchip,rk3308-usb2phy", 141 "rockchip,rk3328-usb2phy"; 142 reg = <0x100 0x10>; 143 clocks = <&cru SCLK_USBPHY_REF>; 144 clock-names = "phyclk"; 145 #clock-cells = <0>; 146 assigned-clocks = <&cru USB480M>; 147 assigned-clock-parents = <&u2phy>; 148 clock-output-names = "usb480m_phy"; 149 status = "disabled"; 150 151 u2phy_host: host-port { 152 #phy-cells = <0>; 153 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 154 interrupt-names = "linestate"; 155 status = "disabled"; 156 }; 157 158 u2phy_otg: otg-port { 159 #phy-cells = <0>; 160 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 163 interrupt-names = "otg-bvalid", "otg-id", 164 "linestate"; 165 status = "disabled"; 166 }; 167 }; 168 }; 169 170 uart0: serial@ff0a0000 { 171 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 172 reg = <0x0 0xff0a0000 0x0 0x100>; 173 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 175 clock-names = "baudclk", "apb_pclk"; 176 reg-shift = <2>; 177 reg-io-width = <4>; 178 status = "disabled"; 179 }; 180 181 uart1: serial@ff0b0000 { 182 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 183 reg = <0x0 0xff0b0000 0x0 0x100>; 184 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 186 clock-names = "baudclk", "apb_pclk"; 187 reg-shift = <2>; 188 reg-io-width = <4>; 189 status = "disabled"; 190 }; 191 192 uart2: serial@ff0c0000 { 193 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 194 reg = <0x0 0xff0c0000 0x0 0x100>; 195 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 197 clock-names = "baudclk", "apb_pclk"; 198 reg-shift = <2>; 199 reg-io-width = <4>; 200 status = "disabled"; 201 }; 202 203 uart3: serial@ff0d0000 { 204 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 205 reg = <0x0 0xff0d0000 0x0 0x100>; 206 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 208 clock-names = "baudclk", "apb_pclk"; 209 reg-shift = <2>; 210 reg-io-width = <4>; 211 status = "disabled"; 212 }; 213 214 uart4: serial@ff0e0000 { 215 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 216 reg = <0x0 0xff0e0000 0x0 0x100>; 217 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 219 clock-names = "baudclk", "apb_pclk"; 220 reg-shift = <2>; 221 reg-io-width = <4>; 222 status = "disabled"; 223 }; 224 225 spi0: spi@ff120000 { 226 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 227 reg = <0x0 0xff120000 0x0 0x1000>; 228 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 232 clock-names = "spiclk", "apb_pclk"; 233 pinctrl-names = "default", "high_speed"; 234 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 235 pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>; 236 status = "disabled"; 237 }; 238 239 spi1: spi@ff130000 { 240 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 241 reg = <0x0 0xff130000 0x0 0x1000>; 242 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 246 clock-names = "spiclk", "apb_pclk"; 247 pinctrl-names = "default", "high_speed"; 248 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 249 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; 250 status = "disabled"; 251 }; 252 253 spi2: spi@ff140000 { 254 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 255 reg = <0x0 0xff140000 0x0 0x1000>; 256 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 260 clock-names = "spiclk", "apb_pclk"; 261 pinctrl-names = "default", "high_speed"; 262 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 263 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; 264 status = "disabled"; 265 }; 266 267 secure_otp: secure_otp@0xff2a8000 { 268 compatible = "rockchip,rk3308-secure-otp"; 269 reg = <0x0 0xff2a8000 0x0 0x4000>; 270 secure_conf = <0xff2b0004>; 271 mask_addr = <0xff540000>; 272 }; 273 274 vop: vop@ff2e0000 { 275 compatible = "rockchip,rk3308-vop"; 276 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 277 reg-names = "regs", "gamma_lut"; 278 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 280 <&cru HCLK_VOP>; 281 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 282 status = "disabled"; 283 284 vop_out: port { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 vop_out_rgb: endpoint@0 { 289 reg = <0>; 290 remote-endpoint = <&rgb_in_vop>; 291 }; 292 }; 293 }; 294 295 crypto: crypto@ff2f0000 { 296 compatible = "rockchip,rk3308-crypto"; 297 reg = <0x0 0xff2f0000 0x0 0x4000>; 298 clock-names = "sclk_crypto", "apkclk_crypto"; 299 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 300 clock-frequency = <200000000>, <300000000>; 301 status = "disabled"; 302 }; 303 304 pwm0: pwm@ff180000 { 305 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 306 reg = <0x0 0xff180000 0x0 0x10>; 307 #pwm-cells = <3>; 308 pinctrl-names = "active"; 309 pinctrl-0 = <&pwm0_pin>; 310 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 311 clock-names = "pwm", "pclk"; 312 status = "disabled"; 313 }; 314 315 pwm1: pwm@ff180010 { 316 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 317 reg = <0x0 0xff180010 0x0 0x10>; 318 #pwm-cells = <3>; 319 pinctrl-names = "active"; 320 pinctrl-0 = <&pwm1_pin>; 321 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 322 clock-names = "pwm", "pclk"; 323 status = "disabled"; 324 }; 325 326 pwm2: pwm@ff180020 { 327 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 328 reg = <0x0 0xff180020 0x0 0x10>; 329 #pwm-cells = <3>; 330 pinctrl-names = "active"; 331 pinctrl-0 = <&pwm2_pin>; 332 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 333 clock-names = "pwm", "pclk"; 334 status = "disabled"; 335 }; 336 337 pwm3: pwm@ff180030 { 338 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 339 reg = <0x0 0xff180030 0x0 0x10>; 340 #pwm-cells = <3>; 341 pinctrl-names = "active"; 342 pinctrl-0 = <&pwm3_pin>; 343 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 344 clock-names = "pwm", "pclk"; 345 status = "disabled"; 346 }; 347 348 rgb: rgb { 349 compatible = "rockchip,rk3308-rgb"; 350 status = "disabled"; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&lcdc_ctl>; 353 354 ports { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 358 port@0 { 359 reg = <0>; 360 361 #address-cells = <1>; 362 #size-cells = <0>; 363 364 rgb_in_vop: endpoint@0 { 365 reg = <0>; 366 remote-endpoint = <&vop_out_rgb>; 367 }; 368 }; 369 370 }; 371 }; 372 373 saradc: saradc@ff1e0000 { 374 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 375 reg = <0x0 0xff1e0000 0x0 0x100>; 376 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 377 #io-channel-cells = <1>; 378 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 379 clock-names = "saradc", "apb_pclk"; 380 resets = <&cru SRST_SARADC_P>; 381 reset-names = "saradc-apb"; 382 status = "disabled"; 383 }; 384 385 i2s0: i2s@ff300000 { 386 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 387 reg = <0x0 0xff300000 0x0 0x10000>; 388 }; 389 390 i2s1: i2s@ff310000 { 391 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 392 reg = <0x0 0xff100000 0x0 0x10000>; 393 }; 394 395 i2s2: i2s@ff320000 { 396 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 397 reg = <0x0 0xff320000 0x0 0x10000>; 398 }; 399 400 i2s3: i2s@ff330000 { 401 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 402 reg = <0x0 0xff330000 0x0 0x10000>; 403 }; 404 405 vad: vad@ff3c0000 { 406 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 407 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 408 reg-names = "vad", "vad-memory"; 409 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 410 rockchip,audio-src = <0>; 411 rockchip,audio-chnl-num = <8>; 412 rockchip,audio-chnl = <0>; 413 rockchip,mode = <0>; 414 }; 415 416 usb20_otg: usb@ff400000 { 417 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 418 "snps,dwc2"; 419 reg = <0x0 0xff400000 0x0 0x40000>; 420 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cru HCLK_OTG>; 422 clock-names = "otg"; 423 dr_mode = "otg"; 424 g-np-tx-fifo-size = <16>; 425 g-rx-fifo-size = <275>; 426 g-tx-fifo-size = <256 128 128 64 64 32>; 427 g-use-dma; 428 phys = <&u2phy_otg>; 429 phy-names = "usb2-phy"; 430 status = "disabled"; 431 }; 432 433 usb_host0_ehci: usb@ff440000 { 434 compatible = "generic-ehci"; 435 reg = <0x0 0xff440000 0x0 0x10000>; 436 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 438 <&u2phy>; 439 clock-names = "usbhost", "arbiter", "utmi"; 440 phys = <&u2phy_host>; 441 phy-names = "usb"; 442 status = "disabled"; 443 }; 444 445 usb_host0_ohci: usb@ff450000 { 446 compatible = "generic-ohci"; 447 reg = <0x0 0xff450000 0x0 0x10000>; 448 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 450 <&u2phy>; 451 clock-names = "usbhost", "arbiter", "utmi"; 452 phys = <&u2phy_host>; 453 phy-names = "usb"; 454 }; 455 456 sdmmc: dwmmc@ff480000 { 457 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 458 reg = <0x0 0xff480000 0x0 0x4000>; 459 max-frequency = <150000000>; 460 bus-width = <4>; 461 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 462 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 463 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 464 fifo-depth = <0x100>; 465 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 468 status = "disabled"; 469 }; 470 471 emmc: dwmmc@ff490000 { 472 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 473 reg = <0x0 0xff490000 0x0 0x4000>; 474 max-frequency = <150000000>; 475 bus-width = <8>; 476 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 477 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 478 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 479 fifo-depth = <0x100>; 480 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 481 status = "disabled"; 482 }; 483 484 sdio: dwmmc@ff4a0000 { 485 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 486 reg = <0x0 0xff4a0000 0x0 0x4000>; 487 max-frequency = <150000000>; 488 bus-width = <4>; 489 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 490 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 491 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 492 fifo-depth = <0x100>; 493 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 496 status = "disabled"; 497 }; 498 499 nandc: nandc@ff4b0000 { 500 compatible = "rockchip,rk-nandc"; 501 reg = <0x0 0xff4b0000 0x0 0x4000>; 502 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 503 nandc_id = <0>; 504 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 505 clock-names = "clk_nandc", "hclk_nandc"; 506 status = "disabled"; 507 }; 508 509 510 sfc: sfc@ff4c0000 { 511 compatible = "rockchip,rksfc","rockchip,sfc"; 512 reg = <0x0 0xff4c0000 0x0 0x4000>; 513 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 515 clock-names = "clk_sfc", "hclk_sfc"; 516 status = "disabled"; 517 }; 518 519 mac: ethernet@ff4e0000 { 520 compatible = "rockchip,rk3308-mac"; 521 reg = <0x0 0xff4e0000 0x0 0x10000>; 522 rockchip,grf = <&grf>; 523 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 524 interrupt-names = "macirq"; 525 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 526 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 527 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 528 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 529 clock-names = "stmmaceth", "mac_clk_rx", 530 "mac_clk_tx", "clk_mac_ref", 531 "clk_mac_refout", "aclk_mac", 532 "pclk_mac", "clk_mac_speed"; 533 phy-mode = "rmii"; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 536 resets = <&cru SRST_MAC_A>; 537 reset-names = "stmmaceth"; 538 status = "disabled"; 539 }; 540 541 cru: clock-controller@ff500000 { 542 compatible = "rockchip,rk3308-cru"; 543 reg = <0x0 0xff500000 0x0 0x1000>; 544 rockchip,grf = <&grf>; 545 #clock-cells = <1>; 546 #reset-cells = <1>; 547 }; 548 549 gic: interrupt-controller@ff580000 { 550 compatible = "arm,gic-400"; 551 #interrupt-cells = <3>; 552 #address-cells = <0>; 553 interrupt-controller; 554 555 reg = <0x0 0xff581000 0x0 0x1000>, 556 <0x0 0xff582000 0x0 0x2000>, 557 <0x0 0xff584000 0x0 0x2000>, 558 <0x0 0xff586000 0x0 0x2000>; 559 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 560 }; 561 562 pinctrl: pinctrl { 563 compatible = "rockchip,rk3308-pinctrl"; 564 rockchip,grf = <&grf>; 565 #address-cells = <2>; 566 #size-cells = <2>; 567 ranges; 568 569 gpio0: gpio0@ff220000 { 570 compatible = "rockchip,gpio-bank"; 571 reg = <0x0 0xff220000 0x0 0x100>; 572 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 573 //clocks = <&cru PCLK_GPIO0>; 574 clocks = <&xin24m>; 575 gpio-controller; 576 #gpio-cells = <2>; 577 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 }; 581 582 gpio1: gpio1@ff230000 { 583 compatible = "rockchip,gpio-bank"; 584 reg = <0x0 0xff230000 0x0 0x100>; 585 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 586 //clocks = <&cru PCLK_GPIO1>; 587 clocks = <&xin24m>; 588 gpio-controller; 589 #gpio-cells = <2>; 590 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 }; 594 595 gpio2: gpio2@ff240000 { 596 compatible = "rockchip,gpio-bank"; 597 reg = <0x0 0xff240000 0x0 0x100>; 598 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 599 //clocks = <&cru PCLK_GPIO2>; 600 clocks = <&xin24m>; 601 gpio-controller; 602 #gpio-cells = <2>; 603 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 }; 607 608 gpio3: gpio3@ff250000 { 609 compatible = "rockchip,gpio-bank"; 610 reg = <0x0 0xff250000 0x0 0x100>; 611 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 612 //clocks = <&cru PCLK_GPIO3>; 613 clocks = <&xin24m>; 614 gpio-controller; 615 #gpio-cells = <2>; 616 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 }; 620 621 gpio4: gpio4@ff260000 { 622 compatible = "rockchip,gpio-bank"; 623 reg = <0x0 0xff260000 0x0 0x100>; 624 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 625 //clocks = <&cru PCLK_GPIO4>; 626 clocks = <&xin24m>; 627 gpio-controller; 628 #gpio-cells = <2>; 629 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 }; 633 634 pcfg_pull_up: pcfg-pull-up { 635 bias-pull-up; 636 }; 637 638 pcfg_pull_down: pcfg-pull-down { 639 bias-pull-down; 640 }; 641 642 pcfg_pull_none: pcfg-pull-none { 643 bias-disable; 644 }; 645 646 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 647 bias-disable; 648 drive-strength = <2>; 649 }; 650 651 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 652 bias-pull-up; 653 drive-strength = <2>; 654 }; 655 656 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 657 bias-pull-up; 658 drive-strength = <4>; 659 }; 660 661 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 662 bias-disable; 663 drive-strength = <4>; 664 }; 665 666 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 667 bias-pull-down; 668 drive-strength = <4>; 669 }; 670 671 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 672 bias-disable; 673 drive-strength = <8>; 674 }; 675 676 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 677 bias-pull-up; 678 drive-strength = <8>; 679 }; 680 681 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 682 bias-disable; 683 drive-strength = <12>; 684 }; 685 686 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 687 bias-pull-up; 688 drive-strength = <12>; 689 }; 690 691 pcfg_pull_none_smt: pcfg-pull-none-smt { 692 bias-disable; 693 input-schmitt-enable; 694 }; 695 696 pcfg_output_high: pcfg-output-high { 697 output-high; 698 }; 699 700 pcfg_output_low: pcfg-output-low { 701 output-low; 702 }; 703 704 pcfg_input_high: pcfg-input-high { 705 bias-pull-up; 706 input-enable; 707 }; 708 709 pcfg_input: pcfg-input { 710 input-enable; 711 }; 712 713 i2c0 { 714 i2c0_xfer: i2c0-xfer { 715 rockchip,pins = 716 <1 RK_PD0 2 &pcfg_pull_none_smt>, 717 <1 RK_PD1 2 &pcfg_pull_none_smt>; 718 }; 719 }; 720 721 i2c1 { 722 i2c1_xfer: i2c1-xfer { 723 rockchip,pins = 724 <0 RK_PB3 1 &pcfg_pull_none_smt>, 725 <0 RK_PB4 1 &pcfg_pull_none_smt>; 726 }; 727 }; 728 729 i2c2 { 730 i2c2_xfer: i2c2-xfer { 731 rockchip,pins = 732 <2 RK_PA2 3 &pcfg_pull_none_smt>, 733 <2 RK_PA3 3 &pcfg_pull_none_smt>; 734 }; 735 }; 736 737 i2c3-m0 { 738 i2c3m0_xfer: i2c3m0-xfer { 739 rockchip,pins = 740 <0 RK_PB7 2 &pcfg_pull_none_smt>, 741 <0 RK_PC0 2 &pcfg_pull_none_smt>; 742 }; 743 }; 744 745 i2c3-m1 { 746 i2c3m1_xfer: i2c3m1-xfer { 747 rockchip,pins = 748 <3 RK_PB4 2 &pcfg_pull_none_smt>, 749 <3 RK_PB5 2 &pcfg_pull_none_smt>; 750 }; 751 }; 752 753 tsadc { 754 tsadc_otp_gpio: tsadc-otp-gpio { 755 rockchip,pins = 756 <0 RK_PB2 0 &pcfg_pull_none>; 757 }; 758 759 tsadc_otp_out: tsadc-otp-out { 760 rockchip,pins = 761 <0 RK_PB2 1 &pcfg_pull_none>; 762 }; 763 }; 764 765 uart0 { 766 uart0_xfer: uart0-xfer { 767 rockchip,pins = 768 <2 RK_PA1 1 &pcfg_pull_up>, 769 <2 RK_PA0 1 &pcfg_pull_none>; 770 }; 771 772 uart0_cts: uart0-cts { 773 rockchip,pins = 774 <2 RK_PA2 1 &pcfg_pull_none>; 775 }; 776 777 uart0_rts: uart0-rts { 778 rockchip,pins = 779 <2 RK_PA3 1 &pcfg_pull_none>; 780 }; 781 }; 782 783 uart1 { 784 uart1_xfer: uart1-xfer { 785 rockchip,pins = 786 <1 RK_PD1 1 &pcfg_pull_up>, 787 <1 RK_PD0 1 &pcfg_pull_none>; 788 }; 789 790 uart1_cts: uart1-cts { 791 rockchip,pins = 792 <1 RK_PC6 1 &pcfg_pull_none>; 793 }; 794 795 uart1_rts: uart1-rts { 796 rockchip,pins = 797 <1 RK_PC7 1 &pcfg_pull_none>; 798 }; 799 }; 800 801 uart2-m0 { 802 uart2m0_xfer: uart2m0-xfer { 803 rockchip,pins = 804 <1 RK_PC7 2 &pcfg_pull_up>, 805 <1 RK_PC6 2 &pcfg_pull_none>; 806 }; 807 }; 808 809 uart2-m1 { 810 uart2m1_xfer: uart2m1-xfer { 811 rockchip,pins = 812 <4 RK_PD3 2 &pcfg_pull_up>, 813 <4 RK_PD2 2 &pcfg_pull_none>; 814 }; 815 }; 816 817 uart3 { 818 uart3_xfer: uart3-xfer { 819 rockchip,pins = 820 <3 RK_PB5 4 &pcfg_pull_up>, 821 <3 RK_PB4 4 &pcfg_pull_none>; 822 }; 823 }; 824 825 uart4 { 826 827 uart4_xfer: uart4-xfer { 828 rockchip,pins = 829 <4 RK_PB1 1 &pcfg_pull_up>, 830 <4 RK_PB0 1 &pcfg_pull_none>; 831 }; 832 833 uart4_cts: uart4-cts { 834 rockchip,pins = 835 <4 RK_PA6 1 &pcfg_pull_none>; 836 837 }; 838 839 uart4_rts: uart4-rts { 840 rockchip,pins = 841 <4 RK_PA7 1 &pcfg_pull_none>; 842 }; 843 }; 844 845 spi0 { 846 spi0_clk: spi0-clk { 847 rockchip,pins = 848 <2 RK_PA2 2 &pcfg_pull_up>; 849 }; 850 851 spi0_csn0: spi0-csn0 { 852 rockchip,pins = 853 <2 RK_PA3 2 &pcfg_pull_up>; 854 }; 855 856 spi0_miso: spi0-miso { 857 rockchip,pins = 858 <2 RK_PA0 2 &pcfg_pull_up>; 859 }; 860 861 spi0_mosi: spi0-mosi { 862 rockchip,pins = 863 <2 RK_PA1 2 &pcfg_pull_up>; 864 }; 865 spi0_clk_hs: spi0-clk-hs { 866 rockchip,pins = 867 <2 RK_PA2 2 &pcfg_pull_up_8ma>; 868 }; 869 870 spi0_miso_hs: spi0-miso-hs { 871 rockchip,pins = 872 <2 RK_PA0 2 &pcfg_pull_up_8ma>; 873 }; 874 875 spi0_mosi_hs: spi0-mosi-hs { 876 rockchip,pins = 877 <2 RK_PA1 2 &pcfg_pull_up_8ma>; 878 }; 879 }; 880 881 spi1 { 882 spi1_clk: spi1-clk { 883 rockchip,pins = 884 <3 RK_PB3 3 &pcfg_pull_up>; 885 }; 886 887 spi1_csn0: spi1-csn0 { 888 rockchip,pins = 889 <3 RK_PB5 3 &pcfg_pull_up>; 890 }; 891 892 spi1_miso: spi1-miso { 893 rockchip,pins = 894 <3 RK_PB2 3 &pcfg_pull_up>; 895 }; 896 897 spi1_mosi: spi1-mosi { 898 rockchip,pins = 899 <3 RK_PB4 3 &pcfg_pull_up>; 900 }; 901 spi1_clk_hs: spi1-clk-hs { 902 rockchip,pins = 903 <3 RK_PB3 3 &pcfg_pull_up_8ma>; 904 }; 905 906 spi1_miso_hs: spi1-miso-hs { 907 rockchip,pins = 908 <3 RK_PB2 3 &pcfg_pull_up_8ma>; 909 }; 910 911 spi1_mosi_hs: spi1-mosi-hs { 912 rockchip,pins = 913 <3 RK_PB4 3 &pcfg_pull_up_8ma>; 914 }; 915 }; 916 917 spi2 { 918 spi2_clk: spi2-clk { 919 rockchip,pins = 920 <1 RK_PD0 3 &pcfg_pull_up>; 921 }; 922 923 spi2_csn0: spi2-csn0 { 924 rockchip,pins = 925 <1 RK_PD1 3 &pcfg_pull_up>; 926 }; 927 928 spi2_miso: spi2-miso { 929 rockchip,pins = 930 <1 RK_PC6 3 &pcfg_pull_up>; 931 }; 932 933 spi2_mosi: spi2-mosi { 934 rockchip,pins = 935 <1 RK_PC7 3 &pcfg_pull_up>; 936 }; 937 spi2_clk_hs: spi2-clk-hs { 938 rockchip,pins = 939 <1 RK_PD0 3 &pcfg_pull_up_8ma>; 940 }; 941 942 spi2_miso_hs: spi2-miso-hs { 943 rockchip,pins = 944 <1 RK_PC6 3 &pcfg_pull_up_8ma>; 945 }; 946 947 spi2_mosi_hs: spi2-mosi-hs { 948 rockchip,pins = 949 <1 RK_PC7 3 &pcfg_pull_up_8ma>; 950 }; 951 }; 952 953 sdmmc_pin: sdmmc_pin { 954 sdmmc_clk: sdmmc-clk { 955 rockchip,pins = 956 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 957 }; 958 959 sdmmc_cmd: sdmmc-cmd { 960 rockchip,pins = 961 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 962 }; 963 964 sdmmc_pwren: sdmmc-pwren { 965 rockchip,pins = 966 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 967 }; 968 969 sdmmc_bus1: sdmmc-bus1 { 970 rockchip,pins = 971 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 972 }; 973 974 sdmmc_bus4: sdmmc-bus4 { 975 rockchip,pins = 976 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 977 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 978 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 979 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 980 }; 981 982 sdmmc_gpio: sdmmc-gpio { 983 rockchip,pins = 984 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 985 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 986 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 987 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 988 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 989 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 990 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 991 }; 992 }; 993 994 sdio { 995 sdio_clk: sdio-clk { 996 rockchip,pins = 997 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 998 }; 999 1000 sdio_cmd: sdio-cmd { 1001 rockchip,pins = 1002 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1003 }; 1004 1005 sdio_pwren: sdio-pwren { 1006 rockchip,pins = 1007 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1008 }; 1009 1010 sdio_wrpt: sdio-wrpt { 1011 rockchip,pins = 1012 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1013 }; 1014 1015 sdio_intn: sdio-intn { 1016 rockchip,pins = 1017 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1018 }; 1019 1020 sdio_bus1: sdio-bus1 { 1021 rockchip,pins = 1022 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1023 }; 1024 1025 sdio_bus4: sdio-bus4 { 1026 rockchip,pins = 1027 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1028 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1029 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1030 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1031 }; 1032 1033 sdio_gpio: sdio-gpio { 1034 rockchip,pins = 1035 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 1036 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 1037 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 1038 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 1039 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 1040 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 1041 }; 1042 }; 1043 1044 emmc { 1045 emmc_clk: emmc-clk { 1046 rockchip,pins = 1047 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 1048 }; 1049 1050 emmc_cmd: emmc-cmd { 1051 rockchip,pins = 1052 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 1053 }; 1054 1055 emmc_pwren: emmc-pwren { 1056 rockchip,pins = 1057 <3 RK_PB3 2 &pcfg_pull_none>; 1058 }; 1059 1060 emmc_rstn: emmc-rstn { 1061 rockchip,pins = 1062 <3 RK_PB2 2 &pcfg_pull_none>; 1063 }; 1064 1065 emmc_bus1: emmc-bus1 { 1066 rockchip,pins = 1067 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 1068 }; 1069 1070 emmc_bus4: emmc-bus4 { 1071 rockchip,pins = 1072 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1073 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1074 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1075 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 1076 }; 1077 1078 emmc_bus8: emmc-bus8 { 1079 rockchip,pins = 1080 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1081 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1082 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1083 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 1084 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 1085 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 1086 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 1087 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 1088 }; 1089 }; 1090 1091 flash { 1092 flash_csn0: flash-csn0 { 1093 rockchip,pins = 1094 <3 RK_PB5 1 &pcfg_pull_none>; 1095 }; 1096 1097 flash_rdy: flash-rdy { 1098 rockchip,pins = 1099 <3 RK_PB4 1 &pcfg_pull_none>; 1100 }; 1101 1102 flash_ale: flash-ale { 1103 rockchip,pins = 1104 <3 RK_PB3 1 &pcfg_pull_none>; 1105 }; 1106 1107 flash_cle: flash-cle { 1108 rockchip,pins = 1109 <3 RK_PB1 1 &pcfg_pull_none>; 1110 }; 1111 1112 flash_wrn: flash-wrn { 1113 rockchip,pins = 1114 <3 RK_PB0 1 &pcfg_pull_none>; 1115 }; 1116 1117 flash_rdn: flash-rdn { 1118 rockchip,pins = 1119 <3 RK_PB2 1 &pcfg_pull_none>; 1120 }; 1121 1122 flash_bus8: flash-bus8 { 1123 rockchip,pins = 1124 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1125 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1126 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1127 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1128 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1129 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1130 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1131 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1132 }; 1133 }; 1134 1135 pwm0 { 1136 pwm0_pin: pwm0-pin { 1137 rockchip,pins = 1138 <0 RK_PB5 1 &pcfg_pull_none>; 1139 }; 1140 }; 1141 1142 pwm1 { 1143 pwm1_pin: pwm1-pin { 1144 rockchip,pins = 1145 <0 RK_PB6 1 &pcfg_pull_none>; 1146 }; 1147 }; 1148 1149 pwm2 { 1150 pwm2_pin: pwm2-pin { 1151 rockchip,pins = 1152 <0 RK_PB7 1 &pcfg_pull_none>; 1153 }; 1154 }; 1155 1156 pwm3 { 1157 pwm3_pin: pwm3-pin { 1158 rockchip,pins = 1159 <0 RK_PC0 1 &pcfg_pull_none>; 1160 }; 1161 }; 1162 1163 gmac { 1164 rmii_pins: rmii-pins { 1165 rockchip,pins = 1166 /* mac_txen */ 1167 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1168 /* mac_txd1 */ 1169 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1170 /* mac_txd0 */ 1171 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1172 /* mac_rxd0 */ 1173 <1 RK_PC4 3 &pcfg_pull_none>, 1174 /* mac_rxd1 */ 1175 <1 RK_PC5 3 &pcfg_pull_none>, 1176 /* mac_rxer */ 1177 <1 RK_PB7 3 &pcfg_pull_none>, 1178 /* mac_rxdv */ 1179 <1 RK_PC0 3 &pcfg_pull_none>, 1180 /* mac_mdio */ 1181 <1 RK_PB6 3 &pcfg_pull_none>, 1182 /* mac_mdc */ 1183 <1 RK_PB5 3 &pcfg_pull_none>; 1184 }; 1185 1186 mac_refclk_12ma: mac-refclk-12ma { 1187 rockchip,pins = 1188 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1189 }; 1190 1191 mac_refclk: mac-refclk { 1192 rockchip,pins = 1193 <1 RK_PB4 3 &pcfg_pull_none>; 1194 }; 1195 1196 }; 1197 1198 lcdc { 1199 lcdc_ctl: lcdc-ctl { 1200 rockchip,pins = 1201 /* dclk */ 1202 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1203 /* hsync */ 1204 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1205 /* vsync */ 1206 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1207 /* den */ 1208 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1209 /* d0 */ 1210 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1211 /* d1 */ 1212 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1213 /* d2 */ 1214 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1215 /* d3 */ 1216 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1217 /* d4 */ 1218 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1219 /* d5 */ 1220 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1221 /* d6 */ 1222 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1223 /* d7 */ 1224 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1225 /* d8 */ 1226 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1227 /* d9 */ 1228 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1229 /* d10 */ 1230 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1231 /* d11 */ 1232 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1233 /* d12 */ 1234 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1235 /* d13 */ 1236 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1237 /* d14 */ 1238 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1239 /* d15 */ 1240 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1241 /* d16 */ 1242 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1243 /* d17 */ 1244 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1245 }; 1246 }; 1247 }; 1248}; 1249
