1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 }; 25 26 cpus { 27 #address-cells = <2>; 28 #size-cells = <0>; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a35", "arm,armv8"; 33 reg = <0x0 0x0>; 34 enable-method = "psci"; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a35", "arm,armv8"; 40 reg = <0x0 0x1>; 41 enable-method = "psci"; 42 }; 43 44 cpu2: cpu@2 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35", "arm,armv8"; 47 reg = <0x0 0x2>; 48 enable-method = "psci"; 49 }; 50 51 cpu3: cpu@3 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35", "arm,armv8"; 54 reg = <0x0 0x3>; 55 enable-method = "psci"; 56 }; 57 }; 58 59 arm-pmu { 60 compatible = "arm,cortex-a53-pmu"; 61 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 65 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 66 }; 67 68 psci { 69 compatible = "arm,psci-1.0"; 70 method = "smc"; 71 }; 72 73 timer { 74 compatible = "arm,armv8-timer"; 75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 77 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 78 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 79 clock-frequency = <24000000>; 80 }; 81 82 clocks { 83 xin24m: xin24m { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <24000000>; 87 clock-output-names = "xin24m"; 88 }; 89 }; 90 91 grf: grf@ff000000 { 92 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 93 reg = <0x0 0xff000000 0x0 0x10000>; 94 }; 95 96 usb2phy_grf: syscon@ff008000 { 97 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 98 "simple-mfd"; 99 reg = <0x0 0xff008000 0x0 0x4000>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 103 u2phy: usb2-phy@100 { 104 compatible = "rockchip,rk3308-usb2phy", 105 "rockchip,rk3328-usb2phy"; 106 reg = <0x100 0x10>; 107 clocks = <&cru SCLK_USBPHY_REF>; 108 clock-names = "phyclk"; 109 #clock-cells = <0>; 110 assigned-clocks = <&cru USB480M>; 111 assigned-clock-parents = <&u2phy>; 112 clock-output-names = "usb480m_phy"; 113 status = "disabled"; 114 115 u2phy_host: host-port { 116 #phy-cells = <0>; 117 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 118 interrupt-names = "linestate"; 119 status = "disabled"; 120 }; 121 122 u2phy_otg: otg-port { 123 #phy-cells = <0>; 124 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-names = "otg-bvalid", "otg-id", 128 "linestate"; 129 status = "disabled"; 130 }; 131 }; 132 }; 133 134 uart0: serial@ff0a0000 { 135 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 136 reg = <0x0 0xff0a0000 0x0 0x100>; 137 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 139 clock-names = "baudclk", "apb_pclk"; 140 reg-shift = <2>; 141 reg-io-width = <4>; 142 status = "disabled"; 143 }; 144 145 uart1: serial@ff0b0000 { 146 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 147 reg = <0x0 0xff0b0000 0x0 0x100>; 148 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 150 clock-names = "baudclk", "apb_pclk"; 151 reg-shift = <2>; 152 reg-io-width = <4>; 153 status = "disabled"; 154 }; 155 156 uart2: serial@ff0c0000 { 157 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 158 reg = <0x0 0xff0c0000 0x0 0x100>; 159 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 161 clock-names = "baudclk", "apb_pclk"; 162 reg-shift = <2>; 163 reg-io-width = <4>; 164 status = "disabled"; 165 }; 166 167 saradc: saradc@ff1e0000 { 168 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 169 reg = <0x0 0xff1e0000 0x0 0x100>; 170 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 171 #io-channel-cells = <1>; 172 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 173 clock-names = "saradc", "apb_pclk"; 174 resets = <&cru SRST_SARADC_P>; 175 reset-names = "saradc-apb"; 176 status = "disabled"; 177 }; 178 179 i2s0: i2s@ff300000 { 180 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 181 reg = <0x0 0xff300000 0x0 0x10000>; 182 }; 183 184 i2s1: i2s@ff310000 { 185 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 186 reg = <0x0 0xff100000 0x0 0x10000>; 187 }; 188 189 i2s2: i2s@ff320000 { 190 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 191 reg = <0x0 0xff320000 0x0 0x10000>; 192 }; 193 194 i2s3: i2s@ff330000 { 195 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 196 reg = <0x0 0xff330000 0x0 0x10000>; 197 }; 198 199 vad: vad@ff3c0000 { 200 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 201 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 202 reg-names = "vad", "vad-memory"; 203 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 204 rockchip,audio-src = <0>; 205 rockchip,audio-chnl-num = <8>; 206 rockchip,audio-chnl = <0>; 207 rockchip,mode = <0>; 208 }; 209 210 usb20_otg: usb@ff400000 { 211 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 212 "snps,dwc2"; 213 reg = <0x0 0xff400000 0x0 0x40000>; 214 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru HCLK_OTG>; 216 clock-names = "otg"; 217 dr_mode = "otg"; 218 g-np-tx-fifo-size = <16>; 219 g-rx-fifo-size = <275>; 220 g-tx-fifo-size = <256 128 128 64 64 32>; 221 g-use-dma; 222 phys = <&u2phy_otg>; 223 phy-names = "usb2-phy"; 224 status = "disabled"; 225 }; 226 227 usb_host0_ehci: usb@ff440000 { 228 compatible = "generic-ehci"; 229 reg = <0x0 0xff440000 0x0 0x10000>; 230 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 232 <&u2phy>; 233 clock-names = "usbhost", "arbiter", "utmi"; 234 phys = <&u2phy_host>; 235 phy-names = "usb"; 236 status = "disabled"; 237 }; 238 239 usb_host0_ohci: usb@ff450000 { 240 compatible = "generic-ohci"; 241 reg = <0x0 0xff450000 0x0 0x10000>; 242 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 244 <&u2phy>; 245 clock-names = "usbhost", "arbiter", "utmi"; 246 phys = <&u2phy_host>; 247 phy-names = "usb"; 248 }; 249 250 sdmmc: dwmmc@ff480000 { 251 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 252 reg = <0x0 0xff480000 0x0 0x4000>; 253 max-frequency = <150000000>; 254 bus-width = <4>; 255 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 256 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 257 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 258 fifo-depth = <0x100>; 259 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 262 status = "disabled"; 263 }; 264 265 emmc: dwmmc@ff490000 { 266 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 267 reg = <0x0 0xff490000 0x0 0x4000>; 268 max-frequency = <150000000>; 269 bus-width = <8>; 270 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 271 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 272 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 273 fifo-depth = <0x100>; 274 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; 277 status = "disabled"; 278 }; 279 280 sdio: dwmmc@ff4a0000 { 281 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 282 reg = <0x0 0xff4a0000 0x0 0x4000>; 283 max-frequency = <150000000>; 284 bus-width = <4>; 285 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 286 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 287 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 288 fifo-depth = <0x100>; 289 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 292 status = "disabled"; 293 }; 294 295 cru: clock-controller@ff500000 { 296 compatible = "rockchip,rk3308-cru"; 297 reg = <0x0 0xff500000 0x0 0x1000>; 298 rockchip,grf = <&grf>; 299 #clock-cells = <1>; 300 #reset-cells = <1>; 301 }; 302 303 gic: interrupt-controller@ff580000 { 304 compatible = "arm,gic-400"; 305 #interrupt-cells = <3>; 306 #address-cells = <0>; 307 interrupt-controller; 308 309 reg = <0x0 0xff581000 0x0 0x1000>, 310 <0x0 0xff582000 0x0 0x2000>, 311 <0x0 0xff584000 0x0 0x2000>, 312 <0x0 0xff586000 0x0 0x2000>; 313 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 316 pinctrl: pinctrl { 317 compatible = "rockchip,rk3308-pinctrl"; 318 rockchip,grf = <&grf>; 319 #address-cells = <2>; 320 #size-cells = <2>; 321 ranges; 322 323 gpio0: gpio0@ff220000 { 324 compatible = "rockchip,gpio-bank"; 325 reg = <0x0 0xff220000 0x0 0x100>; 326 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 327 //clocks = <&cru PCLK_GPIO0>; 328 clocks = <&xin24m>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 336 gpio1: gpio1@ff230000 { 337 compatible = "rockchip,gpio-bank"; 338 reg = <0x0 0xff230000 0x0 0x100>; 339 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 340 //clocks = <&cru PCLK_GPIO1>; 341 clocks = <&xin24m>; 342 gpio-controller; 343 #gpio-cells = <2>; 344 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 }; 348 349 gpio2: gpio2@ff240000 { 350 compatible = "rockchip,gpio-bank"; 351 reg = <0x0 0xff240000 0x0 0x100>; 352 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 353 //clocks = <&cru PCLK_GPIO2>; 354 clocks = <&xin24m>; 355 gpio-controller; 356 #gpio-cells = <2>; 357 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 }; 361 362 gpio3: gpio3@ff250000 { 363 compatible = "rockchip,gpio-bank"; 364 reg = <0x0 0xff250000 0x0 0x100>; 365 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 366 //clocks = <&cru PCLK_GPIO3>; 367 clocks = <&xin24m>; 368 gpio-controller; 369 #gpio-cells = <2>; 370 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 }; 374 375 gpio4: gpio4@ff260000 { 376 compatible = "rockchip,gpio-bank"; 377 reg = <0x0 0xff260000 0x0 0x100>; 378 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 379 //clocks = <&cru PCLK_GPIO4>; 380 clocks = <&xin24m>; 381 gpio-controller; 382 #gpio-cells = <2>; 383 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 }; 387 388 pcfg_pull_up: pcfg-pull-up { 389 bias-pull-up; 390 }; 391 392 pcfg_pull_down: pcfg-pull-down { 393 bias-pull-down; 394 }; 395 396 pcfg_pull_none: pcfg-pull-none { 397 bias-disable; 398 }; 399 400 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 401 bias-disable; 402 drive-strength = <2>; 403 }; 404 405 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 406 bias-pull-up; 407 drive-strength = <2>; 408 }; 409 410 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 411 bias-pull-up; 412 drive-strength = <4>; 413 }; 414 415 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 416 bias-disable; 417 drive-strength = <4>; 418 }; 419 420 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 421 bias-pull-down; 422 drive-strength = <4>; 423 }; 424 425 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 426 bias-disable; 427 drive-strength = <8>; 428 }; 429 430 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 431 bias-pull-up; 432 drive-strength = <8>; 433 }; 434 435 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 436 bias-disable; 437 drive-strength = <12>; 438 }; 439 440 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 441 bias-pull-up; 442 drive-strength = <12>; 443 }; 444 445 pcfg_pull_none_smt: pcfg-pull-none-smt { 446 bias-disable; 447 input-schmitt-enable; 448 }; 449 450 pcfg_output_high: pcfg-output-high { 451 output-high; 452 }; 453 454 pcfg_output_low: pcfg-output-low { 455 output-low; 456 }; 457 458 pcfg_input_high: pcfg-input-high { 459 bias-pull-up; 460 input-enable; 461 }; 462 463 pcfg_input: pcfg-input { 464 input-enable; 465 }; 466 467 i2c0 { 468 i2c0_xfer: i2c0-xfer { 469 rockchip,pins = 470 <1 RK_PD0 2 &pcfg_pull_none_smt>, 471 <1 RK_PD1 2 &pcfg_pull_none_smt>; 472 }; 473 }; 474 475 i2c1 { 476 i2c1_xfer: i2c1-xfer { 477 rockchip,pins = 478 <0 RK_PB3 1 &pcfg_pull_none_smt>, 479 <0 RK_PB4 1 &pcfg_pull_none_smt>; 480 }; 481 }; 482 483 i2c2 { 484 i2c2_xfer: i2c2-xfer { 485 rockchip,pins = 486 <2 RK_PA2 3 &pcfg_pull_none_smt>, 487 <2 RK_PA3 3 &pcfg_pull_none_smt>; 488 }; 489 }; 490 491 i2c3-m0 { 492 i2c3m0_xfer: i2c3m0-xfer { 493 rockchip,pins = 494 <0 RK_PB7 2 &pcfg_pull_none_smt>, 495 <0 RK_PC0 2 &pcfg_pull_none_smt>; 496 }; 497 }; 498 499 i2c3-m1 { 500 i2c3m1_xfer: i2c3m1-xfer { 501 rockchip,pins = 502 <3 RK_PB4 2 &pcfg_pull_none_smt>, 503 <3 RK_PB5 2 &pcfg_pull_none_smt>; 504 }; 505 }; 506 507 tsadc { 508 tsadc_otp_gpio: tsadc-otp-gpio { 509 rockchip,pins = 510 <0 RK_PB2 0 &pcfg_pull_none>; 511 }; 512 513 tsadc_otp_out: tsadc-otp-out { 514 rockchip,pins = 515 <0 RK_PB2 1 &pcfg_pull_none>; 516 }; 517 }; 518 519 uart0 { 520 uart0_xfer: uart0-xfer { 521 rockchip,pins = 522 <2 RK_PA1 1 &pcfg_pull_up>, 523 <2 RK_PA0 1 &pcfg_pull_none>; 524 }; 525 526 uart0_cts: uart0-cts { 527 rockchip,pins = 528 <2 RK_PA2 1 &pcfg_pull_none>; 529 }; 530 531 uart0_rts: uart0-rts { 532 rockchip,pins = 533 <2 RK_PA3 1 &pcfg_pull_none>; 534 }; 535 }; 536 537 uart1 { 538 uart1_xfer: uart1-xfer { 539 rockchip,pins = 540 <1 RK_PD1 1 &pcfg_pull_up>, 541 <1 RK_PD0 1 &pcfg_pull_none>; 542 }; 543 544 uart1_cts: uart1-cts { 545 rockchip,pins = 546 <1 RK_PC6 1 &pcfg_pull_none>; 547 }; 548 549 uart1_rts: uart1-rts { 550 rockchip,pins = 551 <1 RK_PC7 1 &pcfg_pull_none>; 552 }; 553 }; 554 555 uart2-m0 { 556 uart2m0_xfer: uart2m0-xfer { 557 rockchip,pins = 558 <1 RK_PC7 2 &pcfg_pull_up>, 559 <1 RK_PC6 2 &pcfg_pull_none>; 560 }; 561 }; 562 563 uart2-m1 { 564 uart2m1_xfer: uart2m1-xfer { 565 rockchip,pins = 566 <4 RK_PD3 2 &pcfg_pull_up>, 567 <4 RK_PD2 2 &pcfg_pull_none>; 568 }; 569 }; 570 571 uart3 { 572 uart3_xfer: uart3-xfer { 573 rockchip,pins = 574 <3 RK_PB5 4 &pcfg_pull_up>, 575 <3 RK_PB4 4 &pcfg_pull_none>; 576 }; 577 }; 578 579 uart4 { 580 581 uart4_xfer: uart4-xfer { 582 rockchip,pins = 583 <4 RK_PB1 1 &pcfg_pull_up>, 584 <4 RK_PB0 1 &pcfg_pull_none>; 585 }; 586 587 uart4_cts: uart4-cts { 588 rockchip,pins = 589 <4 RK_PA6 1 &pcfg_pull_none>; 590 591 }; 592 593 uart4_rts: uart4-rts { 594 rockchip,pins = 595 <4 RK_PA7 1 &pcfg_pull_none>; 596 }; 597 }; 598 599 spi0 { 600 spi0_clk: spi0-clk { 601 rockchip,pins = 602 <2 RK_PA2 2 &pcfg_pull_up>; 603 }; 604 605 spi0_csn0: spi0-csn0 { 606 rockchip,pins = 607 <2 RK_PA3 2 &pcfg_pull_up>; 608 }; 609 610 spi0_miso: spi0-miso { 611 rockchip,pins = 612 <2 RK_PA0 2 &pcfg_pull_up>; 613 }; 614 615 spi0_mosi: spi0-mosi { 616 rockchip,pins = 617 <2 RK_PA1 2 &pcfg_pull_up>; 618 }; 619 }; 620 621 spi1 { 622 spi1_clk: spi1-clk { 623 rockchip,pins = 624 <3 RK_PB3 3 &pcfg_pull_up>; 625 }; 626 627 spi1_csn0: spi1-csn0 { 628 rockchip,pins = 629 <3 RK_PB5 3 &pcfg_pull_up>; 630 }; 631 632 spi1_miso: spi1-miso { 633 rockchip,pins = 634 <3 RK_PB2 3 &pcfg_pull_up>; 635 }; 636 637 spi1_mosi: spi1-mosi { 638 rockchip,pins = 639 <3 RK_PB4 3 &pcfg_pull_up>; 640 }; 641 }; 642 643 spi2 { 644 spi2_clk: spi2-clk { 645 rockchip,pins = 646 <1 RK_PD0 3 &pcfg_pull_up>; 647 }; 648 649 spi2_csn0: spi2-csn0 { 650 rockchip,pins = 651 <1 RK_PD1 3 &pcfg_pull_up>; 652 }; 653 654 spi2_miso: spi2-miso { 655 rockchip,pins = 656 <1 RK_PC6 3 &pcfg_pull_up>; 657 }; 658 659 spi2_mosi: spi2-mosi { 660 rockchip,pins = 661 <1 RK_PC7 3 &pcfg_pull_up>; 662 }; 663 }; 664 665 sdmmc { 666 sdmmc_clk: sdmmc-clk { 667 rockchip,pins = 668 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 669 }; 670 671 sdmmc_cmd: sdmmc-cmd { 672 rockchip,pins = 673 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 674 }; 675 676 sdmmc_pwren: sdmmc-pwren { 677 rockchip,pins = 678 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 679 }; 680 681 sdmmc_bus1: sdmmc-bus1 { 682 rockchip,pins = 683 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 684 }; 685 686 sdmmc_bus4: sdmmc-bus4 { 687 rockchip,pins = 688 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 689 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 690 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 691 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 692 }; 693 694 sdmmc_gpio: sdmmc-gpio { 695 rockchip,pins = 696 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 697 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 698 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 699 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 700 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 701 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 702 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 703 }; 704 }; 705 706 sdio { 707 sdio_clk: sdio-clk { 708 rockchip,pins = 709 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 710 }; 711 712 sdio_cmd: sdio-cmd { 713 rockchip,pins = 714 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 715 }; 716 717 sdio_pwren: sdio-pwren { 718 rockchip,pins = 719 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 720 }; 721 722 sdio_wrpt: sdio-wrpt { 723 rockchip,pins = 724 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 725 }; 726 727 sdio_intn: sdio-intn { 728 rockchip,pins = 729 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 730 }; 731 732 sdio_bus1: sdio-bus1 { 733 rockchip,pins = 734 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 735 }; 736 737 sdio_bus4: sdio-bus4 { 738 rockchip,pins = 739 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 740 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 741 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 742 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 743 }; 744 745 sdio_gpio: sdio-gpio { 746 rockchip,pins = 747 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 748 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 749 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 750 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 751 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 752 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 753 }; 754 }; 755 756 emmc { 757 emmc_clk: emmc-clk { 758 rockchip,pins = 759 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 760 }; 761 762 emmc_cmd: emmc-cmd { 763 rockchip,pins = 764 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 765 }; 766 767 emmc_pwren: emmc-pwren { 768 rockchip,pins = 769 <3 RK_PB3 2 &pcfg_pull_none>; 770 }; 771 772 emmc_rstn: emmc-rstn { 773 rockchip,pins = 774 <3 RK_PB2 2 &pcfg_pull_none>; 775 }; 776 777 emmc_bus1: emmc-bus1 { 778 rockchip,pins = 779 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 780 }; 781 782 emmc_bus4: emmc-bus4 { 783 rockchip,pins = 784 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 785 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 786 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 787 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 788 }; 789 790 emmc_bus8: emmc-bus8 { 791 rockchip,pins = 792 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 793 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 794 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 795 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 796 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 797 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 798 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 799 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 800 }; 801 }; 802 803 flash { 804 flash_csn0: flash-csn0 { 805 rockchip,pins = 806 <3 RK_PB5 1 &pcfg_pull_none>; 807 }; 808 809 flash_rdy: flash-rdy { 810 rockchip,pins = 811 <3 RK_PB4 1 &pcfg_pull_none>; 812 }; 813 814 flash_ale: flash-ale { 815 rockchip,pins = 816 <3 RK_PB3 1 &pcfg_pull_none>; 817 }; 818 819 flash_cle: flash-cle { 820 rockchip,pins = 821 <3 RK_PB1 1 &pcfg_pull_none>; 822 }; 823 824 flash_wrn: flash-wrn { 825 rockchip,pins = 826 <3 RK_PB0 1 &pcfg_pull_none>; 827 }; 828 829 flash_rdn: flash-rdn { 830 rockchip,pins = 831 <3 RK_PB2 1 &pcfg_pull_none>; 832 }; 833 834 flash_bus8: flash-bus8 { 835 rockchip,pins = 836 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 837 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 838 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 839 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 840 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 841 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 842 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 843 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 844 }; 845 }; 846 847 pwm0 { 848 pwm0_pin: pwm0-pin { 849 rockchip,pins = 850 <0 RK_PB5 1 &pcfg_pull_none>; 851 }; 852 }; 853 854 pwm1 { 855 pwm1_pin: pwm1-pin { 856 rockchip,pins = 857 <0 RK_PB6 1 &pcfg_pull_none>; 858 }; 859 }; 860 861 pwm2 { 862 pwm2_pin: pwm2-pin { 863 rockchip,pins = 864 <0 RK_PB7 1 &pcfg_pull_none>; 865 }; 866 }; 867 868 pwm3 { 869 pwm3_pin: pwm3-pin { 870 rockchip,pins = 871 <0 RK_PC0 1 &pcfg_pull_none>; 872 }; 873 }; 874 875 gmac { 876 rmii_pins: rmii-pins { 877 rockchip,pins = 878 /* mac_txen */ 879 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 880 /* mac_txd1 */ 881 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 882 /* mac_txd0 */ 883 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 884 /* mac_rxd0 */ 885 <1 RK_PC4 3 &pcfg_pull_none>, 886 /* mac_rxd1 */ 887 <1 RK_PC5 3 &pcfg_pull_none>, 888 /* mac_rxer */ 889 <1 RK_PB7 3 &pcfg_pull_none>, 890 /* mac_rxdv */ 891 <1 RK_PC0 3 &pcfg_pull_none>, 892 /* mac_mdio */ 893 <1 RK_PB6 3 &pcfg_pull_none>, 894 /* mac_mdc */ 895 <1 RK_PB5 3 &pcfg_pull_none>, 896 /* mac_clk */ 897 <1 RK_PB4 3 &pcfg_pull_none>; 898 }; 899 }; 900 }; 901}; 902