1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a35", "arm,armv8"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a35", "arm,armv8"; 42 reg = <0x0 0x1>; 43 enable-method = "psci"; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a35", "arm,armv8"; 49 reg = <0x0 0x2>; 50 enable-method = "psci"; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35", "arm,armv8"; 56 reg = <0x0 0x3>; 57 enable-method = "psci"; 58 }; 59 }; 60 61 arm-pmu { 62 compatible = "arm,cortex-a53-pmu"; 63 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 68 }; 69 70 mac_clkin: external-mac-clock { 71 compatible = "fixed-clock"; 72 clock-frequency = <50000000>; 73 clock-output-names = "mac_clkin"; 74 #clock-cells = <0>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vop_out>; 80 status = "disabled"; 81 82 route { 83 route_rgb: route-rgb { 84 status = "okay"; 85 logo,uboot = "logo.bmp"; 86 logo,kernel = "logo_kernel.bmp"; 87 logo,mode = "center"; 88 charge_logo,mode = "center"; 89 connect = <&vop_out_rgb>; 90 }; 91 }; 92 }; 93 94 dmc: dmc@20004000 { 95 compatible = "rockchip,rk3308-dmc"; 96 reg = <0x0 0xff010000 0x0 0x10000>; 97 }; 98 99 psci { 100 compatible = "arm,psci-1.0"; 101 method = "smc"; 102 }; 103 104 timer { 105 compatible = "arm,armv8-timer"; 106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 clock-frequency = <24000000>; 111 }; 112 113 clocks { 114 xin24m: xin24m { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <24000000>; 118 clock-output-names = "xin24m"; 119 }; 120 }; 121 122 grf: grf@ff000000 { 123 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 124 reg = <0x0 0xff000000 0x0 0x10000>; 125 }; 126 127 usb2phy_grf: syscon@ff008000 { 128 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 129 "simple-mfd"; 130 reg = <0x0 0xff008000 0x0 0x4000>; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 134 u2phy: usb2-phy@100 { 135 compatible = "rockchip,rk3308-usb2phy", 136 "rockchip,rk3328-usb2phy"; 137 reg = <0x100 0x10>; 138 clocks = <&cru SCLK_USBPHY_REF>; 139 clock-names = "phyclk"; 140 #clock-cells = <0>; 141 assigned-clocks = <&cru USB480M>; 142 assigned-clock-parents = <&u2phy>; 143 clock-output-names = "usb480m_phy"; 144 status = "disabled"; 145 146 u2phy_host: host-port { 147 #phy-cells = <0>; 148 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 149 interrupt-names = "linestate"; 150 status = "disabled"; 151 }; 152 153 u2phy_otg: otg-port { 154 #phy-cells = <0>; 155 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "otg-bvalid", "otg-id", 159 "linestate"; 160 status = "disabled"; 161 }; 162 }; 163 }; 164 165 uart0: serial@ff0a0000 { 166 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 167 reg = <0x0 0xff0a0000 0x0 0x100>; 168 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 170 clock-names = "baudclk", "apb_pclk"; 171 reg-shift = <2>; 172 reg-io-width = <4>; 173 status = "disabled"; 174 }; 175 176 uart1: serial@ff0b0000 { 177 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 178 reg = <0x0 0xff0b0000 0x0 0x100>; 179 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 181 clock-names = "baudclk", "apb_pclk"; 182 reg-shift = <2>; 183 reg-io-width = <4>; 184 status = "disabled"; 185 }; 186 187 uart2: serial@ff0c0000 { 188 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 189 reg = <0x0 0xff0c0000 0x0 0x100>; 190 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 192 clock-names = "baudclk", "apb_pclk"; 193 reg-shift = <2>; 194 reg-io-width = <4>; 195 status = "disabled"; 196 }; 197 198 uart3: serial@ff0d0000 { 199 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 200 reg = <0x0 0xff0d0000 0x0 0x100>; 201 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 203 clock-names = "baudclk", "apb_pclk"; 204 reg-shift = <2>; 205 reg-io-width = <4>; 206 status = "disabled"; 207 }; 208 209 uart4: serial@ff0e0000 { 210 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 211 reg = <0x0 0xff0e0000 0x0 0x100>; 212 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 214 clock-names = "baudclk", "apb_pclk"; 215 reg-shift = <2>; 216 reg-io-width = <4>; 217 status = "disabled"; 218 }; 219 220 secure_otp: secure_otp@0xff2a8000 { 221 compatible = "rockchip,rk3308-secure-otp"; 222 reg = <0x0 0xff2a8000 0x0 0x4000>; 223 secure_conf = <0xff2b0004>; 224 mask_addr = <0xff540000>; 225 }; 226 227 vop: vop@ff2e0000 { 228 compatible = "rockchip,rk3308-vop"; 229 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 230 reg-names = "regs", "gamma_lut"; 231 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 233 <&cru HCLK_VOP>; 234 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 235 status = "disabled"; 236 237 vop_out: port { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 vop_out_rgb: endpoint@0 { 242 reg = <0>; 243 remote-endpoint = <&rgb_in_vop>; 244 }; 245 }; 246 }; 247 248 crypto: crypto@ff2f0000 { 249 compatible = "rockchip,rk3308-crypto"; 250 reg = <0x0 0xff2f0000 0x0 0x4000>; 251 clock-names = "sclk_crypto", "apkclk_crypto"; 252 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 253 clock-frequency = <200000000>, <300000000>; 254 status = "disabled"; 255 }; 256 257 pwm0: pwm@ff180000 { 258 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 259 reg = <0x0 0xff180000 0x0 0x10>; 260 #pwm-cells = <3>; 261 pinctrl-names = "active"; 262 pinctrl-0 = <&pwm0_pin>; 263 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 264 clock-names = "pwm", "pclk"; 265 status = "disabled"; 266 }; 267 268 pwm1: pwm@ff180010 { 269 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 270 reg = <0x0 0xff180010 0x0 0x10>; 271 #pwm-cells = <3>; 272 pinctrl-names = "active"; 273 pinctrl-0 = <&pwm1_pin>; 274 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 275 clock-names = "pwm", "pclk"; 276 status = "disabled"; 277 }; 278 279 pwm2: pwm@ff180020 { 280 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 281 reg = <0x0 0xff180020 0x0 0x10>; 282 #pwm-cells = <3>; 283 pinctrl-names = "active"; 284 pinctrl-0 = <&pwm2_pin>; 285 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 286 clock-names = "pwm", "pclk"; 287 status = "disabled"; 288 }; 289 290 pwm3: pwm@ff180030 { 291 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 292 reg = <0x0 0xff180030 0x0 0x10>; 293 #pwm-cells = <3>; 294 pinctrl-names = "active"; 295 pinctrl-0 = <&pwm3_pin>; 296 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 297 clock-names = "pwm", "pclk"; 298 status = "disabled"; 299 }; 300 301 rgb: rgb { 302 compatible = "rockchip,rk3308-rgb"; 303 status = "disabled"; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&lcdc_ctl>; 306 307 ports { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 311 port@0 { 312 reg = <0>; 313 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 rgb_in_vop: endpoint@0 { 318 reg = <0>; 319 remote-endpoint = <&vop_out_rgb>; 320 }; 321 }; 322 323 }; 324 }; 325 326 saradc: saradc@ff1e0000 { 327 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 328 reg = <0x0 0xff1e0000 0x0 0x100>; 329 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 330 #io-channel-cells = <1>; 331 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 332 clock-names = "saradc", "apb_pclk"; 333 resets = <&cru SRST_SARADC_P>; 334 reset-names = "saradc-apb"; 335 status = "disabled"; 336 }; 337 338 i2s0: i2s@ff300000 { 339 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 340 reg = <0x0 0xff300000 0x0 0x10000>; 341 }; 342 343 i2s1: i2s@ff310000 { 344 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 345 reg = <0x0 0xff100000 0x0 0x10000>; 346 }; 347 348 i2s2: i2s@ff320000 { 349 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 350 reg = <0x0 0xff320000 0x0 0x10000>; 351 }; 352 353 i2s3: i2s@ff330000 { 354 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 355 reg = <0x0 0xff330000 0x0 0x10000>; 356 }; 357 358 vad: vad@ff3c0000 { 359 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 360 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 361 reg-names = "vad", "vad-memory"; 362 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 363 rockchip,audio-src = <0>; 364 rockchip,audio-chnl-num = <8>; 365 rockchip,audio-chnl = <0>; 366 rockchip,mode = <0>; 367 }; 368 369 usb20_otg: usb@ff400000 { 370 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 371 "snps,dwc2"; 372 reg = <0x0 0xff400000 0x0 0x40000>; 373 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cru HCLK_OTG>; 375 clock-names = "otg"; 376 dr_mode = "otg"; 377 g-np-tx-fifo-size = <16>; 378 g-rx-fifo-size = <275>; 379 g-tx-fifo-size = <256 128 128 64 64 32>; 380 g-use-dma; 381 phys = <&u2phy_otg>; 382 phy-names = "usb2-phy"; 383 status = "disabled"; 384 }; 385 386 usb_host0_ehci: usb@ff440000 { 387 compatible = "generic-ehci"; 388 reg = <0x0 0xff440000 0x0 0x10000>; 389 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 391 <&u2phy>; 392 clock-names = "usbhost", "arbiter", "utmi"; 393 phys = <&u2phy_host>; 394 phy-names = "usb"; 395 status = "disabled"; 396 }; 397 398 usb_host0_ohci: usb@ff450000 { 399 compatible = "generic-ohci"; 400 reg = <0x0 0xff450000 0x0 0x10000>; 401 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 403 <&u2phy>; 404 clock-names = "usbhost", "arbiter", "utmi"; 405 phys = <&u2phy_host>; 406 phy-names = "usb"; 407 }; 408 409 sdmmc: dwmmc@ff480000 { 410 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 411 reg = <0x0 0xff480000 0x0 0x4000>; 412 max-frequency = <150000000>; 413 bus-width = <4>; 414 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 415 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 416 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 417 fifo-depth = <0x100>; 418 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 421 status = "disabled"; 422 }; 423 424 emmc: dwmmc@ff490000 { 425 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 426 reg = <0x0 0xff490000 0x0 0x4000>; 427 max-frequency = <150000000>; 428 bus-width = <8>; 429 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 430 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 431 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 432 fifo-depth = <0x100>; 433 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 434 status = "disabled"; 435 }; 436 437 sdio: dwmmc@ff4a0000 { 438 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 439 reg = <0x0 0xff4a0000 0x0 0x4000>; 440 max-frequency = <150000000>; 441 bus-width = <4>; 442 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 443 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 444 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 445 fifo-depth = <0x100>; 446 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 449 status = "disabled"; 450 }; 451 452 nandc: nandc@ff4b0000 { 453 compatible = "rockchip,rk-nandc"; 454 reg = <0x0 0xff4b0000 0x0 0x4000>; 455 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 456 nandc_id = <0>; 457 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 458 clock-names = "clk_nandc", "hclk_nandc"; 459 status = "disabled"; 460 }; 461 462 463 sfc: sfc@ff4c0000 { 464 compatible = "rockchip,rksfc","rockchip,sfc"; 465 reg = <0x0 0xff4c0000 0x0 0x4000>; 466 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 468 clock-names = "clk_sfc", "hclk_sfc"; 469 status = "disabled"; 470 }; 471 472 mac: ethernet@ff4e0000 { 473 compatible = "rockchip,rk3308-mac"; 474 reg = <0x0 0xff4e0000 0x0 0x10000>; 475 rockchip,grf = <&grf>; 476 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-names = "macirq"; 478 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 479 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 480 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 481 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 482 clock-names = "stmmaceth", "mac_clk_rx", 483 "mac_clk_tx", "clk_mac_ref", 484 "clk_mac_refout", "aclk_mac", 485 "pclk_mac", "clk_mac_speed"; 486 phy-mode = "rmii"; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 489 resets = <&cru SRST_MAC_A>; 490 reset-names = "stmmaceth"; 491 status = "disabled"; 492 }; 493 494 cru: clock-controller@ff500000 { 495 compatible = "rockchip,rk3308-cru"; 496 reg = <0x0 0xff500000 0x0 0x1000>; 497 rockchip,grf = <&grf>; 498 #clock-cells = <1>; 499 #reset-cells = <1>; 500 }; 501 502 gic: interrupt-controller@ff580000 { 503 compatible = "arm,gic-400"; 504 #interrupt-cells = <3>; 505 #address-cells = <0>; 506 interrupt-controller; 507 508 reg = <0x0 0xff581000 0x0 0x1000>, 509 <0x0 0xff582000 0x0 0x2000>, 510 <0x0 0xff584000 0x0 0x2000>, 511 <0x0 0xff586000 0x0 0x2000>; 512 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 513 }; 514 515 pinctrl: pinctrl { 516 compatible = "rockchip,rk3308-pinctrl"; 517 rockchip,grf = <&grf>; 518 #address-cells = <2>; 519 #size-cells = <2>; 520 ranges; 521 522 gpio0: gpio0@ff220000 { 523 compatible = "rockchip,gpio-bank"; 524 reg = <0x0 0xff220000 0x0 0x100>; 525 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 526 //clocks = <&cru PCLK_GPIO0>; 527 clocks = <&xin24m>; 528 gpio-controller; 529 #gpio-cells = <2>; 530 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 }; 534 535 gpio1: gpio1@ff230000 { 536 compatible = "rockchip,gpio-bank"; 537 reg = <0x0 0xff230000 0x0 0x100>; 538 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 539 //clocks = <&cru PCLK_GPIO1>; 540 clocks = <&xin24m>; 541 gpio-controller; 542 #gpio-cells = <2>; 543 544 interrupt-controller; 545 #interrupt-cells = <2>; 546 }; 547 548 gpio2: gpio2@ff240000 { 549 compatible = "rockchip,gpio-bank"; 550 reg = <0x0 0xff240000 0x0 0x100>; 551 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 552 //clocks = <&cru PCLK_GPIO2>; 553 clocks = <&xin24m>; 554 gpio-controller; 555 #gpio-cells = <2>; 556 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 }; 560 561 gpio3: gpio3@ff250000 { 562 compatible = "rockchip,gpio-bank"; 563 reg = <0x0 0xff250000 0x0 0x100>; 564 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 565 //clocks = <&cru PCLK_GPIO3>; 566 clocks = <&xin24m>; 567 gpio-controller; 568 #gpio-cells = <2>; 569 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 }; 573 574 gpio4: gpio4@ff260000 { 575 compatible = "rockchip,gpio-bank"; 576 reg = <0x0 0xff260000 0x0 0x100>; 577 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 578 //clocks = <&cru PCLK_GPIO4>; 579 clocks = <&xin24m>; 580 gpio-controller; 581 #gpio-cells = <2>; 582 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 587 pcfg_pull_up: pcfg-pull-up { 588 bias-pull-up; 589 }; 590 591 pcfg_pull_down: pcfg-pull-down { 592 bias-pull-down; 593 }; 594 595 pcfg_pull_none: pcfg-pull-none { 596 bias-disable; 597 }; 598 599 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 600 bias-disable; 601 drive-strength = <2>; 602 }; 603 604 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 605 bias-pull-up; 606 drive-strength = <2>; 607 }; 608 609 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 610 bias-pull-up; 611 drive-strength = <4>; 612 }; 613 614 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 615 bias-disable; 616 drive-strength = <4>; 617 }; 618 619 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 620 bias-pull-down; 621 drive-strength = <4>; 622 }; 623 624 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 625 bias-disable; 626 drive-strength = <8>; 627 }; 628 629 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 630 bias-pull-up; 631 drive-strength = <8>; 632 }; 633 634 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 635 bias-disable; 636 drive-strength = <12>; 637 }; 638 639 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 640 bias-pull-up; 641 drive-strength = <12>; 642 }; 643 644 pcfg_pull_none_smt: pcfg-pull-none-smt { 645 bias-disable; 646 input-schmitt-enable; 647 }; 648 649 pcfg_output_high: pcfg-output-high { 650 output-high; 651 }; 652 653 pcfg_output_low: pcfg-output-low { 654 output-low; 655 }; 656 657 pcfg_input_high: pcfg-input-high { 658 bias-pull-up; 659 input-enable; 660 }; 661 662 pcfg_input: pcfg-input { 663 input-enable; 664 }; 665 666 i2c0 { 667 i2c0_xfer: i2c0-xfer { 668 rockchip,pins = 669 <1 RK_PD0 2 &pcfg_pull_none_smt>, 670 <1 RK_PD1 2 &pcfg_pull_none_smt>; 671 }; 672 }; 673 674 i2c1 { 675 i2c1_xfer: i2c1-xfer { 676 rockchip,pins = 677 <0 RK_PB3 1 &pcfg_pull_none_smt>, 678 <0 RK_PB4 1 &pcfg_pull_none_smt>; 679 }; 680 }; 681 682 i2c2 { 683 i2c2_xfer: i2c2-xfer { 684 rockchip,pins = 685 <2 RK_PA2 3 &pcfg_pull_none_smt>, 686 <2 RK_PA3 3 &pcfg_pull_none_smt>; 687 }; 688 }; 689 690 i2c3-m0 { 691 i2c3m0_xfer: i2c3m0-xfer { 692 rockchip,pins = 693 <0 RK_PB7 2 &pcfg_pull_none_smt>, 694 <0 RK_PC0 2 &pcfg_pull_none_smt>; 695 }; 696 }; 697 698 i2c3-m1 { 699 i2c3m1_xfer: i2c3m1-xfer { 700 rockchip,pins = 701 <3 RK_PB4 2 &pcfg_pull_none_smt>, 702 <3 RK_PB5 2 &pcfg_pull_none_smt>; 703 }; 704 }; 705 706 tsadc { 707 tsadc_otp_gpio: tsadc-otp-gpio { 708 rockchip,pins = 709 <0 RK_PB2 0 &pcfg_pull_none>; 710 }; 711 712 tsadc_otp_out: tsadc-otp-out { 713 rockchip,pins = 714 <0 RK_PB2 1 &pcfg_pull_none>; 715 }; 716 }; 717 718 uart0 { 719 uart0_xfer: uart0-xfer { 720 rockchip,pins = 721 <2 RK_PA1 1 &pcfg_pull_up>, 722 <2 RK_PA0 1 &pcfg_pull_none>; 723 }; 724 725 uart0_cts: uart0-cts { 726 rockchip,pins = 727 <2 RK_PA2 1 &pcfg_pull_none>; 728 }; 729 730 uart0_rts: uart0-rts { 731 rockchip,pins = 732 <2 RK_PA3 1 &pcfg_pull_none>; 733 }; 734 }; 735 736 uart1 { 737 uart1_xfer: uart1-xfer { 738 rockchip,pins = 739 <1 RK_PD1 1 &pcfg_pull_up>, 740 <1 RK_PD0 1 &pcfg_pull_none>; 741 }; 742 743 uart1_cts: uart1-cts { 744 rockchip,pins = 745 <1 RK_PC6 1 &pcfg_pull_none>; 746 }; 747 748 uart1_rts: uart1-rts { 749 rockchip,pins = 750 <1 RK_PC7 1 &pcfg_pull_none>; 751 }; 752 }; 753 754 uart2-m0 { 755 uart2m0_xfer: uart2m0-xfer { 756 rockchip,pins = 757 <1 RK_PC7 2 &pcfg_pull_up>, 758 <1 RK_PC6 2 &pcfg_pull_none>; 759 }; 760 }; 761 762 uart2-m1 { 763 uart2m1_xfer: uart2m1-xfer { 764 rockchip,pins = 765 <4 RK_PD3 2 &pcfg_pull_up>, 766 <4 RK_PD2 2 &pcfg_pull_none>; 767 }; 768 }; 769 770 uart3 { 771 uart3_xfer: uart3-xfer { 772 rockchip,pins = 773 <3 RK_PB5 4 &pcfg_pull_up>, 774 <3 RK_PB4 4 &pcfg_pull_none>; 775 }; 776 }; 777 778 uart4 { 779 780 uart4_xfer: uart4-xfer { 781 rockchip,pins = 782 <4 RK_PB1 1 &pcfg_pull_up>, 783 <4 RK_PB0 1 &pcfg_pull_none>; 784 }; 785 786 uart4_cts: uart4-cts { 787 rockchip,pins = 788 <4 RK_PA6 1 &pcfg_pull_none>; 789 790 }; 791 792 uart4_rts: uart4-rts { 793 rockchip,pins = 794 <4 RK_PA7 1 &pcfg_pull_none>; 795 }; 796 }; 797 798 spi0 { 799 spi0_clk: spi0-clk { 800 rockchip,pins = 801 <2 RK_PA2 2 &pcfg_pull_up>; 802 }; 803 804 spi0_csn0: spi0-csn0 { 805 rockchip,pins = 806 <2 RK_PA3 2 &pcfg_pull_up>; 807 }; 808 809 spi0_miso: spi0-miso { 810 rockchip,pins = 811 <2 RK_PA0 2 &pcfg_pull_up>; 812 }; 813 814 spi0_mosi: spi0-mosi { 815 rockchip,pins = 816 <2 RK_PA1 2 &pcfg_pull_up>; 817 }; 818 }; 819 820 spi1 { 821 spi1_clk: spi1-clk { 822 rockchip,pins = 823 <3 RK_PB3 3 &pcfg_pull_up>; 824 }; 825 826 spi1_csn0: spi1-csn0 { 827 rockchip,pins = 828 <3 RK_PB5 3 &pcfg_pull_up>; 829 }; 830 831 spi1_miso: spi1-miso { 832 rockchip,pins = 833 <3 RK_PB2 3 &pcfg_pull_up>; 834 }; 835 836 spi1_mosi: spi1-mosi { 837 rockchip,pins = 838 <3 RK_PB4 3 &pcfg_pull_up>; 839 }; 840 }; 841 842 spi2 { 843 spi2_clk: spi2-clk { 844 rockchip,pins = 845 <1 RK_PD0 3 &pcfg_pull_up>; 846 }; 847 848 spi2_csn0: spi2-csn0 { 849 rockchip,pins = 850 <1 RK_PD1 3 &pcfg_pull_up>; 851 }; 852 853 spi2_miso: spi2-miso { 854 rockchip,pins = 855 <1 RK_PC6 3 &pcfg_pull_up>; 856 }; 857 858 spi2_mosi: spi2-mosi { 859 rockchip,pins = 860 <1 RK_PC7 3 &pcfg_pull_up>; 861 }; 862 }; 863 864 sdmmc { 865 sdmmc_clk: sdmmc-clk { 866 rockchip,pins = 867 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 868 }; 869 870 sdmmc_cmd: sdmmc-cmd { 871 rockchip,pins = 872 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 873 }; 874 875 sdmmc_pwren: sdmmc-pwren { 876 rockchip,pins = 877 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 878 }; 879 880 sdmmc_bus1: sdmmc-bus1 { 881 rockchip,pins = 882 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 883 }; 884 885 sdmmc_bus4: sdmmc-bus4 { 886 rockchip,pins = 887 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 888 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 889 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 890 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 891 }; 892 893 sdmmc_gpio: sdmmc-gpio { 894 rockchip,pins = 895 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 896 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 897 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 898 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 899 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 900 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 901 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 902 }; 903 }; 904 905 sdio { 906 sdio_clk: sdio-clk { 907 rockchip,pins = 908 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 909 }; 910 911 sdio_cmd: sdio-cmd { 912 rockchip,pins = 913 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 914 }; 915 916 sdio_pwren: sdio-pwren { 917 rockchip,pins = 918 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 919 }; 920 921 sdio_wrpt: sdio-wrpt { 922 rockchip,pins = 923 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 924 }; 925 926 sdio_intn: sdio-intn { 927 rockchip,pins = 928 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 929 }; 930 931 sdio_bus1: sdio-bus1 { 932 rockchip,pins = 933 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 934 }; 935 936 sdio_bus4: sdio-bus4 { 937 rockchip,pins = 938 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 939 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 940 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 941 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 942 }; 943 944 sdio_gpio: sdio-gpio { 945 rockchip,pins = 946 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 947 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 948 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 949 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 950 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 951 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 952 }; 953 }; 954 955 emmc { 956 emmc_clk: emmc-clk { 957 rockchip,pins = 958 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 959 }; 960 961 emmc_cmd: emmc-cmd { 962 rockchip,pins = 963 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 964 }; 965 966 emmc_pwren: emmc-pwren { 967 rockchip,pins = 968 <3 RK_PB3 2 &pcfg_pull_none>; 969 }; 970 971 emmc_rstn: emmc-rstn { 972 rockchip,pins = 973 <3 RK_PB2 2 &pcfg_pull_none>; 974 }; 975 976 emmc_bus1: emmc-bus1 { 977 rockchip,pins = 978 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 979 }; 980 981 emmc_bus4: emmc-bus4 { 982 rockchip,pins = 983 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 984 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 985 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 986 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 987 }; 988 989 emmc_bus8: emmc-bus8 { 990 rockchip,pins = 991 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 992 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 993 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 994 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 995 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 996 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 997 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 998 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 999 }; 1000 }; 1001 1002 flash { 1003 flash_csn0: flash-csn0 { 1004 rockchip,pins = 1005 <3 RK_PB5 1 &pcfg_pull_none>; 1006 }; 1007 1008 flash_rdy: flash-rdy { 1009 rockchip,pins = 1010 <3 RK_PB4 1 &pcfg_pull_none>; 1011 }; 1012 1013 flash_ale: flash-ale { 1014 rockchip,pins = 1015 <3 RK_PB3 1 &pcfg_pull_none>; 1016 }; 1017 1018 flash_cle: flash-cle { 1019 rockchip,pins = 1020 <3 RK_PB1 1 &pcfg_pull_none>; 1021 }; 1022 1023 flash_wrn: flash-wrn { 1024 rockchip,pins = 1025 <3 RK_PB0 1 &pcfg_pull_none>; 1026 }; 1027 1028 flash_rdn: flash-rdn { 1029 rockchip,pins = 1030 <3 RK_PB2 1 &pcfg_pull_none>; 1031 }; 1032 1033 flash_bus8: flash-bus8 { 1034 rockchip,pins = 1035 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1036 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1037 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1038 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1039 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1040 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1041 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1042 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1043 }; 1044 }; 1045 1046 pwm0 { 1047 pwm0_pin: pwm0-pin { 1048 rockchip,pins = 1049 <0 RK_PB5 1 &pcfg_pull_none>; 1050 }; 1051 }; 1052 1053 pwm1 { 1054 pwm1_pin: pwm1-pin { 1055 rockchip,pins = 1056 <0 RK_PB6 1 &pcfg_pull_none>; 1057 }; 1058 }; 1059 1060 pwm2 { 1061 pwm2_pin: pwm2-pin { 1062 rockchip,pins = 1063 <0 RK_PB7 1 &pcfg_pull_none>; 1064 }; 1065 }; 1066 1067 pwm3 { 1068 pwm3_pin: pwm3-pin { 1069 rockchip,pins = 1070 <0 RK_PC0 1 &pcfg_pull_none>; 1071 }; 1072 }; 1073 1074 gmac { 1075 rmii_pins: rmii-pins { 1076 rockchip,pins = 1077 /* mac_txen */ 1078 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1079 /* mac_txd1 */ 1080 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1081 /* mac_txd0 */ 1082 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1083 /* mac_rxd0 */ 1084 <1 RK_PC4 3 &pcfg_pull_none>, 1085 /* mac_rxd1 */ 1086 <1 RK_PC5 3 &pcfg_pull_none>, 1087 /* mac_rxer */ 1088 <1 RK_PB7 3 &pcfg_pull_none>, 1089 /* mac_rxdv */ 1090 <1 RK_PC0 3 &pcfg_pull_none>, 1091 /* mac_mdio */ 1092 <1 RK_PB6 3 &pcfg_pull_none>, 1093 /* mac_mdc */ 1094 <1 RK_PB5 3 &pcfg_pull_none>; 1095 }; 1096 1097 mac_refclk_12ma: mac-refclk-12ma { 1098 rockchip,pins = 1099 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1100 }; 1101 1102 mac_refclk: mac-refclk { 1103 rockchip,pins = 1104 <1 RK_PB4 3 &pcfg_pull_none>; 1105 }; 1106 1107 }; 1108 1109 lcdc { 1110 lcdc_ctl: lcdc-ctl { 1111 rockchip,pins = 1112 /* dclk */ 1113 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1114 /* hsync */ 1115 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1116 /* vsync */ 1117 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1118 /* den */ 1119 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1120 /* d0 */ 1121 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1122 /* d1 */ 1123 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1124 /* d2 */ 1125 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1126 /* d3 */ 1127 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1128 /* d4 */ 1129 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1130 /* d5 */ 1131 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1132 /* d6 */ 1133 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1134 /* d7 */ 1135 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1136 /* d8 */ 1137 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1138 /* d9 */ 1139 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1140 /* d10 */ 1141 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1142 /* d11 */ 1143 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1144 /* d12 */ 1145 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1146 /* d13 */ 1147 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1148 /* d14 */ 1149 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1150 /* d15 */ 1151 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1152 /* d16 */ 1153 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1154 /* d17 */ 1155 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1156 }; 1157 }; 1158 }; 1159}; 1160
