1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 }; 25 26 cpus { 27 #address-cells = <2>; 28 #size-cells = <0>; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a35", "arm,armv8"; 33 reg = <0x0 0x0>; 34 enable-method = "psci"; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a35", "arm,armv8"; 40 reg = <0x0 0x1>; 41 enable-method = "psci"; 42 }; 43 44 cpu2: cpu@2 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35", "arm,armv8"; 47 reg = <0x0 0x2>; 48 enable-method = "psci"; 49 }; 50 51 cpu3: cpu@3 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35", "arm,armv8"; 54 reg = <0x0 0x3>; 55 enable-method = "psci"; 56 }; 57 }; 58 59 arm-pmu { 60 compatible = "arm,cortex-a53-pmu"; 61 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 65 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 66 }; 67 68 display_subsystem: display-subsystem { 69 compatible = "rockchip,display-subsystem"; 70 ports = <&vop_out>; 71 status = "disabled"; 72 73 route { 74 route_rgb: route-rgb { 75 status = "okay"; 76 logo,uboot = "logo.bmp"; 77 logo,kernel = "logo_kernel.bmp"; 78 logo,mode = "center"; 79 charge_logo,mode = "center"; 80 connect = <&vop_out_rgb>; 81 }; 82 }; 83 }; 84 85 psci { 86 compatible = "arm,psci-1.0"; 87 method = "smc"; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 93 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 clock-frequency = <24000000>; 97 }; 98 99 clocks { 100 xin24m: xin24m { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <24000000>; 104 clock-output-names = "xin24m"; 105 }; 106 }; 107 108 grf: grf@ff000000 { 109 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 110 reg = <0x0 0xff000000 0x0 0x10000>; 111 }; 112 113 usb2phy_grf: syscon@ff008000 { 114 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 115 "simple-mfd"; 116 reg = <0x0 0xff008000 0x0 0x4000>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 120 u2phy: usb2-phy@100 { 121 compatible = "rockchip,rk3308-usb2phy", 122 "rockchip,rk3328-usb2phy"; 123 reg = <0x100 0x10>; 124 clocks = <&cru SCLK_USBPHY_REF>; 125 clock-names = "phyclk"; 126 #clock-cells = <0>; 127 assigned-clocks = <&cru USB480M>; 128 assigned-clock-parents = <&u2phy>; 129 clock-output-names = "usb480m_phy"; 130 status = "disabled"; 131 132 u2phy_host: host-port { 133 #phy-cells = <0>; 134 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-names = "linestate"; 136 status = "disabled"; 137 }; 138 139 u2phy_otg: otg-port { 140 #phy-cells = <0>; 141 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 144 interrupt-names = "otg-bvalid", "otg-id", 145 "linestate"; 146 status = "disabled"; 147 }; 148 }; 149 }; 150 151 uart0: serial@ff0a0000 { 152 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 153 reg = <0x0 0xff0a0000 0x0 0x100>; 154 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 156 clock-names = "baudclk", "apb_pclk"; 157 reg-shift = <2>; 158 reg-io-width = <4>; 159 status = "disabled"; 160 }; 161 162 uart1: serial@ff0b0000 { 163 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 164 reg = <0x0 0xff0b0000 0x0 0x100>; 165 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 167 clock-names = "baudclk", "apb_pclk"; 168 reg-shift = <2>; 169 reg-io-width = <4>; 170 status = "disabled"; 171 }; 172 173 uart2: serial@ff0c0000 { 174 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 175 reg = <0x0 0xff0c0000 0x0 0x100>; 176 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 178 clock-names = "baudclk", "apb_pclk"; 179 reg-shift = <2>; 180 reg-io-width = <4>; 181 status = "disabled"; 182 }; 183 184 vop: vop@ff2e0000 { 185 compatible = "rockchip,rk3308-vop"; 186 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 187 reg-names = "regs", "gamma_lut"; 188 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 190 <&cru HCLK_VOP>; 191 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 192 status = "disabled"; 193 194 vop_out: port { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 198 vop_out_rgb: endpoint@0 { 199 reg = <0>; 200 remote-endpoint = <&rgb_in_vop>; 201 }; 202 }; 203 }; 204 205 pwm0: pwm@ff180000 { 206 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 207 reg = <0x0 0xff180000 0x0 0x10>; 208 #pwm-cells = <3>; 209 pinctrl-names = "active"; 210 pinctrl-0 = <&pwm0_pin>; 211 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 212 clock-names = "pwm", "pclk"; 213 status = "disabled"; 214 }; 215 216 pwm1: pwm@ff180010 { 217 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 218 reg = <0x0 0xff180010 0x0 0x10>; 219 #pwm-cells = <3>; 220 pinctrl-names = "active"; 221 pinctrl-0 = <&pwm1_pin>; 222 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 223 clock-names = "pwm", "pclk"; 224 status = "disabled"; 225 }; 226 227 pwm2: pwm@ff180020 { 228 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 229 reg = <0x0 0xff180020 0x0 0x10>; 230 #pwm-cells = <3>; 231 pinctrl-names = "active"; 232 pinctrl-0 = <&pwm2_pin>; 233 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 234 clock-names = "pwm", "pclk"; 235 status = "disabled"; 236 }; 237 238 pwm3: pwm@ff180030 { 239 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 240 reg = <0x0 0xff180030 0x0 0x10>; 241 #pwm-cells = <3>; 242 pinctrl-names = "active"; 243 pinctrl-0 = <&pwm3_pin>; 244 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 245 clock-names = "pwm", "pclk"; 246 status = "disabled"; 247 }; 248 249 rgb: rgb { 250 compatible = "rockchip,rk3308-rgb"; 251 status = "disabled"; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&lcdc_ctl>; 254 255 ports { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 259 port@0 { 260 reg = <0>; 261 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 rgb_in_vop: endpoint@0 { 266 reg = <0>; 267 remote-endpoint = <&vop_out_rgb>; 268 }; 269 }; 270 271 }; 272 }; 273 274 saradc: saradc@ff1e0000 { 275 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 276 reg = <0x0 0xff1e0000 0x0 0x100>; 277 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 278 #io-channel-cells = <1>; 279 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 280 clock-names = "saradc", "apb_pclk"; 281 resets = <&cru SRST_SARADC_P>; 282 reset-names = "saradc-apb"; 283 status = "disabled"; 284 }; 285 286 i2s0: i2s@ff300000 { 287 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 288 reg = <0x0 0xff300000 0x0 0x10000>; 289 }; 290 291 i2s1: i2s@ff310000 { 292 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 293 reg = <0x0 0xff100000 0x0 0x10000>; 294 }; 295 296 i2s2: i2s@ff320000 { 297 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 298 reg = <0x0 0xff320000 0x0 0x10000>; 299 }; 300 301 i2s3: i2s@ff330000 { 302 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 303 reg = <0x0 0xff330000 0x0 0x10000>; 304 }; 305 306 vad: vad@ff3c0000 { 307 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 308 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 309 reg-names = "vad", "vad-memory"; 310 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 311 rockchip,audio-src = <0>; 312 rockchip,audio-chnl-num = <8>; 313 rockchip,audio-chnl = <0>; 314 rockchip,mode = <0>; 315 }; 316 317 usb20_otg: usb@ff400000 { 318 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 319 "snps,dwc2"; 320 reg = <0x0 0xff400000 0x0 0x40000>; 321 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cru HCLK_OTG>; 323 clock-names = "otg"; 324 dr_mode = "otg"; 325 g-np-tx-fifo-size = <16>; 326 g-rx-fifo-size = <275>; 327 g-tx-fifo-size = <256 128 128 64 64 32>; 328 g-use-dma; 329 phys = <&u2phy_otg>; 330 phy-names = "usb2-phy"; 331 status = "disabled"; 332 }; 333 334 usb_host0_ehci: usb@ff440000 { 335 compatible = "generic-ehci"; 336 reg = <0x0 0xff440000 0x0 0x10000>; 337 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 339 <&u2phy>; 340 clock-names = "usbhost", "arbiter", "utmi"; 341 phys = <&u2phy_host>; 342 phy-names = "usb"; 343 status = "disabled"; 344 }; 345 346 usb_host0_ohci: usb@ff450000 { 347 compatible = "generic-ohci"; 348 reg = <0x0 0xff450000 0x0 0x10000>; 349 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 351 <&u2phy>; 352 clock-names = "usbhost", "arbiter", "utmi"; 353 phys = <&u2phy_host>; 354 phy-names = "usb"; 355 }; 356 357 sdmmc: dwmmc@ff480000 { 358 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 359 reg = <0x0 0xff480000 0x0 0x4000>; 360 max-frequency = <150000000>; 361 bus-width = <4>; 362 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 363 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 364 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 365 fifo-depth = <0x100>; 366 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 369 status = "disabled"; 370 }; 371 372 emmc: dwmmc@ff490000 { 373 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 374 reg = <0x0 0xff490000 0x0 0x4000>; 375 max-frequency = <150000000>; 376 bus-width = <8>; 377 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 378 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 379 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 380 fifo-depth = <0x100>; 381 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 382 status = "disabled"; 383 }; 384 385 sdio: dwmmc@ff4a0000 { 386 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 387 reg = <0x0 0xff4a0000 0x0 0x4000>; 388 max-frequency = <150000000>; 389 bus-width = <4>; 390 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 391 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 392 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 393 fifo-depth = <0x100>; 394 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 397 status = "disabled"; 398 }; 399 400 nandc: nandc@ff4b0000 { 401 compatible = "rockchip,rk-nandc"; 402 reg = <0x0 0xff4b0000 0x0 0x4000>; 403 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 404 nandc_id = <0>; 405 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 406 clock-names = "clk_nandc", "hclk_nandc"; 407 status = "disabled"; 408 }; 409 410 cru: clock-controller@ff500000 { 411 compatible = "rockchip,rk3308-cru"; 412 reg = <0x0 0xff500000 0x0 0x1000>; 413 rockchip,grf = <&grf>; 414 #clock-cells = <1>; 415 #reset-cells = <1>; 416 }; 417 418 gic: interrupt-controller@ff580000 { 419 compatible = "arm,gic-400"; 420 #interrupt-cells = <3>; 421 #address-cells = <0>; 422 interrupt-controller; 423 424 reg = <0x0 0xff581000 0x0 0x1000>, 425 <0x0 0xff582000 0x0 0x2000>, 426 <0x0 0xff584000 0x0 0x2000>, 427 <0x0 0xff586000 0x0 0x2000>; 428 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 429 }; 430 431 pinctrl: pinctrl { 432 compatible = "rockchip,rk3308-pinctrl"; 433 rockchip,grf = <&grf>; 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges; 437 438 gpio0: gpio0@ff220000 { 439 compatible = "rockchip,gpio-bank"; 440 reg = <0x0 0xff220000 0x0 0x100>; 441 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 442 //clocks = <&cru PCLK_GPIO0>; 443 clocks = <&xin24m>; 444 gpio-controller; 445 #gpio-cells = <2>; 446 447 interrupt-controller; 448 #interrupt-cells = <2>; 449 }; 450 451 gpio1: gpio1@ff230000 { 452 compatible = "rockchip,gpio-bank"; 453 reg = <0x0 0xff230000 0x0 0x100>; 454 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 455 //clocks = <&cru PCLK_GPIO1>; 456 clocks = <&xin24m>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 }; 463 464 gpio2: gpio2@ff240000 { 465 compatible = "rockchip,gpio-bank"; 466 reg = <0x0 0xff240000 0x0 0x100>; 467 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 468 //clocks = <&cru PCLK_GPIO2>; 469 clocks = <&xin24m>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 }; 476 477 gpio3: gpio3@ff250000 { 478 compatible = "rockchip,gpio-bank"; 479 reg = <0x0 0xff250000 0x0 0x100>; 480 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 481 //clocks = <&cru PCLK_GPIO3>; 482 clocks = <&xin24m>; 483 gpio-controller; 484 #gpio-cells = <2>; 485 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 }; 489 490 gpio4: gpio4@ff260000 { 491 compatible = "rockchip,gpio-bank"; 492 reg = <0x0 0xff260000 0x0 0x100>; 493 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 494 //clocks = <&cru PCLK_GPIO4>; 495 clocks = <&xin24m>; 496 gpio-controller; 497 #gpio-cells = <2>; 498 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 }; 502 503 pcfg_pull_up: pcfg-pull-up { 504 bias-pull-up; 505 }; 506 507 pcfg_pull_down: pcfg-pull-down { 508 bias-pull-down; 509 }; 510 511 pcfg_pull_none: pcfg-pull-none { 512 bias-disable; 513 }; 514 515 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 516 bias-disable; 517 drive-strength = <2>; 518 }; 519 520 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 521 bias-pull-up; 522 drive-strength = <2>; 523 }; 524 525 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 526 bias-pull-up; 527 drive-strength = <4>; 528 }; 529 530 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 531 bias-disable; 532 drive-strength = <4>; 533 }; 534 535 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 536 bias-pull-down; 537 drive-strength = <4>; 538 }; 539 540 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 541 bias-disable; 542 drive-strength = <8>; 543 }; 544 545 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 546 bias-pull-up; 547 drive-strength = <8>; 548 }; 549 550 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 551 bias-disable; 552 drive-strength = <12>; 553 }; 554 555 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 556 bias-pull-up; 557 drive-strength = <12>; 558 }; 559 560 pcfg_pull_none_smt: pcfg-pull-none-smt { 561 bias-disable; 562 input-schmitt-enable; 563 }; 564 565 pcfg_output_high: pcfg-output-high { 566 output-high; 567 }; 568 569 pcfg_output_low: pcfg-output-low { 570 output-low; 571 }; 572 573 pcfg_input_high: pcfg-input-high { 574 bias-pull-up; 575 input-enable; 576 }; 577 578 pcfg_input: pcfg-input { 579 input-enable; 580 }; 581 582 i2c0 { 583 i2c0_xfer: i2c0-xfer { 584 rockchip,pins = 585 <1 RK_PD0 2 &pcfg_pull_none_smt>, 586 <1 RK_PD1 2 &pcfg_pull_none_smt>; 587 }; 588 }; 589 590 i2c1 { 591 i2c1_xfer: i2c1-xfer { 592 rockchip,pins = 593 <0 RK_PB3 1 &pcfg_pull_none_smt>, 594 <0 RK_PB4 1 &pcfg_pull_none_smt>; 595 }; 596 }; 597 598 i2c2 { 599 i2c2_xfer: i2c2-xfer { 600 rockchip,pins = 601 <2 RK_PA2 3 &pcfg_pull_none_smt>, 602 <2 RK_PA3 3 &pcfg_pull_none_smt>; 603 }; 604 }; 605 606 i2c3-m0 { 607 i2c3m0_xfer: i2c3m0-xfer { 608 rockchip,pins = 609 <0 RK_PB7 2 &pcfg_pull_none_smt>, 610 <0 RK_PC0 2 &pcfg_pull_none_smt>; 611 }; 612 }; 613 614 i2c3-m1 { 615 i2c3m1_xfer: i2c3m1-xfer { 616 rockchip,pins = 617 <3 RK_PB4 2 &pcfg_pull_none_smt>, 618 <3 RK_PB5 2 &pcfg_pull_none_smt>; 619 }; 620 }; 621 622 tsadc { 623 tsadc_otp_gpio: tsadc-otp-gpio { 624 rockchip,pins = 625 <0 RK_PB2 0 &pcfg_pull_none>; 626 }; 627 628 tsadc_otp_out: tsadc-otp-out { 629 rockchip,pins = 630 <0 RK_PB2 1 &pcfg_pull_none>; 631 }; 632 }; 633 634 uart0 { 635 uart0_xfer: uart0-xfer { 636 rockchip,pins = 637 <2 RK_PA1 1 &pcfg_pull_up>, 638 <2 RK_PA0 1 &pcfg_pull_none>; 639 }; 640 641 uart0_cts: uart0-cts { 642 rockchip,pins = 643 <2 RK_PA2 1 &pcfg_pull_none>; 644 }; 645 646 uart0_rts: uart0-rts { 647 rockchip,pins = 648 <2 RK_PA3 1 &pcfg_pull_none>; 649 }; 650 }; 651 652 uart1 { 653 uart1_xfer: uart1-xfer { 654 rockchip,pins = 655 <1 RK_PD1 1 &pcfg_pull_up>, 656 <1 RK_PD0 1 &pcfg_pull_none>; 657 }; 658 659 uart1_cts: uart1-cts { 660 rockchip,pins = 661 <1 RK_PC6 1 &pcfg_pull_none>; 662 }; 663 664 uart1_rts: uart1-rts { 665 rockchip,pins = 666 <1 RK_PC7 1 &pcfg_pull_none>; 667 }; 668 }; 669 670 uart2-m0 { 671 uart2m0_xfer: uart2m0-xfer { 672 rockchip,pins = 673 <1 RK_PC7 2 &pcfg_pull_up>, 674 <1 RK_PC6 2 &pcfg_pull_none>; 675 }; 676 }; 677 678 uart2-m1 { 679 uart2m1_xfer: uart2m1-xfer { 680 rockchip,pins = 681 <4 RK_PD3 2 &pcfg_pull_up>, 682 <4 RK_PD2 2 &pcfg_pull_none>; 683 }; 684 }; 685 686 uart3 { 687 uart3_xfer: uart3-xfer { 688 rockchip,pins = 689 <3 RK_PB5 4 &pcfg_pull_up>, 690 <3 RK_PB4 4 &pcfg_pull_none>; 691 }; 692 }; 693 694 uart4 { 695 696 uart4_xfer: uart4-xfer { 697 rockchip,pins = 698 <4 RK_PB1 1 &pcfg_pull_up>, 699 <4 RK_PB0 1 &pcfg_pull_none>; 700 }; 701 702 uart4_cts: uart4-cts { 703 rockchip,pins = 704 <4 RK_PA6 1 &pcfg_pull_none>; 705 706 }; 707 708 uart4_rts: uart4-rts { 709 rockchip,pins = 710 <4 RK_PA7 1 &pcfg_pull_none>; 711 }; 712 }; 713 714 spi0 { 715 spi0_clk: spi0-clk { 716 rockchip,pins = 717 <2 RK_PA2 2 &pcfg_pull_up>; 718 }; 719 720 spi0_csn0: spi0-csn0 { 721 rockchip,pins = 722 <2 RK_PA3 2 &pcfg_pull_up>; 723 }; 724 725 spi0_miso: spi0-miso { 726 rockchip,pins = 727 <2 RK_PA0 2 &pcfg_pull_up>; 728 }; 729 730 spi0_mosi: spi0-mosi { 731 rockchip,pins = 732 <2 RK_PA1 2 &pcfg_pull_up>; 733 }; 734 }; 735 736 spi1 { 737 spi1_clk: spi1-clk { 738 rockchip,pins = 739 <3 RK_PB3 3 &pcfg_pull_up>; 740 }; 741 742 spi1_csn0: spi1-csn0 { 743 rockchip,pins = 744 <3 RK_PB5 3 &pcfg_pull_up>; 745 }; 746 747 spi1_miso: spi1-miso { 748 rockchip,pins = 749 <3 RK_PB2 3 &pcfg_pull_up>; 750 }; 751 752 spi1_mosi: spi1-mosi { 753 rockchip,pins = 754 <3 RK_PB4 3 &pcfg_pull_up>; 755 }; 756 }; 757 758 spi2 { 759 spi2_clk: spi2-clk { 760 rockchip,pins = 761 <1 RK_PD0 3 &pcfg_pull_up>; 762 }; 763 764 spi2_csn0: spi2-csn0 { 765 rockchip,pins = 766 <1 RK_PD1 3 &pcfg_pull_up>; 767 }; 768 769 spi2_miso: spi2-miso { 770 rockchip,pins = 771 <1 RK_PC6 3 &pcfg_pull_up>; 772 }; 773 774 spi2_mosi: spi2-mosi { 775 rockchip,pins = 776 <1 RK_PC7 3 &pcfg_pull_up>; 777 }; 778 }; 779 780 sdmmc { 781 sdmmc_clk: sdmmc-clk { 782 rockchip,pins = 783 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 784 }; 785 786 sdmmc_cmd: sdmmc-cmd { 787 rockchip,pins = 788 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 789 }; 790 791 sdmmc_pwren: sdmmc-pwren { 792 rockchip,pins = 793 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 794 }; 795 796 sdmmc_bus1: sdmmc-bus1 { 797 rockchip,pins = 798 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 799 }; 800 801 sdmmc_bus4: sdmmc-bus4 { 802 rockchip,pins = 803 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 804 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 805 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 806 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 807 }; 808 809 sdmmc_gpio: sdmmc-gpio { 810 rockchip,pins = 811 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 812 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 813 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 814 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 815 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 816 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 817 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 818 }; 819 }; 820 821 sdio { 822 sdio_clk: sdio-clk { 823 rockchip,pins = 824 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 825 }; 826 827 sdio_cmd: sdio-cmd { 828 rockchip,pins = 829 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 830 }; 831 832 sdio_pwren: sdio-pwren { 833 rockchip,pins = 834 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 835 }; 836 837 sdio_wrpt: sdio-wrpt { 838 rockchip,pins = 839 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 840 }; 841 842 sdio_intn: sdio-intn { 843 rockchip,pins = 844 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 845 }; 846 847 sdio_bus1: sdio-bus1 { 848 rockchip,pins = 849 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 850 }; 851 852 sdio_bus4: sdio-bus4 { 853 rockchip,pins = 854 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 855 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 856 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 857 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 858 }; 859 860 sdio_gpio: sdio-gpio { 861 rockchip,pins = 862 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 863 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 864 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 865 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 866 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 867 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 868 }; 869 }; 870 871 emmc { 872 emmc_clk: emmc-clk { 873 rockchip,pins = 874 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 875 }; 876 877 emmc_cmd: emmc-cmd { 878 rockchip,pins = 879 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 880 }; 881 882 emmc_pwren: emmc-pwren { 883 rockchip,pins = 884 <3 RK_PB3 2 &pcfg_pull_none>; 885 }; 886 887 emmc_rstn: emmc-rstn { 888 rockchip,pins = 889 <3 RK_PB2 2 &pcfg_pull_none>; 890 }; 891 892 emmc_bus1: emmc-bus1 { 893 rockchip,pins = 894 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 895 }; 896 897 emmc_bus4: emmc-bus4 { 898 rockchip,pins = 899 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 900 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 901 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 902 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 903 }; 904 905 emmc_bus8: emmc-bus8 { 906 rockchip,pins = 907 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 908 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 909 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 910 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 911 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 912 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 913 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 914 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 915 }; 916 }; 917 918 flash { 919 flash_csn0: flash-csn0 { 920 rockchip,pins = 921 <3 RK_PB5 1 &pcfg_pull_none>; 922 }; 923 924 flash_rdy: flash-rdy { 925 rockchip,pins = 926 <3 RK_PB4 1 &pcfg_pull_none>; 927 }; 928 929 flash_ale: flash-ale { 930 rockchip,pins = 931 <3 RK_PB3 1 &pcfg_pull_none>; 932 }; 933 934 flash_cle: flash-cle { 935 rockchip,pins = 936 <3 RK_PB1 1 &pcfg_pull_none>; 937 }; 938 939 flash_wrn: flash-wrn { 940 rockchip,pins = 941 <3 RK_PB0 1 &pcfg_pull_none>; 942 }; 943 944 flash_rdn: flash-rdn { 945 rockchip,pins = 946 <3 RK_PB2 1 &pcfg_pull_none>; 947 }; 948 949 flash_bus8: flash-bus8 { 950 rockchip,pins = 951 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 952 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 953 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 954 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 955 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 956 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 957 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 958 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 959 }; 960 }; 961 962 pwm0 { 963 pwm0_pin: pwm0-pin { 964 rockchip,pins = 965 <0 RK_PB5 1 &pcfg_pull_none>; 966 }; 967 }; 968 969 pwm1 { 970 pwm1_pin: pwm1-pin { 971 rockchip,pins = 972 <0 RK_PB6 1 &pcfg_pull_none>; 973 }; 974 }; 975 976 pwm2 { 977 pwm2_pin: pwm2-pin { 978 rockchip,pins = 979 <0 RK_PB7 1 &pcfg_pull_none>; 980 }; 981 }; 982 983 pwm3 { 984 pwm3_pin: pwm3-pin { 985 rockchip,pins = 986 <0 RK_PC0 1 &pcfg_pull_none>; 987 }; 988 }; 989 990 gmac { 991 rmii_pins: rmii-pins { 992 rockchip,pins = 993 /* mac_txen */ 994 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 995 /* mac_txd1 */ 996 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 997 /* mac_txd0 */ 998 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 999 /* mac_rxd0 */ 1000 <1 RK_PC4 3 &pcfg_pull_none>, 1001 /* mac_rxd1 */ 1002 <1 RK_PC5 3 &pcfg_pull_none>, 1003 /* mac_rxer */ 1004 <1 RK_PB7 3 &pcfg_pull_none>, 1005 /* mac_rxdv */ 1006 <1 RK_PC0 3 &pcfg_pull_none>, 1007 /* mac_mdio */ 1008 <1 RK_PB6 3 &pcfg_pull_none>, 1009 /* mac_mdc */ 1010 <1 RK_PB5 3 &pcfg_pull_none>, 1011 /* mac_clk */ 1012 <1 RK_PB4 3 &pcfg_pull_none>; 1013 }; 1014 }; 1015 1016 lcdc { 1017 lcdc_ctl: lcdc-ctl { 1018 rockchip,pins = 1019 /* dclk */ 1020 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1021 /* hsync */ 1022 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1023 /* vsync */ 1024 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1025 /* den */ 1026 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1027 /* d0 */ 1028 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1029 /* d1 */ 1030 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1031 /* d2 */ 1032 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1033 /* d3 */ 1034 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1035 /* d4 */ 1036 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1037 /* d5 */ 1038 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1039 /* d6 */ 1040 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1041 /* d7 */ 1042 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1043 /* d8 */ 1044 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1045 /* d9 */ 1046 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1047 /* d10 */ 1048 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1049 /* d11 */ 1050 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1051 /* d12 */ 1052 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1053 /* d13 */ 1054 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1055 /* d14 */ 1056 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1057 /* d15 */ 1058 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1059 /* d16 */ 1060 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1061 /* d17 */ 1062 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1063 }; 1064 }; 1065 }; 1066}; 1067
