1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a35", "arm,armv8"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a35", "arm,armv8"; 42 reg = <0x0 0x1>; 43 enable-method = "psci"; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a35", "arm,armv8"; 49 reg = <0x0 0x2>; 50 enable-method = "psci"; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35", "arm,armv8"; 56 reg = <0x0 0x3>; 57 enable-method = "psci"; 58 }; 59 }; 60 61 arm-pmu { 62 compatible = "arm,cortex-a53-pmu"; 63 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 68 }; 69 70 display_subsystem: display-subsystem { 71 compatible = "rockchip,display-subsystem"; 72 ports = <&vop_out>; 73 status = "disabled"; 74 75 route { 76 route_rgb: route-rgb { 77 status = "okay"; 78 logo,uboot = "logo.bmp"; 79 logo,kernel = "logo_kernel.bmp"; 80 logo,mode = "center"; 81 charge_logo,mode = "center"; 82 connect = <&vop_out_rgb>; 83 }; 84 }; 85 }; 86 87 dmc: dmc@20004000 { 88 compatible = "rockchip,rk3308-dmc"; 89 reg = <0x0 0xff010000 0x0 0x10000>; 90 }; 91 92 psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 timer { 98 compatible = "arm,armv8-timer"; 99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 clock-frequency = <24000000>; 104 }; 105 106 clocks { 107 xin24m: xin24m { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <24000000>; 111 clock-output-names = "xin24m"; 112 }; 113 }; 114 115 grf: grf@ff000000 { 116 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 117 reg = <0x0 0xff000000 0x0 0x10000>; 118 }; 119 120 usb2phy_grf: syscon@ff008000 { 121 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 122 "simple-mfd"; 123 reg = <0x0 0xff008000 0x0 0x4000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 127 u2phy: usb2-phy@100 { 128 compatible = "rockchip,rk3308-usb2phy", 129 "rockchip,rk3328-usb2phy"; 130 reg = <0x100 0x10>; 131 clocks = <&cru SCLK_USBPHY_REF>; 132 clock-names = "phyclk"; 133 #clock-cells = <0>; 134 assigned-clocks = <&cru USB480M>; 135 assigned-clock-parents = <&u2phy>; 136 clock-output-names = "usb480m_phy"; 137 status = "disabled"; 138 139 u2phy_host: host-port { 140 #phy-cells = <0>; 141 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-names = "linestate"; 143 status = "disabled"; 144 }; 145 146 u2phy_otg: otg-port { 147 #phy-cells = <0>; 148 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-names = "otg-bvalid", "otg-id", 152 "linestate"; 153 status = "disabled"; 154 }; 155 }; 156 }; 157 158 uart0: serial@ff0a0000 { 159 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 160 reg = <0x0 0xff0a0000 0x0 0x100>; 161 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 163 clock-names = "baudclk", "apb_pclk"; 164 reg-shift = <2>; 165 reg-io-width = <4>; 166 status = "disabled"; 167 }; 168 169 uart1: serial@ff0b0000 { 170 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 171 reg = <0x0 0xff0b0000 0x0 0x100>; 172 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 174 clock-names = "baudclk", "apb_pclk"; 175 reg-shift = <2>; 176 reg-io-width = <4>; 177 status = "disabled"; 178 }; 179 180 uart2: serial@ff0c0000 { 181 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 182 reg = <0x0 0xff0c0000 0x0 0x100>; 183 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 185 clock-names = "baudclk", "apb_pclk"; 186 reg-shift = <2>; 187 reg-io-width = <4>; 188 status = "disabled"; 189 }; 190 191 uart3: serial@ff0d0000 { 192 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 193 reg = <0x0 0xff0d0000 0x0 0x100>; 194 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 196 clock-names = "baudclk", "apb_pclk"; 197 reg-shift = <2>; 198 reg-io-width = <4>; 199 status = "disabled"; 200 }; 201 202 uart4: serial@ff0e0000 { 203 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 204 reg = <0x0 0xff0e0000 0x0 0x100>; 205 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 207 clock-names = "baudclk", "apb_pclk"; 208 reg-shift = <2>; 209 reg-io-width = <4>; 210 status = "disabled"; 211 }; 212 213 vop: vop@ff2e0000 { 214 compatible = "rockchip,rk3308-vop"; 215 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 216 reg-names = "regs", "gamma_lut"; 217 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 219 <&cru HCLK_VOP>; 220 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 221 status = "disabled"; 222 223 vop_out: port { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 vop_out_rgb: endpoint@0 { 228 reg = <0>; 229 remote-endpoint = <&rgb_in_vop>; 230 }; 231 }; 232 }; 233 234 pwm0: pwm@ff180000 { 235 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 236 reg = <0x0 0xff180000 0x0 0x10>; 237 #pwm-cells = <3>; 238 pinctrl-names = "active"; 239 pinctrl-0 = <&pwm0_pin>; 240 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 241 clock-names = "pwm", "pclk"; 242 status = "disabled"; 243 }; 244 245 pwm1: pwm@ff180010 { 246 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 247 reg = <0x0 0xff180010 0x0 0x10>; 248 #pwm-cells = <3>; 249 pinctrl-names = "active"; 250 pinctrl-0 = <&pwm1_pin>; 251 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 252 clock-names = "pwm", "pclk"; 253 status = "disabled"; 254 }; 255 256 pwm2: pwm@ff180020 { 257 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 258 reg = <0x0 0xff180020 0x0 0x10>; 259 #pwm-cells = <3>; 260 pinctrl-names = "active"; 261 pinctrl-0 = <&pwm2_pin>; 262 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 263 clock-names = "pwm", "pclk"; 264 status = "disabled"; 265 }; 266 267 pwm3: pwm@ff180030 { 268 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 269 reg = <0x0 0xff180030 0x0 0x10>; 270 #pwm-cells = <3>; 271 pinctrl-names = "active"; 272 pinctrl-0 = <&pwm3_pin>; 273 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 274 clock-names = "pwm", "pclk"; 275 status = "disabled"; 276 }; 277 278 rgb: rgb { 279 compatible = "rockchip,rk3308-rgb"; 280 status = "disabled"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&lcdc_ctl>; 283 284 ports { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 port@0 { 289 reg = <0>; 290 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 rgb_in_vop: endpoint@0 { 295 reg = <0>; 296 remote-endpoint = <&vop_out_rgb>; 297 }; 298 }; 299 300 }; 301 }; 302 303 saradc: saradc@ff1e0000 { 304 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 305 reg = <0x0 0xff1e0000 0x0 0x100>; 306 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 307 #io-channel-cells = <1>; 308 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 309 clock-names = "saradc", "apb_pclk"; 310 resets = <&cru SRST_SARADC_P>; 311 reset-names = "saradc-apb"; 312 status = "disabled"; 313 }; 314 315 i2s0: i2s@ff300000 { 316 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 317 reg = <0x0 0xff300000 0x0 0x10000>; 318 }; 319 320 i2s1: i2s@ff310000 { 321 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 322 reg = <0x0 0xff100000 0x0 0x10000>; 323 }; 324 325 i2s2: i2s@ff320000 { 326 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 327 reg = <0x0 0xff320000 0x0 0x10000>; 328 }; 329 330 i2s3: i2s@ff330000 { 331 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 332 reg = <0x0 0xff330000 0x0 0x10000>; 333 }; 334 335 vad: vad@ff3c0000 { 336 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 337 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 338 reg-names = "vad", "vad-memory"; 339 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 340 rockchip,audio-src = <0>; 341 rockchip,audio-chnl-num = <8>; 342 rockchip,audio-chnl = <0>; 343 rockchip,mode = <0>; 344 }; 345 346 usb20_otg: usb@ff400000 { 347 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 348 "snps,dwc2"; 349 reg = <0x0 0xff400000 0x0 0x40000>; 350 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cru HCLK_OTG>; 352 clock-names = "otg"; 353 dr_mode = "otg"; 354 g-np-tx-fifo-size = <16>; 355 g-rx-fifo-size = <275>; 356 g-tx-fifo-size = <256 128 128 64 64 32>; 357 g-use-dma; 358 phys = <&u2phy_otg>; 359 phy-names = "usb2-phy"; 360 status = "disabled"; 361 }; 362 363 usb_host0_ehci: usb@ff440000 { 364 compatible = "generic-ehci"; 365 reg = <0x0 0xff440000 0x0 0x10000>; 366 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 368 <&u2phy>; 369 clock-names = "usbhost", "arbiter", "utmi"; 370 phys = <&u2phy_host>; 371 phy-names = "usb"; 372 status = "disabled"; 373 }; 374 375 usb_host0_ohci: usb@ff450000 { 376 compatible = "generic-ohci"; 377 reg = <0x0 0xff450000 0x0 0x10000>; 378 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 380 <&u2phy>; 381 clock-names = "usbhost", "arbiter", "utmi"; 382 phys = <&u2phy_host>; 383 phy-names = "usb"; 384 }; 385 386 sdmmc: dwmmc@ff480000 { 387 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 388 reg = <0x0 0xff480000 0x0 0x4000>; 389 max-frequency = <150000000>; 390 bus-width = <4>; 391 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 392 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 393 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 394 fifo-depth = <0x100>; 395 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 396 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 399 status = "disabled"; 400 }; 401 402 emmc: dwmmc@ff490000 { 403 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 404 reg = <0x0 0xff490000 0x0 0x4000>; 405 max-frequency = <150000000>; 406 bus-width = <8>; 407 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 408 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 409 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 410 fifo-depth = <0x100>; 411 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 412 status = "disabled"; 413 }; 414 415 sdio: dwmmc@ff4a0000 { 416 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 417 reg = <0x0 0xff4a0000 0x0 0x4000>; 418 max-frequency = <150000000>; 419 bus-width = <4>; 420 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 421 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 422 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 423 fifo-depth = <0x100>; 424 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 427 status = "disabled"; 428 }; 429 430 nandc: nandc@ff4b0000 { 431 compatible = "rockchip,rk-nandc"; 432 reg = <0x0 0xff4b0000 0x0 0x4000>; 433 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 434 nandc_id = <0>; 435 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 436 clock-names = "clk_nandc", "hclk_nandc"; 437 status = "disabled"; 438 }; 439 440 441 sfc: sfc@ff4c0000 { 442 compatible = "rockchip,rksfc"; 443 reg = <0x0 0xff4c0000 0x0 0x4000>; 444 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 446 clock-names = "clk_sfc", "hclk_sfc"; 447 status = "disabled"; 448 }; 449 450 cru: clock-controller@ff500000 { 451 compatible = "rockchip,rk3308-cru"; 452 reg = <0x0 0xff500000 0x0 0x1000>; 453 rockchip,grf = <&grf>; 454 #clock-cells = <1>; 455 #reset-cells = <1>; 456 }; 457 458 gic: interrupt-controller@ff580000 { 459 compatible = "arm,gic-400"; 460 #interrupt-cells = <3>; 461 #address-cells = <0>; 462 interrupt-controller; 463 464 reg = <0x0 0xff581000 0x0 0x1000>, 465 <0x0 0xff582000 0x0 0x2000>, 466 <0x0 0xff584000 0x0 0x2000>, 467 <0x0 0xff586000 0x0 0x2000>; 468 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 469 }; 470 471 pinctrl: pinctrl { 472 compatible = "rockchip,rk3308-pinctrl"; 473 rockchip,grf = <&grf>; 474 #address-cells = <2>; 475 #size-cells = <2>; 476 ranges; 477 478 gpio0: gpio0@ff220000 { 479 compatible = "rockchip,gpio-bank"; 480 reg = <0x0 0xff220000 0x0 0x100>; 481 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 482 //clocks = <&cru PCLK_GPIO0>; 483 clocks = <&xin24m>; 484 gpio-controller; 485 #gpio-cells = <2>; 486 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 }; 490 491 gpio1: gpio1@ff230000 { 492 compatible = "rockchip,gpio-bank"; 493 reg = <0x0 0xff230000 0x0 0x100>; 494 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 495 //clocks = <&cru PCLK_GPIO1>; 496 clocks = <&xin24m>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 500 interrupt-controller; 501 #interrupt-cells = <2>; 502 }; 503 504 gpio2: gpio2@ff240000 { 505 compatible = "rockchip,gpio-bank"; 506 reg = <0x0 0xff240000 0x0 0x100>; 507 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 508 //clocks = <&cru PCLK_GPIO2>; 509 clocks = <&xin24m>; 510 gpio-controller; 511 #gpio-cells = <2>; 512 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 }; 516 517 gpio3: gpio3@ff250000 { 518 compatible = "rockchip,gpio-bank"; 519 reg = <0x0 0xff250000 0x0 0x100>; 520 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 521 //clocks = <&cru PCLK_GPIO3>; 522 clocks = <&xin24m>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 }; 529 530 gpio4: gpio4@ff260000 { 531 compatible = "rockchip,gpio-bank"; 532 reg = <0x0 0xff260000 0x0 0x100>; 533 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 534 //clocks = <&cru PCLK_GPIO4>; 535 clocks = <&xin24m>; 536 gpio-controller; 537 #gpio-cells = <2>; 538 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 }; 542 543 pcfg_pull_up: pcfg-pull-up { 544 bias-pull-up; 545 }; 546 547 pcfg_pull_down: pcfg-pull-down { 548 bias-pull-down; 549 }; 550 551 pcfg_pull_none: pcfg-pull-none { 552 bias-disable; 553 }; 554 555 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 556 bias-disable; 557 drive-strength = <2>; 558 }; 559 560 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 561 bias-pull-up; 562 drive-strength = <2>; 563 }; 564 565 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 566 bias-pull-up; 567 drive-strength = <4>; 568 }; 569 570 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 571 bias-disable; 572 drive-strength = <4>; 573 }; 574 575 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 576 bias-pull-down; 577 drive-strength = <4>; 578 }; 579 580 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 581 bias-disable; 582 drive-strength = <8>; 583 }; 584 585 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 586 bias-pull-up; 587 drive-strength = <8>; 588 }; 589 590 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 591 bias-disable; 592 drive-strength = <12>; 593 }; 594 595 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 596 bias-pull-up; 597 drive-strength = <12>; 598 }; 599 600 pcfg_pull_none_smt: pcfg-pull-none-smt { 601 bias-disable; 602 input-schmitt-enable; 603 }; 604 605 pcfg_output_high: pcfg-output-high { 606 output-high; 607 }; 608 609 pcfg_output_low: pcfg-output-low { 610 output-low; 611 }; 612 613 pcfg_input_high: pcfg-input-high { 614 bias-pull-up; 615 input-enable; 616 }; 617 618 pcfg_input: pcfg-input { 619 input-enable; 620 }; 621 622 i2c0 { 623 i2c0_xfer: i2c0-xfer { 624 rockchip,pins = 625 <1 RK_PD0 2 &pcfg_pull_none_smt>, 626 <1 RK_PD1 2 &pcfg_pull_none_smt>; 627 }; 628 }; 629 630 i2c1 { 631 i2c1_xfer: i2c1-xfer { 632 rockchip,pins = 633 <0 RK_PB3 1 &pcfg_pull_none_smt>, 634 <0 RK_PB4 1 &pcfg_pull_none_smt>; 635 }; 636 }; 637 638 i2c2 { 639 i2c2_xfer: i2c2-xfer { 640 rockchip,pins = 641 <2 RK_PA2 3 &pcfg_pull_none_smt>, 642 <2 RK_PA3 3 &pcfg_pull_none_smt>; 643 }; 644 }; 645 646 i2c3-m0 { 647 i2c3m0_xfer: i2c3m0-xfer { 648 rockchip,pins = 649 <0 RK_PB7 2 &pcfg_pull_none_smt>, 650 <0 RK_PC0 2 &pcfg_pull_none_smt>; 651 }; 652 }; 653 654 i2c3-m1 { 655 i2c3m1_xfer: i2c3m1-xfer { 656 rockchip,pins = 657 <3 RK_PB4 2 &pcfg_pull_none_smt>, 658 <3 RK_PB5 2 &pcfg_pull_none_smt>; 659 }; 660 }; 661 662 tsadc { 663 tsadc_otp_gpio: tsadc-otp-gpio { 664 rockchip,pins = 665 <0 RK_PB2 0 &pcfg_pull_none>; 666 }; 667 668 tsadc_otp_out: tsadc-otp-out { 669 rockchip,pins = 670 <0 RK_PB2 1 &pcfg_pull_none>; 671 }; 672 }; 673 674 uart0 { 675 uart0_xfer: uart0-xfer { 676 rockchip,pins = 677 <2 RK_PA1 1 &pcfg_pull_up>, 678 <2 RK_PA0 1 &pcfg_pull_none>; 679 }; 680 681 uart0_cts: uart0-cts { 682 rockchip,pins = 683 <2 RK_PA2 1 &pcfg_pull_none>; 684 }; 685 686 uart0_rts: uart0-rts { 687 rockchip,pins = 688 <2 RK_PA3 1 &pcfg_pull_none>; 689 }; 690 }; 691 692 uart1 { 693 uart1_xfer: uart1-xfer { 694 rockchip,pins = 695 <1 RK_PD1 1 &pcfg_pull_up>, 696 <1 RK_PD0 1 &pcfg_pull_none>; 697 }; 698 699 uart1_cts: uart1-cts { 700 rockchip,pins = 701 <1 RK_PC6 1 &pcfg_pull_none>; 702 }; 703 704 uart1_rts: uart1-rts { 705 rockchip,pins = 706 <1 RK_PC7 1 &pcfg_pull_none>; 707 }; 708 }; 709 710 uart2-m0 { 711 uart2m0_xfer: uart2m0-xfer { 712 rockchip,pins = 713 <1 RK_PC7 2 &pcfg_pull_up>, 714 <1 RK_PC6 2 &pcfg_pull_none>; 715 }; 716 }; 717 718 uart2-m1 { 719 uart2m1_xfer: uart2m1-xfer { 720 rockchip,pins = 721 <4 RK_PD3 2 &pcfg_pull_up>, 722 <4 RK_PD2 2 &pcfg_pull_none>; 723 }; 724 }; 725 726 uart3 { 727 uart3_xfer: uart3-xfer { 728 rockchip,pins = 729 <3 RK_PB5 4 &pcfg_pull_up>, 730 <3 RK_PB4 4 &pcfg_pull_none>; 731 }; 732 }; 733 734 uart4 { 735 736 uart4_xfer: uart4-xfer { 737 rockchip,pins = 738 <4 RK_PB1 1 &pcfg_pull_up>, 739 <4 RK_PB0 1 &pcfg_pull_none>; 740 }; 741 742 uart4_cts: uart4-cts { 743 rockchip,pins = 744 <4 RK_PA6 1 &pcfg_pull_none>; 745 746 }; 747 748 uart4_rts: uart4-rts { 749 rockchip,pins = 750 <4 RK_PA7 1 &pcfg_pull_none>; 751 }; 752 }; 753 754 spi0 { 755 spi0_clk: spi0-clk { 756 rockchip,pins = 757 <2 RK_PA2 2 &pcfg_pull_up>; 758 }; 759 760 spi0_csn0: spi0-csn0 { 761 rockchip,pins = 762 <2 RK_PA3 2 &pcfg_pull_up>; 763 }; 764 765 spi0_miso: spi0-miso { 766 rockchip,pins = 767 <2 RK_PA0 2 &pcfg_pull_up>; 768 }; 769 770 spi0_mosi: spi0-mosi { 771 rockchip,pins = 772 <2 RK_PA1 2 &pcfg_pull_up>; 773 }; 774 }; 775 776 spi1 { 777 spi1_clk: spi1-clk { 778 rockchip,pins = 779 <3 RK_PB3 3 &pcfg_pull_up>; 780 }; 781 782 spi1_csn0: spi1-csn0 { 783 rockchip,pins = 784 <3 RK_PB5 3 &pcfg_pull_up>; 785 }; 786 787 spi1_miso: spi1-miso { 788 rockchip,pins = 789 <3 RK_PB2 3 &pcfg_pull_up>; 790 }; 791 792 spi1_mosi: spi1-mosi { 793 rockchip,pins = 794 <3 RK_PB4 3 &pcfg_pull_up>; 795 }; 796 }; 797 798 spi2 { 799 spi2_clk: spi2-clk { 800 rockchip,pins = 801 <1 RK_PD0 3 &pcfg_pull_up>; 802 }; 803 804 spi2_csn0: spi2-csn0 { 805 rockchip,pins = 806 <1 RK_PD1 3 &pcfg_pull_up>; 807 }; 808 809 spi2_miso: spi2-miso { 810 rockchip,pins = 811 <1 RK_PC6 3 &pcfg_pull_up>; 812 }; 813 814 spi2_mosi: spi2-mosi { 815 rockchip,pins = 816 <1 RK_PC7 3 &pcfg_pull_up>; 817 }; 818 }; 819 820 sdmmc { 821 sdmmc_clk: sdmmc-clk { 822 rockchip,pins = 823 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 824 }; 825 826 sdmmc_cmd: sdmmc-cmd { 827 rockchip,pins = 828 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 829 }; 830 831 sdmmc_pwren: sdmmc-pwren { 832 rockchip,pins = 833 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 834 }; 835 836 sdmmc_bus1: sdmmc-bus1 { 837 rockchip,pins = 838 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 839 }; 840 841 sdmmc_bus4: sdmmc-bus4 { 842 rockchip,pins = 843 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 844 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 845 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 846 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 847 }; 848 849 sdmmc_gpio: sdmmc-gpio { 850 rockchip,pins = 851 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 852 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 853 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 854 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 855 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 856 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 857 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 858 }; 859 }; 860 861 sdio { 862 sdio_clk: sdio-clk { 863 rockchip,pins = 864 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 865 }; 866 867 sdio_cmd: sdio-cmd { 868 rockchip,pins = 869 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 870 }; 871 872 sdio_pwren: sdio-pwren { 873 rockchip,pins = 874 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 875 }; 876 877 sdio_wrpt: sdio-wrpt { 878 rockchip,pins = 879 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 880 }; 881 882 sdio_intn: sdio-intn { 883 rockchip,pins = 884 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 885 }; 886 887 sdio_bus1: sdio-bus1 { 888 rockchip,pins = 889 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 890 }; 891 892 sdio_bus4: sdio-bus4 { 893 rockchip,pins = 894 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 895 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 896 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 897 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 898 }; 899 900 sdio_gpio: sdio-gpio { 901 rockchip,pins = 902 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 903 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 904 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 905 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 906 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 907 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 908 }; 909 }; 910 911 emmc { 912 emmc_clk: emmc-clk { 913 rockchip,pins = 914 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 915 }; 916 917 emmc_cmd: emmc-cmd { 918 rockchip,pins = 919 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 920 }; 921 922 emmc_pwren: emmc-pwren { 923 rockchip,pins = 924 <3 RK_PB3 2 &pcfg_pull_none>; 925 }; 926 927 emmc_rstn: emmc-rstn { 928 rockchip,pins = 929 <3 RK_PB2 2 &pcfg_pull_none>; 930 }; 931 932 emmc_bus1: emmc-bus1 { 933 rockchip,pins = 934 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 935 }; 936 937 emmc_bus4: emmc-bus4 { 938 rockchip,pins = 939 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 940 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 941 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 942 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 943 }; 944 945 emmc_bus8: emmc-bus8 { 946 rockchip,pins = 947 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 948 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 949 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 950 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 951 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 952 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 953 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 954 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 955 }; 956 }; 957 958 flash { 959 flash_csn0: flash-csn0 { 960 rockchip,pins = 961 <3 RK_PB5 1 &pcfg_pull_none>; 962 }; 963 964 flash_rdy: flash-rdy { 965 rockchip,pins = 966 <3 RK_PB4 1 &pcfg_pull_none>; 967 }; 968 969 flash_ale: flash-ale { 970 rockchip,pins = 971 <3 RK_PB3 1 &pcfg_pull_none>; 972 }; 973 974 flash_cle: flash-cle { 975 rockchip,pins = 976 <3 RK_PB1 1 &pcfg_pull_none>; 977 }; 978 979 flash_wrn: flash-wrn { 980 rockchip,pins = 981 <3 RK_PB0 1 &pcfg_pull_none>; 982 }; 983 984 flash_rdn: flash-rdn { 985 rockchip,pins = 986 <3 RK_PB2 1 &pcfg_pull_none>; 987 }; 988 989 flash_bus8: flash-bus8 { 990 rockchip,pins = 991 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 992 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 993 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 994 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 995 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 996 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 997 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 998 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 999 }; 1000 }; 1001 1002 pwm0 { 1003 pwm0_pin: pwm0-pin { 1004 rockchip,pins = 1005 <0 RK_PB5 1 &pcfg_pull_none>; 1006 }; 1007 }; 1008 1009 pwm1 { 1010 pwm1_pin: pwm1-pin { 1011 rockchip,pins = 1012 <0 RK_PB6 1 &pcfg_pull_none>; 1013 }; 1014 }; 1015 1016 pwm2 { 1017 pwm2_pin: pwm2-pin { 1018 rockchip,pins = 1019 <0 RK_PB7 1 &pcfg_pull_none>; 1020 }; 1021 }; 1022 1023 pwm3 { 1024 pwm3_pin: pwm3-pin { 1025 rockchip,pins = 1026 <0 RK_PC0 1 &pcfg_pull_none>; 1027 }; 1028 }; 1029 1030 gmac { 1031 rmii_pins: rmii-pins { 1032 rockchip,pins = 1033 /* mac_txen */ 1034 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1035 /* mac_txd1 */ 1036 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1037 /* mac_txd0 */ 1038 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1039 /* mac_rxd0 */ 1040 <1 RK_PC4 3 &pcfg_pull_none>, 1041 /* mac_rxd1 */ 1042 <1 RK_PC5 3 &pcfg_pull_none>, 1043 /* mac_rxer */ 1044 <1 RK_PB7 3 &pcfg_pull_none>, 1045 /* mac_rxdv */ 1046 <1 RK_PC0 3 &pcfg_pull_none>, 1047 /* mac_mdio */ 1048 <1 RK_PB6 3 &pcfg_pull_none>, 1049 /* mac_mdc */ 1050 <1 RK_PB5 3 &pcfg_pull_none>, 1051 /* mac_clk */ 1052 <1 RK_PB4 3 &pcfg_pull_none>; 1053 }; 1054 }; 1055 1056 lcdc { 1057 lcdc_ctl: lcdc-ctl { 1058 rockchip,pins = 1059 /* dclk */ 1060 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1061 /* hsync */ 1062 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1063 /* vsync */ 1064 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1065 /* den */ 1066 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1067 /* d0 */ 1068 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1069 /* d1 */ 1070 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1071 /* d2 */ 1072 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1073 /* d3 */ 1074 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1075 /* d4 */ 1076 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1077 /* d5 */ 1078 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1079 /* d6 */ 1080 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1081 /* d7 */ 1082 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1083 /* d8 */ 1084 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1085 /* d9 */ 1086 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1087 /* d10 */ 1088 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1089 /* d11 */ 1090 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1091 /* d12 */ 1092 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1093 /* d13 */ 1094 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1095 /* d14 */ 1096 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1097 /* d15 */ 1098 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1099 /* d16 */ 1100 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1101 /* d17 */ 1102 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1103 }; 1104 }; 1105 }; 1106}; 1107
