1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a35", "arm,armv8"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a35", "arm,armv8"; 42 reg = <0x0 0x1>; 43 enable-method = "psci"; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a35", "arm,armv8"; 49 reg = <0x0 0x2>; 50 enable-method = "psci"; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35", "arm,armv8"; 56 reg = <0x0 0x3>; 57 enable-method = "psci"; 58 }; 59 }; 60 61 arm-pmu { 62 compatible = "arm,cortex-a53-pmu"; 63 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 68 }; 69 70 mac_clkin: external-mac-clock { 71 compatible = "fixed-clock"; 72 clock-frequency = <50000000>; 73 clock-output-names = "mac_clkin"; 74 #clock-cells = <0>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vop_out>; 80 status = "disabled"; 81 82 route { 83 route_rgb: route-rgb { 84 status = "okay"; 85 logo,uboot = "logo.bmp"; 86 logo,kernel = "logo_kernel.bmp"; 87 logo,mode = "center"; 88 charge_logo,mode = "center"; 89 connect = <&vop_out_rgb>; 90 }; 91 }; 92 }; 93 94 dmc: dmc@20004000 { 95 compatible = "rockchip,rk3308-dmc"; 96 reg = <0x0 0xff010000 0x0 0x10000>; 97 }; 98 99 psci { 100 compatible = "arm,psci-1.0"; 101 method = "smc"; 102 }; 103 104 timer { 105 compatible = "arm,armv8-timer"; 106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 clock-frequency = <24000000>; 111 }; 112 113 clocks { 114 xin24m: xin24m { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <24000000>; 118 clock-output-names = "xin24m"; 119 }; 120 }; 121 122 grf: grf@ff000000 { 123 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 124 reg = <0x0 0xff000000 0x0 0x10000>; 125 }; 126 127 usb2phy_grf: syscon@ff008000 { 128 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 129 "simple-mfd"; 130 reg = <0x0 0xff008000 0x0 0x4000>; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 134 u2phy: usb2-phy@100 { 135 compatible = "rockchip,rk3308-usb2phy", 136 "rockchip,rk3328-usb2phy"; 137 reg = <0x100 0x10>; 138 clocks = <&cru SCLK_USBPHY_REF>; 139 clock-names = "phyclk"; 140 #clock-cells = <0>; 141 assigned-clocks = <&cru USB480M>; 142 assigned-clock-parents = <&u2phy>; 143 clock-output-names = "usb480m_phy"; 144 status = "disabled"; 145 146 u2phy_host: host-port { 147 #phy-cells = <0>; 148 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 149 interrupt-names = "linestate"; 150 status = "disabled"; 151 }; 152 153 u2phy_otg: otg-port { 154 #phy-cells = <0>; 155 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "otg-bvalid", "otg-id", 159 "linestate"; 160 status = "disabled"; 161 }; 162 }; 163 }; 164 165 uart0: serial@ff0a0000 { 166 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 167 reg = <0x0 0xff0a0000 0x0 0x100>; 168 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 170 clock-names = "baudclk", "apb_pclk"; 171 reg-shift = <2>; 172 reg-io-width = <4>; 173 status = "disabled"; 174 }; 175 176 uart1: serial@ff0b0000 { 177 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 178 reg = <0x0 0xff0b0000 0x0 0x100>; 179 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 181 clock-names = "baudclk", "apb_pclk"; 182 reg-shift = <2>; 183 reg-io-width = <4>; 184 status = "disabled"; 185 }; 186 187 uart2: serial@ff0c0000 { 188 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 189 reg = <0x0 0xff0c0000 0x0 0x100>; 190 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 192 clock-names = "baudclk", "apb_pclk"; 193 reg-shift = <2>; 194 reg-io-width = <4>; 195 status = "disabled"; 196 }; 197 198 uart3: serial@ff0d0000 { 199 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 200 reg = <0x0 0xff0d0000 0x0 0x100>; 201 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 203 clock-names = "baudclk", "apb_pclk"; 204 reg-shift = <2>; 205 reg-io-width = <4>; 206 status = "disabled"; 207 }; 208 209 uart4: serial@ff0e0000 { 210 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 211 reg = <0x0 0xff0e0000 0x0 0x100>; 212 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 214 clock-names = "baudclk", "apb_pclk"; 215 reg-shift = <2>; 216 reg-io-width = <4>; 217 status = "disabled"; 218 }; 219 220 vop: vop@ff2e0000 { 221 compatible = "rockchip,rk3308-vop"; 222 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 223 reg-names = "regs", "gamma_lut"; 224 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 226 <&cru HCLK_VOP>; 227 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 228 status = "disabled"; 229 230 vop_out: port { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 234 vop_out_rgb: endpoint@0 { 235 reg = <0>; 236 remote-endpoint = <&rgb_in_vop>; 237 }; 238 }; 239 }; 240 241 pwm0: pwm@ff180000 { 242 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 243 reg = <0x0 0xff180000 0x0 0x10>; 244 #pwm-cells = <3>; 245 pinctrl-names = "active"; 246 pinctrl-0 = <&pwm0_pin>; 247 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 248 clock-names = "pwm", "pclk"; 249 status = "disabled"; 250 }; 251 252 pwm1: pwm@ff180010 { 253 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 254 reg = <0x0 0xff180010 0x0 0x10>; 255 #pwm-cells = <3>; 256 pinctrl-names = "active"; 257 pinctrl-0 = <&pwm1_pin>; 258 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 259 clock-names = "pwm", "pclk"; 260 status = "disabled"; 261 }; 262 263 pwm2: pwm@ff180020 { 264 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 265 reg = <0x0 0xff180020 0x0 0x10>; 266 #pwm-cells = <3>; 267 pinctrl-names = "active"; 268 pinctrl-0 = <&pwm2_pin>; 269 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 270 clock-names = "pwm", "pclk"; 271 status = "disabled"; 272 }; 273 274 pwm3: pwm@ff180030 { 275 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 276 reg = <0x0 0xff180030 0x0 0x10>; 277 #pwm-cells = <3>; 278 pinctrl-names = "active"; 279 pinctrl-0 = <&pwm3_pin>; 280 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 281 clock-names = "pwm", "pclk"; 282 status = "disabled"; 283 }; 284 285 rgb: rgb { 286 compatible = "rockchip,rk3308-rgb"; 287 status = "disabled"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&lcdc_ctl>; 290 291 ports { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 port@0 { 296 reg = <0>; 297 298 #address-cells = <1>; 299 #size-cells = <0>; 300 301 rgb_in_vop: endpoint@0 { 302 reg = <0>; 303 remote-endpoint = <&vop_out_rgb>; 304 }; 305 }; 306 307 }; 308 }; 309 310 saradc: saradc@ff1e0000 { 311 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 312 reg = <0x0 0xff1e0000 0x0 0x100>; 313 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 314 #io-channel-cells = <1>; 315 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 316 clock-names = "saradc", "apb_pclk"; 317 resets = <&cru SRST_SARADC_P>; 318 reset-names = "saradc-apb"; 319 status = "disabled"; 320 }; 321 322 i2s0: i2s@ff300000 { 323 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 324 reg = <0x0 0xff300000 0x0 0x10000>; 325 }; 326 327 i2s1: i2s@ff310000 { 328 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 329 reg = <0x0 0xff100000 0x0 0x10000>; 330 }; 331 332 i2s2: i2s@ff320000 { 333 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 334 reg = <0x0 0xff320000 0x0 0x10000>; 335 }; 336 337 i2s3: i2s@ff330000 { 338 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 339 reg = <0x0 0xff330000 0x0 0x10000>; 340 }; 341 342 vad: vad@ff3c0000 { 343 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 344 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 345 reg-names = "vad", "vad-memory"; 346 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 347 rockchip,audio-src = <0>; 348 rockchip,audio-chnl-num = <8>; 349 rockchip,audio-chnl = <0>; 350 rockchip,mode = <0>; 351 }; 352 353 usb20_otg: usb@ff400000 { 354 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 355 "snps,dwc2"; 356 reg = <0x0 0xff400000 0x0 0x40000>; 357 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cru HCLK_OTG>; 359 clock-names = "otg"; 360 dr_mode = "otg"; 361 g-np-tx-fifo-size = <16>; 362 g-rx-fifo-size = <275>; 363 g-tx-fifo-size = <256 128 128 64 64 32>; 364 g-use-dma; 365 phys = <&u2phy_otg>; 366 phy-names = "usb2-phy"; 367 status = "disabled"; 368 }; 369 370 usb_host0_ehci: usb@ff440000 { 371 compatible = "generic-ehci"; 372 reg = <0x0 0xff440000 0x0 0x10000>; 373 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 375 <&u2phy>; 376 clock-names = "usbhost", "arbiter", "utmi"; 377 phys = <&u2phy_host>; 378 phy-names = "usb"; 379 status = "disabled"; 380 }; 381 382 usb_host0_ohci: usb@ff450000 { 383 compatible = "generic-ohci"; 384 reg = <0x0 0xff450000 0x0 0x10000>; 385 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 387 <&u2phy>; 388 clock-names = "usbhost", "arbiter", "utmi"; 389 phys = <&u2phy_host>; 390 phy-names = "usb"; 391 }; 392 393 sdmmc: dwmmc@ff480000 { 394 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 395 reg = <0x0 0xff480000 0x0 0x4000>; 396 max-frequency = <150000000>; 397 bus-width = <4>; 398 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 399 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 400 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 401 fifo-depth = <0x100>; 402 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 405 status = "disabled"; 406 }; 407 408 emmc: dwmmc@ff490000 { 409 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 410 reg = <0x0 0xff490000 0x0 0x4000>; 411 max-frequency = <150000000>; 412 bus-width = <8>; 413 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 414 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 415 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 416 fifo-depth = <0x100>; 417 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 418 status = "disabled"; 419 }; 420 421 sdio: dwmmc@ff4a0000 { 422 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 423 reg = <0x0 0xff4a0000 0x0 0x4000>; 424 max-frequency = <150000000>; 425 bus-width = <4>; 426 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 427 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 428 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 429 fifo-depth = <0x100>; 430 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 433 status = "disabled"; 434 }; 435 436 nandc: nandc@ff4b0000 { 437 compatible = "rockchip,rk-nandc"; 438 reg = <0x0 0xff4b0000 0x0 0x4000>; 439 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 440 nandc_id = <0>; 441 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 442 clock-names = "clk_nandc", "hclk_nandc"; 443 status = "disabled"; 444 }; 445 446 447 sfc: sfc@ff4c0000 { 448 compatible = "rockchip,rksfc"; 449 reg = <0x0 0xff4c0000 0x0 0x4000>; 450 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 452 clock-names = "clk_sfc", "hclk_sfc"; 453 status = "disabled"; 454 }; 455 456 mac: ethernet@ff4e0000 { 457 compatible = "rockchip,rk3308-mac"; 458 reg = <0x0 0xff4e0000 0x0 0x10000>; 459 rockchip,grf = <&grf>; 460 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "macirq"; 462 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 463 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 464 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 465 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 466 clock-names = "stmmaceth", "mac_clk_rx", 467 "mac_clk_tx", "clk_mac_ref", 468 "clk_mac_refout", "aclk_mac", 469 "pclk_mac", "clk_mac_speed"; 470 phy-mode = "rmii"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 473 resets = <&cru SRST_MAC_A>; 474 reset-names = "stmmaceth"; 475 status = "disabled"; 476 }; 477 478 cru: clock-controller@ff500000 { 479 compatible = "rockchip,rk3308-cru"; 480 reg = <0x0 0xff500000 0x0 0x1000>; 481 rockchip,grf = <&grf>; 482 #clock-cells = <1>; 483 #reset-cells = <1>; 484 }; 485 486 gic: interrupt-controller@ff580000 { 487 compatible = "arm,gic-400"; 488 #interrupt-cells = <3>; 489 #address-cells = <0>; 490 interrupt-controller; 491 492 reg = <0x0 0xff581000 0x0 0x1000>, 493 <0x0 0xff582000 0x0 0x2000>, 494 <0x0 0xff584000 0x0 0x2000>, 495 <0x0 0xff586000 0x0 0x2000>; 496 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 497 }; 498 499 pinctrl: pinctrl { 500 compatible = "rockchip,rk3308-pinctrl"; 501 rockchip,grf = <&grf>; 502 #address-cells = <2>; 503 #size-cells = <2>; 504 ranges; 505 506 gpio0: gpio0@ff220000 { 507 compatible = "rockchip,gpio-bank"; 508 reg = <0x0 0xff220000 0x0 0x100>; 509 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 510 //clocks = <&cru PCLK_GPIO0>; 511 clocks = <&xin24m>; 512 gpio-controller; 513 #gpio-cells = <2>; 514 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 }; 518 519 gpio1: gpio1@ff230000 { 520 compatible = "rockchip,gpio-bank"; 521 reg = <0x0 0xff230000 0x0 0x100>; 522 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 523 //clocks = <&cru PCLK_GPIO1>; 524 clocks = <&xin24m>; 525 gpio-controller; 526 #gpio-cells = <2>; 527 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 }; 531 532 gpio2: gpio2@ff240000 { 533 compatible = "rockchip,gpio-bank"; 534 reg = <0x0 0xff240000 0x0 0x100>; 535 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 536 //clocks = <&cru PCLK_GPIO2>; 537 clocks = <&xin24m>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 }; 544 545 gpio3: gpio3@ff250000 { 546 compatible = "rockchip,gpio-bank"; 547 reg = <0x0 0xff250000 0x0 0x100>; 548 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 549 //clocks = <&cru PCLK_GPIO3>; 550 clocks = <&xin24m>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 }; 557 558 gpio4: gpio4@ff260000 { 559 compatible = "rockchip,gpio-bank"; 560 reg = <0x0 0xff260000 0x0 0x100>; 561 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 562 //clocks = <&cru PCLK_GPIO4>; 563 clocks = <&xin24m>; 564 gpio-controller; 565 #gpio-cells = <2>; 566 567 interrupt-controller; 568 #interrupt-cells = <2>; 569 }; 570 571 pcfg_pull_up: pcfg-pull-up { 572 bias-pull-up; 573 }; 574 575 pcfg_pull_down: pcfg-pull-down { 576 bias-pull-down; 577 }; 578 579 pcfg_pull_none: pcfg-pull-none { 580 bias-disable; 581 }; 582 583 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 584 bias-disable; 585 drive-strength = <2>; 586 }; 587 588 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 589 bias-pull-up; 590 drive-strength = <2>; 591 }; 592 593 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 594 bias-pull-up; 595 drive-strength = <4>; 596 }; 597 598 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 599 bias-disable; 600 drive-strength = <4>; 601 }; 602 603 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 604 bias-pull-down; 605 drive-strength = <4>; 606 }; 607 608 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 609 bias-disable; 610 drive-strength = <8>; 611 }; 612 613 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 614 bias-pull-up; 615 drive-strength = <8>; 616 }; 617 618 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 619 bias-disable; 620 drive-strength = <12>; 621 }; 622 623 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 624 bias-pull-up; 625 drive-strength = <12>; 626 }; 627 628 pcfg_pull_none_smt: pcfg-pull-none-smt { 629 bias-disable; 630 input-schmitt-enable; 631 }; 632 633 pcfg_output_high: pcfg-output-high { 634 output-high; 635 }; 636 637 pcfg_output_low: pcfg-output-low { 638 output-low; 639 }; 640 641 pcfg_input_high: pcfg-input-high { 642 bias-pull-up; 643 input-enable; 644 }; 645 646 pcfg_input: pcfg-input { 647 input-enable; 648 }; 649 650 i2c0 { 651 i2c0_xfer: i2c0-xfer { 652 rockchip,pins = 653 <1 RK_PD0 2 &pcfg_pull_none_smt>, 654 <1 RK_PD1 2 &pcfg_pull_none_smt>; 655 }; 656 }; 657 658 i2c1 { 659 i2c1_xfer: i2c1-xfer { 660 rockchip,pins = 661 <0 RK_PB3 1 &pcfg_pull_none_smt>, 662 <0 RK_PB4 1 &pcfg_pull_none_smt>; 663 }; 664 }; 665 666 i2c2 { 667 i2c2_xfer: i2c2-xfer { 668 rockchip,pins = 669 <2 RK_PA2 3 &pcfg_pull_none_smt>, 670 <2 RK_PA3 3 &pcfg_pull_none_smt>; 671 }; 672 }; 673 674 i2c3-m0 { 675 i2c3m0_xfer: i2c3m0-xfer { 676 rockchip,pins = 677 <0 RK_PB7 2 &pcfg_pull_none_smt>, 678 <0 RK_PC0 2 &pcfg_pull_none_smt>; 679 }; 680 }; 681 682 i2c3-m1 { 683 i2c3m1_xfer: i2c3m1-xfer { 684 rockchip,pins = 685 <3 RK_PB4 2 &pcfg_pull_none_smt>, 686 <3 RK_PB5 2 &pcfg_pull_none_smt>; 687 }; 688 }; 689 690 tsadc { 691 tsadc_otp_gpio: tsadc-otp-gpio { 692 rockchip,pins = 693 <0 RK_PB2 0 &pcfg_pull_none>; 694 }; 695 696 tsadc_otp_out: tsadc-otp-out { 697 rockchip,pins = 698 <0 RK_PB2 1 &pcfg_pull_none>; 699 }; 700 }; 701 702 uart0 { 703 uart0_xfer: uart0-xfer { 704 rockchip,pins = 705 <2 RK_PA1 1 &pcfg_pull_up>, 706 <2 RK_PA0 1 &pcfg_pull_none>; 707 }; 708 709 uart0_cts: uart0-cts { 710 rockchip,pins = 711 <2 RK_PA2 1 &pcfg_pull_none>; 712 }; 713 714 uart0_rts: uart0-rts { 715 rockchip,pins = 716 <2 RK_PA3 1 &pcfg_pull_none>; 717 }; 718 }; 719 720 uart1 { 721 uart1_xfer: uart1-xfer { 722 rockchip,pins = 723 <1 RK_PD1 1 &pcfg_pull_up>, 724 <1 RK_PD0 1 &pcfg_pull_none>; 725 }; 726 727 uart1_cts: uart1-cts { 728 rockchip,pins = 729 <1 RK_PC6 1 &pcfg_pull_none>; 730 }; 731 732 uart1_rts: uart1-rts { 733 rockchip,pins = 734 <1 RK_PC7 1 &pcfg_pull_none>; 735 }; 736 }; 737 738 uart2-m0 { 739 uart2m0_xfer: uart2m0-xfer { 740 rockchip,pins = 741 <1 RK_PC7 2 &pcfg_pull_up>, 742 <1 RK_PC6 2 &pcfg_pull_none>; 743 }; 744 }; 745 746 uart2-m1 { 747 uart2m1_xfer: uart2m1-xfer { 748 rockchip,pins = 749 <4 RK_PD3 2 &pcfg_pull_up>, 750 <4 RK_PD2 2 &pcfg_pull_none>; 751 }; 752 }; 753 754 uart3 { 755 uart3_xfer: uart3-xfer { 756 rockchip,pins = 757 <3 RK_PB5 4 &pcfg_pull_up>, 758 <3 RK_PB4 4 &pcfg_pull_none>; 759 }; 760 }; 761 762 uart4 { 763 764 uart4_xfer: uart4-xfer { 765 rockchip,pins = 766 <4 RK_PB1 1 &pcfg_pull_up>, 767 <4 RK_PB0 1 &pcfg_pull_none>; 768 }; 769 770 uart4_cts: uart4-cts { 771 rockchip,pins = 772 <4 RK_PA6 1 &pcfg_pull_none>; 773 774 }; 775 776 uart4_rts: uart4-rts { 777 rockchip,pins = 778 <4 RK_PA7 1 &pcfg_pull_none>; 779 }; 780 }; 781 782 spi0 { 783 spi0_clk: spi0-clk { 784 rockchip,pins = 785 <2 RK_PA2 2 &pcfg_pull_up>; 786 }; 787 788 spi0_csn0: spi0-csn0 { 789 rockchip,pins = 790 <2 RK_PA3 2 &pcfg_pull_up>; 791 }; 792 793 spi0_miso: spi0-miso { 794 rockchip,pins = 795 <2 RK_PA0 2 &pcfg_pull_up>; 796 }; 797 798 spi0_mosi: spi0-mosi { 799 rockchip,pins = 800 <2 RK_PA1 2 &pcfg_pull_up>; 801 }; 802 }; 803 804 spi1 { 805 spi1_clk: spi1-clk { 806 rockchip,pins = 807 <3 RK_PB3 3 &pcfg_pull_up>; 808 }; 809 810 spi1_csn0: spi1-csn0 { 811 rockchip,pins = 812 <3 RK_PB5 3 &pcfg_pull_up>; 813 }; 814 815 spi1_miso: spi1-miso { 816 rockchip,pins = 817 <3 RK_PB2 3 &pcfg_pull_up>; 818 }; 819 820 spi1_mosi: spi1-mosi { 821 rockchip,pins = 822 <3 RK_PB4 3 &pcfg_pull_up>; 823 }; 824 }; 825 826 spi2 { 827 spi2_clk: spi2-clk { 828 rockchip,pins = 829 <1 RK_PD0 3 &pcfg_pull_up>; 830 }; 831 832 spi2_csn0: spi2-csn0 { 833 rockchip,pins = 834 <1 RK_PD1 3 &pcfg_pull_up>; 835 }; 836 837 spi2_miso: spi2-miso { 838 rockchip,pins = 839 <1 RK_PC6 3 &pcfg_pull_up>; 840 }; 841 842 spi2_mosi: spi2-mosi { 843 rockchip,pins = 844 <1 RK_PC7 3 &pcfg_pull_up>; 845 }; 846 }; 847 848 sdmmc { 849 sdmmc_clk: sdmmc-clk { 850 rockchip,pins = 851 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 852 }; 853 854 sdmmc_cmd: sdmmc-cmd { 855 rockchip,pins = 856 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 857 }; 858 859 sdmmc_pwren: sdmmc-pwren { 860 rockchip,pins = 861 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 862 }; 863 864 sdmmc_bus1: sdmmc-bus1 { 865 rockchip,pins = 866 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 867 }; 868 869 sdmmc_bus4: sdmmc-bus4 { 870 rockchip,pins = 871 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 872 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 873 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 874 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 875 }; 876 877 sdmmc_gpio: sdmmc-gpio { 878 rockchip,pins = 879 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 880 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 881 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 882 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 883 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 884 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 885 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 886 }; 887 }; 888 889 sdio { 890 sdio_clk: sdio-clk { 891 rockchip,pins = 892 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 893 }; 894 895 sdio_cmd: sdio-cmd { 896 rockchip,pins = 897 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 898 }; 899 900 sdio_pwren: sdio-pwren { 901 rockchip,pins = 902 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 903 }; 904 905 sdio_wrpt: sdio-wrpt { 906 rockchip,pins = 907 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 908 }; 909 910 sdio_intn: sdio-intn { 911 rockchip,pins = 912 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 913 }; 914 915 sdio_bus1: sdio-bus1 { 916 rockchip,pins = 917 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 918 }; 919 920 sdio_bus4: sdio-bus4 { 921 rockchip,pins = 922 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 923 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 924 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 925 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 926 }; 927 928 sdio_gpio: sdio-gpio { 929 rockchip,pins = 930 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 931 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 932 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 933 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 934 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 935 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 936 }; 937 }; 938 939 emmc { 940 emmc_clk: emmc-clk { 941 rockchip,pins = 942 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 943 }; 944 945 emmc_cmd: emmc-cmd { 946 rockchip,pins = 947 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 948 }; 949 950 emmc_pwren: emmc-pwren { 951 rockchip,pins = 952 <3 RK_PB3 2 &pcfg_pull_none>; 953 }; 954 955 emmc_rstn: emmc-rstn { 956 rockchip,pins = 957 <3 RK_PB2 2 &pcfg_pull_none>; 958 }; 959 960 emmc_bus1: emmc-bus1 { 961 rockchip,pins = 962 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 963 }; 964 965 emmc_bus4: emmc-bus4 { 966 rockchip,pins = 967 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 968 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 969 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 970 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 971 }; 972 973 emmc_bus8: emmc-bus8 { 974 rockchip,pins = 975 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 976 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 977 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 978 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 979 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 980 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 981 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 982 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 983 }; 984 }; 985 986 flash { 987 flash_csn0: flash-csn0 { 988 rockchip,pins = 989 <3 RK_PB5 1 &pcfg_pull_none>; 990 }; 991 992 flash_rdy: flash-rdy { 993 rockchip,pins = 994 <3 RK_PB4 1 &pcfg_pull_none>; 995 }; 996 997 flash_ale: flash-ale { 998 rockchip,pins = 999 <3 RK_PB3 1 &pcfg_pull_none>; 1000 }; 1001 1002 flash_cle: flash-cle { 1003 rockchip,pins = 1004 <3 RK_PB1 1 &pcfg_pull_none>; 1005 }; 1006 1007 flash_wrn: flash-wrn { 1008 rockchip,pins = 1009 <3 RK_PB0 1 &pcfg_pull_none>; 1010 }; 1011 1012 flash_rdn: flash-rdn { 1013 rockchip,pins = 1014 <3 RK_PB2 1 &pcfg_pull_none>; 1015 }; 1016 1017 flash_bus8: flash-bus8 { 1018 rockchip,pins = 1019 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1020 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1021 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1022 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1023 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1024 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1025 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1026 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1027 }; 1028 }; 1029 1030 pwm0 { 1031 pwm0_pin: pwm0-pin { 1032 rockchip,pins = 1033 <0 RK_PB5 1 &pcfg_pull_none>; 1034 }; 1035 }; 1036 1037 pwm1 { 1038 pwm1_pin: pwm1-pin { 1039 rockchip,pins = 1040 <0 RK_PB6 1 &pcfg_pull_none>; 1041 }; 1042 }; 1043 1044 pwm2 { 1045 pwm2_pin: pwm2-pin { 1046 rockchip,pins = 1047 <0 RK_PB7 1 &pcfg_pull_none>; 1048 }; 1049 }; 1050 1051 pwm3 { 1052 pwm3_pin: pwm3-pin { 1053 rockchip,pins = 1054 <0 RK_PC0 1 &pcfg_pull_none>; 1055 }; 1056 }; 1057 1058 gmac { 1059 rmii_pins: rmii-pins { 1060 rockchip,pins = 1061 /* mac_txen */ 1062 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1063 /* mac_txd1 */ 1064 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1065 /* mac_txd0 */ 1066 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1067 /* mac_rxd0 */ 1068 <1 RK_PC4 3 &pcfg_pull_none>, 1069 /* mac_rxd1 */ 1070 <1 RK_PC5 3 &pcfg_pull_none>, 1071 /* mac_rxer */ 1072 <1 RK_PB7 3 &pcfg_pull_none>, 1073 /* mac_rxdv */ 1074 <1 RK_PC0 3 &pcfg_pull_none>, 1075 /* mac_mdio */ 1076 <1 RK_PB6 3 &pcfg_pull_none>, 1077 /* mac_mdc */ 1078 <1 RK_PB5 3 &pcfg_pull_none>; 1079 }; 1080 1081 mac_refclk_12ma: mac-refclk-12ma { 1082 rockchip,pins = 1083 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1084 }; 1085 1086 mac_refclk: mac-refclk { 1087 rockchip,pins = 1088 <1 RK_PB4 3 &pcfg_pull_none>; 1089 }; 1090 1091 }; 1092 1093 lcdc { 1094 lcdc_ctl: lcdc-ctl { 1095 rockchip,pins = 1096 /* dclk */ 1097 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1098 /* hsync */ 1099 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1100 /* vsync */ 1101 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1102 /* den */ 1103 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1104 /* d0 */ 1105 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1106 /* d1 */ 1107 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1108 /* d2 */ 1109 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1110 /* d3 */ 1111 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1112 /* d4 */ 1113 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1114 /* d5 */ 1115 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1116 /* d6 */ 1117 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1118 /* d7 */ 1119 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1120 /* d8 */ 1121 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1122 /* d9 */ 1123 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1124 /* d10 */ 1125 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1126 /* d11 */ 1127 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1128 /* d12 */ 1129 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1130 /* d13 */ 1131 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1132 /* d14 */ 1133 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1134 /* d15 */ 1135 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1136 /* d16 */ 1137 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1138 /* d17 */ 1139 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1140 }; 1141 }; 1142 }; 1143}; 1144
