1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 mmc0 = &emmc; 27 mmc1 = &sdmmc; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a35", "arm,armv8"; 37 reg = <0x0 0x0>; 38 enable-method = "psci"; 39 }; 40 41 cpu1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35", "arm,armv8"; 44 reg = <0x0 0x1>; 45 enable-method = "psci"; 46 }; 47 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a35", "arm,armv8"; 51 reg = <0x0 0x2>; 52 enable-method = "psci"; 53 }; 54 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 mac_clkin: external-mac-clock { 73 compatible = "fixed-clock"; 74 clock-frequency = <50000000>; 75 clock-output-names = "mac_clkin"; 76 #clock-cells = <0>; 77 }; 78 79 display_subsystem: display-subsystem { 80 compatible = "rockchip,display-subsystem"; 81 ports = <&vop_out>; 82 status = "disabled"; 83 84 route { 85 route_rgb: route-rgb { 86 status = "okay"; 87 logo,uboot = "logo.bmp"; 88 logo,kernel = "logo_kernel.bmp"; 89 logo,mode = "center"; 90 charge_logo,mode = "center"; 91 connect = <&vop_out_rgb>; 92 }; 93 }; 94 }; 95 96 dmc: dmc@20004000 { 97 compatible = "rockchip,rk3308-dmc"; 98 reg = <0x0 0xff010000 0x0 0x10000>; 99 }; 100 101 psci { 102 compatible = "arm,psci-1.0"; 103 method = "smc"; 104 }; 105 106 timer { 107 compatible = "arm,armv8-timer"; 108 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 109 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 110 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 111 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 112 clock-frequency = <24000000>; 113 }; 114 115 clocks { 116 xin24m: xin24m { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <24000000>; 120 clock-output-names = "xin24m"; 121 }; 122 }; 123 124 grf: grf@ff000000 { 125 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 126 reg = <0x0 0xff000000 0x0 0x10000>; 127 }; 128 129 usb2phy_grf: syscon@ff008000 { 130 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 131 "simple-mfd"; 132 reg = <0x0 0xff008000 0x0 0x4000>; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 136 u2phy: usb2-phy@100 { 137 compatible = "rockchip,rk3308-usb2phy", 138 "rockchip,rk3328-usb2phy"; 139 reg = <0x100 0x10>; 140 clocks = <&cru SCLK_USBPHY_REF>; 141 clock-names = "phyclk"; 142 #clock-cells = <0>; 143 assigned-clocks = <&cru USB480M>; 144 assigned-clock-parents = <&u2phy>; 145 clock-output-names = "usb480m_phy"; 146 status = "disabled"; 147 148 u2phy_host: host-port { 149 #phy-cells = <0>; 150 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-names = "linestate"; 152 status = "disabled"; 153 }; 154 155 u2phy_otg: otg-port { 156 #phy-cells = <0>; 157 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-names = "otg-bvalid", "otg-id", 161 "linestate"; 162 status = "disabled"; 163 }; 164 }; 165 }; 166 167 uart0: serial@ff0a0000 { 168 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 169 reg = <0x0 0xff0a0000 0x0 0x100>; 170 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 172 clock-names = "baudclk", "apb_pclk"; 173 reg-shift = <2>; 174 reg-io-width = <4>; 175 status = "disabled"; 176 }; 177 178 uart1: serial@ff0b0000 { 179 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 180 reg = <0x0 0xff0b0000 0x0 0x100>; 181 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 183 clock-names = "baudclk", "apb_pclk"; 184 reg-shift = <2>; 185 reg-io-width = <4>; 186 status = "disabled"; 187 }; 188 189 uart2: serial@ff0c0000 { 190 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 191 reg = <0x0 0xff0c0000 0x0 0x100>; 192 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 194 clock-names = "baudclk", "apb_pclk"; 195 reg-shift = <2>; 196 reg-io-width = <4>; 197 status = "disabled"; 198 }; 199 200 uart3: serial@ff0d0000 { 201 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 202 reg = <0x0 0xff0d0000 0x0 0x100>; 203 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 205 clock-names = "baudclk", "apb_pclk"; 206 reg-shift = <2>; 207 reg-io-width = <4>; 208 status = "disabled"; 209 }; 210 211 uart4: serial@ff0e0000 { 212 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 213 reg = <0x0 0xff0e0000 0x0 0x100>; 214 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 216 clock-names = "baudclk", "apb_pclk"; 217 reg-shift = <2>; 218 reg-io-width = <4>; 219 status = "disabled"; 220 }; 221 222 secure_otp: secure_otp@0xff2a8000 { 223 compatible = "rockchip,rk3308-secure-otp"; 224 reg = <0x0 0xff2a8000 0x0 0x4000>; 225 secure_conf = <0xff2b0004>; 226 mask_addr = <0xff540000>; 227 }; 228 229 vop: vop@ff2e0000 { 230 compatible = "rockchip,rk3308-vop"; 231 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 232 reg-names = "regs", "gamma_lut"; 233 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 235 <&cru HCLK_VOP>; 236 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 237 status = "disabled"; 238 239 vop_out: port { 240 #address-cells = <1>; 241 #size-cells = <0>; 242 243 vop_out_rgb: endpoint@0 { 244 reg = <0>; 245 remote-endpoint = <&rgb_in_vop>; 246 }; 247 }; 248 }; 249 250 crypto: crypto@ff2f0000 { 251 compatible = "rockchip,rk3308-crypto"; 252 reg = <0x0 0xff2f0000 0x0 0x4000>; 253 clock-names = "sclk_crypto", "apkclk_crypto"; 254 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 255 clock-frequency = <200000000>, <300000000>; 256 status = "disabled"; 257 }; 258 259 pwm0: pwm@ff180000 { 260 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 261 reg = <0x0 0xff180000 0x0 0x10>; 262 #pwm-cells = <3>; 263 pinctrl-names = "active"; 264 pinctrl-0 = <&pwm0_pin>; 265 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 266 clock-names = "pwm", "pclk"; 267 status = "disabled"; 268 }; 269 270 pwm1: pwm@ff180010 { 271 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 272 reg = <0x0 0xff180010 0x0 0x10>; 273 #pwm-cells = <3>; 274 pinctrl-names = "active"; 275 pinctrl-0 = <&pwm1_pin>; 276 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 277 clock-names = "pwm", "pclk"; 278 status = "disabled"; 279 }; 280 281 pwm2: pwm@ff180020 { 282 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 283 reg = <0x0 0xff180020 0x0 0x10>; 284 #pwm-cells = <3>; 285 pinctrl-names = "active"; 286 pinctrl-0 = <&pwm2_pin>; 287 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 288 clock-names = "pwm", "pclk"; 289 status = "disabled"; 290 }; 291 292 pwm3: pwm@ff180030 { 293 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 294 reg = <0x0 0xff180030 0x0 0x10>; 295 #pwm-cells = <3>; 296 pinctrl-names = "active"; 297 pinctrl-0 = <&pwm3_pin>; 298 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 299 clock-names = "pwm", "pclk"; 300 status = "disabled"; 301 }; 302 303 rgb: rgb { 304 compatible = "rockchip,rk3308-rgb"; 305 status = "disabled"; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&lcdc_ctl>; 308 309 ports { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 313 port@0 { 314 reg = <0>; 315 316 #address-cells = <1>; 317 #size-cells = <0>; 318 319 rgb_in_vop: endpoint@0 { 320 reg = <0>; 321 remote-endpoint = <&vop_out_rgb>; 322 }; 323 }; 324 325 }; 326 }; 327 328 saradc: saradc@ff1e0000 { 329 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 330 reg = <0x0 0xff1e0000 0x0 0x100>; 331 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 332 #io-channel-cells = <1>; 333 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 334 clock-names = "saradc", "apb_pclk"; 335 resets = <&cru SRST_SARADC_P>; 336 reset-names = "saradc-apb"; 337 status = "disabled"; 338 }; 339 340 i2s0: i2s@ff300000 { 341 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 342 reg = <0x0 0xff300000 0x0 0x10000>; 343 }; 344 345 i2s1: i2s@ff310000 { 346 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 347 reg = <0x0 0xff100000 0x0 0x10000>; 348 }; 349 350 i2s2: i2s@ff320000 { 351 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 352 reg = <0x0 0xff320000 0x0 0x10000>; 353 }; 354 355 i2s3: i2s@ff330000 { 356 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 357 reg = <0x0 0xff330000 0x0 0x10000>; 358 }; 359 360 vad: vad@ff3c0000 { 361 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 362 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 363 reg-names = "vad", "vad-memory"; 364 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 365 rockchip,audio-src = <0>; 366 rockchip,audio-chnl-num = <8>; 367 rockchip,audio-chnl = <0>; 368 rockchip,mode = <0>; 369 }; 370 371 usb20_otg: usb@ff400000 { 372 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 373 "snps,dwc2"; 374 reg = <0x0 0xff400000 0x0 0x40000>; 375 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cru HCLK_OTG>; 377 clock-names = "otg"; 378 dr_mode = "otg"; 379 g-np-tx-fifo-size = <16>; 380 g-rx-fifo-size = <275>; 381 g-tx-fifo-size = <256 128 128 64 64 32>; 382 g-use-dma; 383 phys = <&u2phy_otg>; 384 phy-names = "usb2-phy"; 385 status = "disabled"; 386 }; 387 388 usb_host0_ehci: usb@ff440000 { 389 compatible = "generic-ehci"; 390 reg = <0x0 0xff440000 0x0 0x10000>; 391 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 393 <&u2phy>; 394 clock-names = "usbhost", "arbiter", "utmi"; 395 phys = <&u2phy_host>; 396 phy-names = "usb"; 397 status = "disabled"; 398 }; 399 400 usb_host0_ohci: usb@ff450000 { 401 compatible = "generic-ohci"; 402 reg = <0x0 0xff450000 0x0 0x10000>; 403 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 405 <&u2phy>; 406 clock-names = "usbhost", "arbiter", "utmi"; 407 phys = <&u2phy_host>; 408 phy-names = "usb"; 409 }; 410 411 sdmmc: dwmmc@ff480000 { 412 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 413 reg = <0x0 0xff480000 0x0 0x4000>; 414 max-frequency = <150000000>; 415 bus-width = <4>; 416 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 417 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 418 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 419 fifo-depth = <0x100>; 420 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 423 status = "disabled"; 424 }; 425 426 emmc: dwmmc@ff490000 { 427 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 428 reg = <0x0 0xff490000 0x0 0x4000>; 429 max-frequency = <150000000>; 430 bus-width = <8>; 431 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 432 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 433 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 434 fifo-depth = <0x100>; 435 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 436 status = "disabled"; 437 }; 438 439 sdio: dwmmc@ff4a0000 { 440 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 441 reg = <0x0 0xff4a0000 0x0 0x4000>; 442 max-frequency = <150000000>; 443 bus-width = <4>; 444 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 445 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 446 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 447 fifo-depth = <0x100>; 448 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 451 status = "disabled"; 452 }; 453 454 nandc: nandc@ff4b0000 { 455 compatible = "rockchip,rk-nandc"; 456 reg = <0x0 0xff4b0000 0x0 0x4000>; 457 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 458 nandc_id = <0>; 459 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 460 clock-names = "clk_nandc", "hclk_nandc"; 461 status = "disabled"; 462 }; 463 464 465 sfc: sfc@ff4c0000 { 466 compatible = "rockchip,rksfc","rockchip,sfc"; 467 reg = <0x0 0xff4c0000 0x0 0x4000>; 468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 470 clock-names = "clk_sfc", "hclk_sfc"; 471 status = "disabled"; 472 }; 473 474 mac: ethernet@ff4e0000 { 475 compatible = "rockchip,rk3308-mac"; 476 reg = <0x0 0xff4e0000 0x0 0x10000>; 477 rockchip,grf = <&grf>; 478 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "macirq"; 480 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 481 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 482 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 483 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 484 clock-names = "stmmaceth", "mac_clk_rx", 485 "mac_clk_tx", "clk_mac_ref", 486 "clk_mac_refout", "aclk_mac", 487 "pclk_mac", "clk_mac_speed"; 488 phy-mode = "rmii"; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 491 resets = <&cru SRST_MAC_A>; 492 reset-names = "stmmaceth"; 493 status = "disabled"; 494 }; 495 496 cru: clock-controller@ff500000 { 497 compatible = "rockchip,rk3308-cru"; 498 reg = <0x0 0xff500000 0x0 0x1000>; 499 rockchip,grf = <&grf>; 500 #clock-cells = <1>; 501 #reset-cells = <1>; 502 }; 503 504 gic: interrupt-controller@ff580000 { 505 compatible = "arm,gic-400"; 506 #interrupt-cells = <3>; 507 #address-cells = <0>; 508 interrupt-controller; 509 510 reg = <0x0 0xff581000 0x0 0x1000>, 511 <0x0 0xff582000 0x0 0x2000>, 512 <0x0 0xff584000 0x0 0x2000>, 513 <0x0 0xff586000 0x0 0x2000>; 514 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 515 }; 516 517 pinctrl: pinctrl { 518 compatible = "rockchip,rk3308-pinctrl"; 519 rockchip,grf = <&grf>; 520 #address-cells = <2>; 521 #size-cells = <2>; 522 ranges; 523 524 gpio0: gpio0@ff220000 { 525 compatible = "rockchip,gpio-bank"; 526 reg = <0x0 0xff220000 0x0 0x100>; 527 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 528 //clocks = <&cru PCLK_GPIO0>; 529 clocks = <&xin24m>; 530 gpio-controller; 531 #gpio-cells = <2>; 532 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 }; 536 537 gpio1: gpio1@ff230000 { 538 compatible = "rockchip,gpio-bank"; 539 reg = <0x0 0xff230000 0x0 0x100>; 540 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 541 //clocks = <&cru PCLK_GPIO1>; 542 clocks = <&xin24m>; 543 gpio-controller; 544 #gpio-cells = <2>; 545 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 550 gpio2: gpio2@ff240000 { 551 compatible = "rockchip,gpio-bank"; 552 reg = <0x0 0xff240000 0x0 0x100>; 553 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 554 //clocks = <&cru PCLK_GPIO2>; 555 clocks = <&xin24m>; 556 gpio-controller; 557 #gpio-cells = <2>; 558 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 }; 562 563 gpio3: gpio3@ff250000 { 564 compatible = "rockchip,gpio-bank"; 565 reg = <0x0 0xff250000 0x0 0x100>; 566 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 567 //clocks = <&cru PCLK_GPIO3>; 568 clocks = <&xin24m>; 569 gpio-controller; 570 #gpio-cells = <2>; 571 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 }; 575 576 gpio4: gpio4@ff260000 { 577 compatible = "rockchip,gpio-bank"; 578 reg = <0x0 0xff260000 0x0 0x100>; 579 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 580 //clocks = <&cru PCLK_GPIO4>; 581 clocks = <&xin24m>; 582 gpio-controller; 583 #gpio-cells = <2>; 584 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 589 pcfg_pull_up: pcfg-pull-up { 590 bias-pull-up; 591 }; 592 593 pcfg_pull_down: pcfg-pull-down { 594 bias-pull-down; 595 }; 596 597 pcfg_pull_none: pcfg-pull-none { 598 bias-disable; 599 }; 600 601 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 602 bias-disable; 603 drive-strength = <2>; 604 }; 605 606 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 607 bias-pull-up; 608 drive-strength = <2>; 609 }; 610 611 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 612 bias-pull-up; 613 drive-strength = <4>; 614 }; 615 616 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 617 bias-disable; 618 drive-strength = <4>; 619 }; 620 621 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 622 bias-pull-down; 623 drive-strength = <4>; 624 }; 625 626 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 627 bias-disable; 628 drive-strength = <8>; 629 }; 630 631 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 632 bias-pull-up; 633 drive-strength = <8>; 634 }; 635 636 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 637 bias-disable; 638 drive-strength = <12>; 639 }; 640 641 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 642 bias-pull-up; 643 drive-strength = <12>; 644 }; 645 646 pcfg_pull_none_smt: pcfg-pull-none-smt { 647 bias-disable; 648 input-schmitt-enable; 649 }; 650 651 pcfg_output_high: pcfg-output-high { 652 output-high; 653 }; 654 655 pcfg_output_low: pcfg-output-low { 656 output-low; 657 }; 658 659 pcfg_input_high: pcfg-input-high { 660 bias-pull-up; 661 input-enable; 662 }; 663 664 pcfg_input: pcfg-input { 665 input-enable; 666 }; 667 668 i2c0 { 669 i2c0_xfer: i2c0-xfer { 670 rockchip,pins = 671 <1 RK_PD0 2 &pcfg_pull_none_smt>, 672 <1 RK_PD1 2 &pcfg_pull_none_smt>; 673 }; 674 }; 675 676 i2c1 { 677 i2c1_xfer: i2c1-xfer { 678 rockchip,pins = 679 <0 RK_PB3 1 &pcfg_pull_none_smt>, 680 <0 RK_PB4 1 &pcfg_pull_none_smt>; 681 }; 682 }; 683 684 i2c2 { 685 i2c2_xfer: i2c2-xfer { 686 rockchip,pins = 687 <2 RK_PA2 3 &pcfg_pull_none_smt>, 688 <2 RK_PA3 3 &pcfg_pull_none_smt>; 689 }; 690 }; 691 692 i2c3-m0 { 693 i2c3m0_xfer: i2c3m0-xfer { 694 rockchip,pins = 695 <0 RK_PB7 2 &pcfg_pull_none_smt>, 696 <0 RK_PC0 2 &pcfg_pull_none_smt>; 697 }; 698 }; 699 700 i2c3-m1 { 701 i2c3m1_xfer: i2c3m1-xfer { 702 rockchip,pins = 703 <3 RK_PB4 2 &pcfg_pull_none_smt>, 704 <3 RK_PB5 2 &pcfg_pull_none_smt>; 705 }; 706 }; 707 708 tsadc { 709 tsadc_otp_gpio: tsadc-otp-gpio { 710 rockchip,pins = 711 <0 RK_PB2 0 &pcfg_pull_none>; 712 }; 713 714 tsadc_otp_out: tsadc-otp-out { 715 rockchip,pins = 716 <0 RK_PB2 1 &pcfg_pull_none>; 717 }; 718 }; 719 720 uart0 { 721 uart0_xfer: uart0-xfer { 722 rockchip,pins = 723 <2 RK_PA1 1 &pcfg_pull_up>, 724 <2 RK_PA0 1 &pcfg_pull_none>; 725 }; 726 727 uart0_cts: uart0-cts { 728 rockchip,pins = 729 <2 RK_PA2 1 &pcfg_pull_none>; 730 }; 731 732 uart0_rts: uart0-rts { 733 rockchip,pins = 734 <2 RK_PA3 1 &pcfg_pull_none>; 735 }; 736 }; 737 738 uart1 { 739 uart1_xfer: uart1-xfer { 740 rockchip,pins = 741 <1 RK_PD1 1 &pcfg_pull_up>, 742 <1 RK_PD0 1 &pcfg_pull_none>; 743 }; 744 745 uart1_cts: uart1-cts { 746 rockchip,pins = 747 <1 RK_PC6 1 &pcfg_pull_none>; 748 }; 749 750 uart1_rts: uart1-rts { 751 rockchip,pins = 752 <1 RK_PC7 1 &pcfg_pull_none>; 753 }; 754 }; 755 756 uart2-m0 { 757 uart2m0_xfer: uart2m0-xfer { 758 rockchip,pins = 759 <1 RK_PC7 2 &pcfg_pull_up>, 760 <1 RK_PC6 2 &pcfg_pull_none>; 761 }; 762 }; 763 764 uart2-m1 { 765 uart2m1_xfer: uart2m1-xfer { 766 rockchip,pins = 767 <4 RK_PD3 2 &pcfg_pull_up>, 768 <4 RK_PD2 2 &pcfg_pull_none>; 769 }; 770 }; 771 772 uart3 { 773 uart3_xfer: uart3-xfer { 774 rockchip,pins = 775 <3 RK_PB5 4 &pcfg_pull_up>, 776 <3 RK_PB4 4 &pcfg_pull_none>; 777 }; 778 }; 779 780 uart4 { 781 782 uart4_xfer: uart4-xfer { 783 rockchip,pins = 784 <4 RK_PB1 1 &pcfg_pull_up>, 785 <4 RK_PB0 1 &pcfg_pull_none>; 786 }; 787 788 uart4_cts: uart4-cts { 789 rockchip,pins = 790 <4 RK_PA6 1 &pcfg_pull_none>; 791 792 }; 793 794 uart4_rts: uart4-rts { 795 rockchip,pins = 796 <4 RK_PA7 1 &pcfg_pull_none>; 797 }; 798 }; 799 800 spi0 { 801 spi0_clk: spi0-clk { 802 rockchip,pins = 803 <2 RK_PA2 2 &pcfg_pull_up>; 804 }; 805 806 spi0_csn0: spi0-csn0 { 807 rockchip,pins = 808 <2 RK_PA3 2 &pcfg_pull_up>; 809 }; 810 811 spi0_miso: spi0-miso { 812 rockchip,pins = 813 <2 RK_PA0 2 &pcfg_pull_up>; 814 }; 815 816 spi0_mosi: spi0-mosi { 817 rockchip,pins = 818 <2 RK_PA1 2 &pcfg_pull_up>; 819 }; 820 }; 821 822 spi1 { 823 spi1_clk: spi1-clk { 824 rockchip,pins = 825 <3 RK_PB3 3 &pcfg_pull_up>; 826 }; 827 828 spi1_csn0: spi1-csn0 { 829 rockchip,pins = 830 <3 RK_PB5 3 &pcfg_pull_up>; 831 }; 832 833 spi1_miso: spi1-miso { 834 rockchip,pins = 835 <3 RK_PB2 3 &pcfg_pull_up>; 836 }; 837 838 spi1_mosi: spi1-mosi { 839 rockchip,pins = 840 <3 RK_PB4 3 &pcfg_pull_up>; 841 }; 842 }; 843 844 spi2 { 845 spi2_clk: spi2-clk { 846 rockchip,pins = 847 <1 RK_PD0 3 &pcfg_pull_up>; 848 }; 849 850 spi2_csn0: spi2-csn0 { 851 rockchip,pins = 852 <1 RK_PD1 3 &pcfg_pull_up>; 853 }; 854 855 spi2_miso: spi2-miso { 856 rockchip,pins = 857 <1 RK_PC6 3 &pcfg_pull_up>; 858 }; 859 860 spi2_mosi: spi2-mosi { 861 rockchip,pins = 862 <1 RK_PC7 3 &pcfg_pull_up>; 863 }; 864 }; 865 866 sdmmc_pin: sdmmc_pin { 867 sdmmc_clk: sdmmc-clk { 868 rockchip,pins = 869 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 870 }; 871 872 sdmmc_cmd: sdmmc-cmd { 873 rockchip,pins = 874 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 875 }; 876 877 sdmmc_pwren: sdmmc-pwren { 878 rockchip,pins = 879 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 880 }; 881 882 sdmmc_bus1: sdmmc-bus1 { 883 rockchip,pins = 884 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 885 }; 886 887 sdmmc_bus4: sdmmc-bus4 { 888 rockchip,pins = 889 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 890 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 891 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 892 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 893 }; 894 895 sdmmc_gpio: sdmmc-gpio { 896 rockchip,pins = 897 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 898 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 899 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 900 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 901 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 902 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 903 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 904 }; 905 }; 906 907 sdio { 908 sdio_clk: sdio-clk { 909 rockchip,pins = 910 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 911 }; 912 913 sdio_cmd: sdio-cmd { 914 rockchip,pins = 915 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 916 }; 917 918 sdio_pwren: sdio-pwren { 919 rockchip,pins = 920 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 921 }; 922 923 sdio_wrpt: sdio-wrpt { 924 rockchip,pins = 925 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 926 }; 927 928 sdio_intn: sdio-intn { 929 rockchip,pins = 930 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 931 }; 932 933 sdio_bus1: sdio-bus1 { 934 rockchip,pins = 935 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 936 }; 937 938 sdio_bus4: sdio-bus4 { 939 rockchip,pins = 940 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 941 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 942 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 943 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 944 }; 945 946 sdio_gpio: sdio-gpio { 947 rockchip,pins = 948 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 949 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 950 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 951 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 952 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 953 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 954 }; 955 }; 956 957 emmc { 958 emmc_clk: emmc-clk { 959 rockchip,pins = 960 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 961 }; 962 963 emmc_cmd: emmc-cmd { 964 rockchip,pins = 965 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 966 }; 967 968 emmc_pwren: emmc-pwren { 969 rockchip,pins = 970 <3 RK_PB3 2 &pcfg_pull_none>; 971 }; 972 973 emmc_rstn: emmc-rstn { 974 rockchip,pins = 975 <3 RK_PB2 2 &pcfg_pull_none>; 976 }; 977 978 emmc_bus1: emmc-bus1 { 979 rockchip,pins = 980 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 981 }; 982 983 emmc_bus4: emmc-bus4 { 984 rockchip,pins = 985 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 986 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 987 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 988 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 989 }; 990 991 emmc_bus8: emmc-bus8 { 992 rockchip,pins = 993 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 994 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 995 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 996 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 997 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 998 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 999 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 1000 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 1001 }; 1002 }; 1003 1004 flash { 1005 flash_csn0: flash-csn0 { 1006 rockchip,pins = 1007 <3 RK_PB5 1 &pcfg_pull_none>; 1008 }; 1009 1010 flash_rdy: flash-rdy { 1011 rockchip,pins = 1012 <3 RK_PB4 1 &pcfg_pull_none>; 1013 }; 1014 1015 flash_ale: flash-ale { 1016 rockchip,pins = 1017 <3 RK_PB3 1 &pcfg_pull_none>; 1018 }; 1019 1020 flash_cle: flash-cle { 1021 rockchip,pins = 1022 <3 RK_PB1 1 &pcfg_pull_none>; 1023 }; 1024 1025 flash_wrn: flash-wrn { 1026 rockchip,pins = 1027 <3 RK_PB0 1 &pcfg_pull_none>; 1028 }; 1029 1030 flash_rdn: flash-rdn { 1031 rockchip,pins = 1032 <3 RK_PB2 1 &pcfg_pull_none>; 1033 }; 1034 1035 flash_bus8: flash-bus8 { 1036 rockchip,pins = 1037 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1038 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1039 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1040 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1041 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1042 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1043 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1044 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1045 }; 1046 }; 1047 1048 pwm0 { 1049 pwm0_pin: pwm0-pin { 1050 rockchip,pins = 1051 <0 RK_PB5 1 &pcfg_pull_none>; 1052 }; 1053 }; 1054 1055 pwm1 { 1056 pwm1_pin: pwm1-pin { 1057 rockchip,pins = 1058 <0 RK_PB6 1 &pcfg_pull_none>; 1059 }; 1060 }; 1061 1062 pwm2 { 1063 pwm2_pin: pwm2-pin { 1064 rockchip,pins = 1065 <0 RK_PB7 1 &pcfg_pull_none>; 1066 }; 1067 }; 1068 1069 pwm3 { 1070 pwm3_pin: pwm3-pin { 1071 rockchip,pins = 1072 <0 RK_PC0 1 &pcfg_pull_none>; 1073 }; 1074 }; 1075 1076 gmac { 1077 rmii_pins: rmii-pins { 1078 rockchip,pins = 1079 /* mac_txen */ 1080 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1081 /* mac_txd1 */ 1082 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1083 /* mac_txd0 */ 1084 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1085 /* mac_rxd0 */ 1086 <1 RK_PC4 3 &pcfg_pull_none>, 1087 /* mac_rxd1 */ 1088 <1 RK_PC5 3 &pcfg_pull_none>, 1089 /* mac_rxer */ 1090 <1 RK_PB7 3 &pcfg_pull_none>, 1091 /* mac_rxdv */ 1092 <1 RK_PC0 3 &pcfg_pull_none>, 1093 /* mac_mdio */ 1094 <1 RK_PB6 3 &pcfg_pull_none>, 1095 /* mac_mdc */ 1096 <1 RK_PB5 3 &pcfg_pull_none>; 1097 }; 1098 1099 mac_refclk_12ma: mac-refclk-12ma { 1100 rockchip,pins = 1101 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1102 }; 1103 1104 mac_refclk: mac-refclk { 1105 rockchip,pins = 1106 <1 RK_PB4 3 &pcfg_pull_none>; 1107 }; 1108 1109 }; 1110 1111 lcdc { 1112 lcdc_ctl: lcdc-ctl { 1113 rockchip,pins = 1114 /* dclk */ 1115 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1116 /* hsync */ 1117 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1118 /* vsync */ 1119 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1120 /* den */ 1121 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1122 /* d0 */ 1123 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1124 /* d1 */ 1125 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1126 /* d2 */ 1127 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1128 /* d3 */ 1129 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1130 /* d4 */ 1131 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1132 /* d5 */ 1133 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1134 /* d6 */ 1135 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1136 /* d7 */ 1137 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1138 /* d8 */ 1139 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1140 /* d9 */ 1141 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1142 /* d10 */ 1143 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1144 /* d11 */ 1145 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1146 /* d12 */ 1147 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1148 /* d13 */ 1149 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1150 /* d14 */ 1151 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1152 /* d15 */ 1153 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1154 /* d16 */ 1155 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1156 /* d17 */ 1157 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1158 }; 1159 }; 1160 }; 1161}; 1162
