1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 }; 25 26 cpus { 27 #address-cells = <2>; 28 #size-cells = <0>; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a35", "arm,armv8"; 33 reg = <0x0 0x0>; 34 enable-method = "psci"; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a35", "arm,armv8"; 40 reg = <0x0 0x1>; 41 enable-method = "psci"; 42 }; 43 44 cpu2: cpu@2 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35", "arm,armv8"; 47 reg = <0x0 0x2>; 48 enable-method = "psci"; 49 }; 50 51 cpu3: cpu@3 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35", "arm,armv8"; 54 reg = <0x0 0x3>; 55 enable-method = "psci"; 56 }; 57 }; 58 59 arm-pmu { 60 compatible = "arm,cortex-a53-pmu"; 61 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 65 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 66 }; 67 68 psci { 69 compatible = "arm,psci-1.0"; 70 method = "smc"; 71 }; 72 73 timer { 74 compatible = "arm,armv8-timer"; 75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 77 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 78 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 79 clock-frequency = <24000000>; 80 }; 81 82 clocks { 83 xin24m: xin24m { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <24000000>; 87 clock-output-names = "xin24m"; 88 }; 89 }; 90 91 grf: grf@ff000000 { 92 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 93 reg = <0x0 0xff000000 0x0 0x10000>; 94 }; 95 96 usb2phy_grf: syscon@ff008000 { 97 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 98 "simple-mfd"; 99 reg = <0x0 0xff008000 0x0 0x4000>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 103 u2phy: usb2-phy@100 { 104 compatible = "rockchip,rk3308-usb2phy", 105 "rockchip,rk3328-usb2phy"; 106 reg = <0x100 0x10>; 107 clocks = <&cru SCLK_USBPHY_REF>; 108 clock-names = "phyclk"; 109 #clock-cells = <0>; 110 assigned-clocks = <&cru USB480M>; 111 assigned-clock-parents = <&u2phy>; 112 clock-output-names = "usb480m_phy"; 113 status = "disabled"; 114 115 u2phy_host: host-port { 116 #phy-cells = <0>; 117 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 118 interrupt-names = "linestate"; 119 status = "disabled"; 120 }; 121 122 u2phy_otg: otg-port { 123 #phy-cells = <0>; 124 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-names = "otg-bvalid", "otg-id", 128 "linestate"; 129 status = "disabled"; 130 }; 131 }; 132 }; 133 134 uart0: serial@ff0a0000 { 135 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 136 reg = <0x0 0xff0a0000 0x0 0x100>; 137 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 139 clock-names = "baudclk", "apb_pclk"; 140 reg-shift = <2>; 141 reg-io-width = <4>; 142 status = "disabled"; 143 }; 144 145 uart1: serial@ff0b0000 { 146 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 147 reg = <0x0 0xff0b0000 0x0 0x100>; 148 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 150 clock-names = "baudclk", "apb_pclk"; 151 reg-shift = <2>; 152 reg-io-width = <4>; 153 status = "disabled"; 154 }; 155 156 uart2: serial@ff0c0000 { 157 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 158 reg = <0x0 0xff0c0000 0x0 0x100>; 159 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 161 clock-names = "baudclk", "apb_pclk"; 162 reg-shift = <2>; 163 reg-io-width = <4>; 164 status = "disabled"; 165 }; 166 167 pwm0: pwm@ff180000 { 168 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 169 reg = <0x0 0xff180000 0x0 0x10>; 170 #pwm-cells = <3>; 171 pinctrl-names = "active"; 172 pinctrl-0 = <&pwm0_pin>; 173 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 174 clock-names = "pwm", "pclk"; 175 status = "disabled"; 176 }; 177 178 pwm1: pwm@ff180010 { 179 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 180 reg = <0x0 0xff180010 0x0 0x10>; 181 #pwm-cells = <3>; 182 pinctrl-names = "active"; 183 pinctrl-0 = <&pwm1_pin>; 184 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 185 clock-names = "pwm", "pclk"; 186 status = "disabled"; 187 }; 188 189 pwm2: pwm@ff180020 { 190 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 191 reg = <0x0 0xff180020 0x0 0x10>; 192 #pwm-cells = <3>; 193 pinctrl-names = "active"; 194 pinctrl-0 = <&pwm2_pin>; 195 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 196 clock-names = "pwm", "pclk"; 197 status = "disabled"; 198 }; 199 200 pwm3: pwm@ff180030 { 201 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 202 reg = <0x0 0xff180030 0x0 0x10>; 203 #pwm-cells = <3>; 204 pinctrl-names = "active"; 205 pinctrl-0 = <&pwm3_pin>; 206 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 207 clock-names = "pwm", "pclk"; 208 status = "disabled"; 209 }; 210 211 saradc: saradc@ff1e0000 { 212 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 213 reg = <0x0 0xff1e0000 0x0 0x100>; 214 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 215 #io-channel-cells = <1>; 216 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 217 clock-names = "saradc", "apb_pclk"; 218 resets = <&cru SRST_SARADC_P>; 219 reset-names = "saradc-apb"; 220 status = "disabled"; 221 }; 222 223 i2s0: i2s@ff300000 { 224 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 225 reg = <0x0 0xff300000 0x0 0x10000>; 226 }; 227 228 i2s1: i2s@ff310000 { 229 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 230 reg = <0x0 0xff100000 0x0 0x10000>; 231 }; 232 233 i2s2: i2s@ff320000 { 234 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 235 reg = <0x0 0xff320000 0x0 0x10000>; 236 }; 237 238 i2s3: i2s@ff330000 { 239 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 240 reg = <0x0 0xff330000 0x0 0x10000>; 241 }; 242 243 vad: vad@ff3c0000 { 244 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 245 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 246 reg-names = "vad", "vad-memory"; 247 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 248 rockchip,audio-src = <0>; 249 rockchip,audio-chnl-num = <8>; 250 rockchip,audio-chnl = <0>; 251 rockchip,mode = <0>; 252 }; 253 254 usb20_otg: usb@ff400000 { 255 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 256 "snps,dwc2"; 257 reg = <0x0 0xff400000 0x0 0x40000>; 258 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&cru HCLK_OTG>; 260 clock-names = "otg"; 261 dr_mode = "otg"; 262 g-np-tx-fifo-size = <16>; 263 g-rx-fifo-size = <275>; 264 g-tx-fifo-size = <256 128 128 64 64 32>; 265 g-use-dma; 266 phys = <&u2phy_otg>; 267 phy-names = "usb2-phy"; 268 status = "disabled"; 269 }; 270 271 usb_host0_ehci: usb@ff440000 { 272 compatible = "generic-ehci"; 273 reg = <0x0 0xff440000 0x0 0x10000>; 274 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 276 <&u2phy>; 277 clock-names = "usbhost", "arbiter", "utmi"; 278 phys = <&u2phy_host>; 279 phy-names = "usb"; 280 status = "disabled"; 281 }; 282 283 usb_host0_ohci: usb@ff450000 { 284 compatible = "generic-ohci"; 285 reg = <0x0 0xff450000 0x0 0x10000>; 286 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 288 <&u2phy>; 289 clock-names = "usbhost", "arbiter", "utmi"; 290 phys = <&u2phy_host>; 291 phy-names = "usb"; 292 }; 293 294 sdmmc: dwmmc@ff480000 { 295 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 296 reg = <0x0 0xff480000 0x0 0x4000>; 297 max-frequency = <150000000>; 298 bus-width = <4>; 299 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 300 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 301 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 302 fifo-depth = <0x100>; 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 306 status = "disabled"; 307 }; 308 309 emmc: dwmmc@ff490000 { 310 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 311 reg = <0x0 0xff490000 0x0 0x4000>; 312 max-frequency = <150000000>; 313 bus-width = <8>; 314 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 315 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 316 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 317 fifo-depth = <0x100>; 318 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; 321 status = "disabled"; 322 }; 323 324 sdio: dwmmc@ff4a0000 { 325 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 326 reg = <0x0 0xff4a0000 0x0 0x4000>; 327 max-frequency = <150000000>; 328 bus-width = <4>; 329 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 330 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 331 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 332 fifo-depth = <0x100>; 333 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 336 status = "disabled"; 337 }; 338 339 cru: clock-controller@ff500000 { 340 compatible = "rockchip,rk3308-cru"; 341 reg = <0x0 0xff500000 0x0 0x1000>; 342 rockchip,grf = <&grf>; 343 #clock-cells = <1>; 344 #reset-cells = <1>; 345 }; 346 347 gic: interrupt-controller@ff580000 { 348 compatible = "arm,gic-400"; 349 #interrupt-cells = <3>; 350 #address-cells = <0>; 351 interrupt-controller; 352 353 reg = <0x0 0xff581000 0x0 0x1000>, 354 <0x0 0xff582000 0x0 0x2000>, 355 <0x0 0xff584000 0x0 0x2000>, 356 <0x0 0xff586000 0x0 0x2000>; 357 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 358 }; 359 360 pinctrl: pinctrl { 361 compatible = "rockchip,rk3308-pinctrl"; 362 rockchip,grf = <&grf>; 363 #address-cells = <2>; 364 #size-cells = <2>; 365 ranges; 366 367 gpio0: gpio0@ff220000 { 368 compatible = "rockchip,gpio-bank"; 369 reg = <0x0 0xff220000 0x0 0x100>; 370 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 371 //clocks = <&cru PCLK_GPIO0>; 372 clocks = <&xin24m>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 }; 379 380 gpio1: gpio1@ff230000 { 381 compatible = "rockchip,gpio-bank"; 382 reg = <0x0 0xff230000 0x0 0x100>; 383 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 384 //clocks = <&cru PCLK_GPIO1>; 385 clocks = <&xin24m>; 386 gpio-controller; 387 #gpio-cells = <2>; 388 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 }; 392 393 gpio2: gpio2@ff240000 { 394 compatible = "rockchip,gpio-bank"; 395 reg = <0x0 0xff240000 0x0 0x100>; 396 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 397 //clocks = <&cru PCLK_GPIO2>; 398 clocks = <&xin24m>; 399 gpio-controller; 400 #gpio-cells = <2>; 401 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 }; 405 406 gpio3: gpio3@ff250000 { 407 compatible = "rockchip,gpio-bank"; 408 reg = <0x0 0xff250000 0x0 0x100>; 409 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 410 //clocks = <&cru PCLK_GPIO3>; 411 clocks = <&xin24m>; 412 gpio-controller; 413 #gpio-cells = <2>; 414 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 419 gpio4: gpio4@ff260000 { 420 compatible = "rockchip,gpio-bank"; 421 reg = <0x0 0xff260000 0x0 0x100>; 422 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 423 //clocks = <&cru PCLK_GPIO4>; 424 clocks = <&xin24m>; 425 gpio-controller; 426 #gpio-cells = <2>; 427 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 }; 431 432 pcfg_pull_up: pcfg-pull-up { 433 bias-pull-up; 434 }; 435 436 pcfg_pull_down: pcfg-pull-down { 437 bias-pull-down; 438 }; 439 440 pcfg_pull_none: pcfg-pull-none { 441 bias-disable; 442 }; 443 444 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 445 bias-disable; 446 drive-strength = <2>; 447 }; 448 449 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 450 bias-pull-up; 451 drive-strength = <2>; 452 }; 453 454 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 455 bias-pull-up; 456 drive-strength = <4>; 457 }; 458 459 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 460 bias-disable; 461 drive-strength = <4>; 462 }; 463 464 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 465 bias-pull-down; 466 drive-strength = <4>; 467 }; 468 469 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 470 bias-disable; 471 drive-strength = <8>; 472 }; 473 474 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 475 bias-pull-up; 476 drive-strength = <8>; 477 }; 478 479 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 480 bias-disable; 481 drive-strength = <12>; 482 }; 483 484 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 485 bias-pull-up; 486 drive-strength = <12>; 487 }; 488 489 pcfg_pull_none_smt: pcfg-pull-none-smt { 490 bias-disable; 491 input-schmitt-enable; 492 }; 493 494 pcfg_output_high: pcfg-output-high { 495 output-high; 496 }; 497 498 pcfg_output_low: pcfg-output-low { 499 output-low; 500 }; 501 502 pcfg_input_high: pcfg-input-high { 503 bias-pull-up; 504 input-enable; 505 }; 506 507 pcfg_input: pcfg-input { 508 input-enable; 509 }; 510 511 i2c0 { 512 i2c0_xfer: i2c0-xfer { 513 rockchip,pins = 514 <1 RK_PD0 2 &pcfg_pull_none_smt>, 515 <1 RK_PD1 2 &pcfg_pull_none_smt>; 516 }; 517 }; 518 519 i2c1 { 520 i2c1_xfer: i2c1-xfer { 521 rockchip,pins = 522 <0 RK_PB3 1 &pcfg_pull_none_smt>, 523 <0 RK_PB4 1 &pcfg_pull_none_smt>; 524 }; 525 }; 526 527 i2c2 { 528 i2c2_xfer: i2c2-xfer { 529 rockchip,pins = 530 <2 RK_PA2 3 &pcfg_pull_none_smt>, 531 <2 RK_PA3 3 &pcfg_pull_none_smt>; 532 }; 533 }; 534 535 i2c3-m0 { 536 i2c3m0_xfer: i2c3m0-xfer { 537 rockchip,pins = 538 <0 RK_PB7 2 &pcfg_pull_none_smt>, 539 <0 RK_PC0 2 &pcfg_pull_none_smt>; 540 }; 541 }; 542 543 i2c3-m1 { 544 i2c3m1_xfer: i2c3m1-xfer { 545 rockchip,pins = 546 <3 RK_PB4 2 &pcfg_pull_none_smt>, 547 <3 RK_PB5 2 &pcfg_pull_none_smt>; 548 }; 549 }; 550 551 tsadc { 552 tsadc_otp_gpio: tsadc-otp-gpio { 553 rockchip,pins = 554 <0 RK_PB2 0 &pcfg_pull_none>; 555 }; 556 557 tsadc_otp_out: tsadc-otp-out { 558 rockchip,pins = 559 <0 RK_PB2 1 &pcfg_pull_none>; 560 }; 561 }; 562 563 uart0 { 564 uart0_xfer: uart0-xfer { 565 rockchip,pins = 566 <2 RK_PA1 1 &pcfg_pull_up>, 567 <2 RK_PA0 1 &pcfg_pull_none>; 568 }; 569 570 uart0_cts: uart0-cts { 571 rockchip,pins = 572 <2 RK_PA2 1 &pcfg_pull_none>; 573 }; 574 575 uart0_rts: uart0-rts { 576 rockchip,pins = 577 <2 RK_PA3 1 &pcfg_pull_none>; 578 }; 579 }; 580 581 uart1 { 582 uart1_xfer: uart1-xfer { 583 rockchip,pins = 584 <1 RK_PD1 1 &pcfg_pull_up>, 585 <1 RK_PD0 1 &pcfg_pull_none>; 586 }; 587 588 uart1_cts: uart1-cts { 589 rockchip,pins = 590 <1 RK_PC6 1 &pcfg_pull_none>; 591 }; 592 593 uart1_rts: uart1-rts { 594 rockchip,pins = 595 <1 RK_PC7 1 &pcfg_pull_none>; 596 }; 597 }; 598 599 uart2-m0 { 600 uart2m0_xfer: uart2m0-xfer { 601 rockchip,pins = 602 <1 RK_PC7 2 &pcfg_pull_up>, 603 <1 RK_PC6 2 &pcfg_pull_none>; 604 }; 605 }; 606 607 uart2-m1 { 608 uart2m1_xfer: uart2m1-xfer { 609 rockchip,pins = 610 <4 RK_PD3 2 &pcfg_pull_up>, 611 <4 RK_PD2 2 &pcfg_pull_none>; 612 }; 613 }; 614 615 uart3 { 616 uart3_xfer: uart3-xfer { 617 rockchip,pins = 618 <3 RK_PB5 4 &pcfg_pull_up>, 619 <3 RK_PB4 4 &pcfg_pull_none>; 620 }; 621 }; 622 623 uart4 { 624 625 uart4_xfer: uart4-xfer { 626 rockchip,pins = 627 <4 RK_PB1 1 &pcfg_pull_up>, 628 <4 RK_PB0 1 &pcfg_pull_none>; 629 }; 630 631 uart4_cts: uart4-cts { 632 rockchip,pins = 633 <4 RK_PA6 1 &pcfg_pull_none>; 634 635 }; 636 637 uart4_rts: uart4-rts { 638 rockchip,pins = 639 <4 RK_PA7 1 &pcfg_pull_none>; 640 }; 641 }; 642 643 spi0 { 644 spi0_clk: spi0-clk { 645 rockchip,pins = 646 <2 RK_PA2 2 &pcfg_pull_up>; 647 }; 648 649 spi0_csn0: spi0-csn0 { 650 rockchip,pins = 651 <2 RK_PA3 2 &pcfg_pull_up>; 652 }; 653 654 spi0_miso: spi0-miso { 655 rockchip,pins = 656 <2 RK_PA0 2 &pcfg_pull_up>; 657 }; 658 659 spi0_mosi: spi0-mosi { 660 rockchip,pins = 661 <2 RK_PA1 2 &pcfg_pull_up>; 662 }; 663 }; 664 665 spi1 { 666 spi1_clk: spi1-clk { 667 rockchip,pins = 668 <3 RK_PB3 3 &pcfg_pull_up>; 669 }; 670 671 spi1_csn0: spi1-csn0 { 672 rockchip,pins = 673 <3 RK_PB5 3 &pcfg_pull_up>; 674 }; 675 676 spi1_miso: spi1-miso { 677 rockchip,pins = 678 <3 RK_PB2 3 &pcfg_pull_up>; 679 }; 680 681 spi1_mosi: spi1-mosi { 682 rockchip,pins = 683 <3 RK_PB4 3 &pcfg_pull_up>; 684 }; 685 }; 686 687 spi2 { 688 spi2_clk: spi2-clk { 689 rockchip,pins = 690 <1 RK_PD0 3 &pcfg_pull_up>; 691 }; 692 693 spi2_csn0: spi2-csn0 { 694 rockchip,pins = 695 <1 RK_PD1 3 &pcfg_pull_up>; 696 }; 697 698 spi2_miso: spi2-miso { 699 rockchip,pins = 700 <1 RK_PC6 3 &pcfg_pull_up>; 701 }; 702 703 spi2_mosi: spi2-mosi { 704 rockchip,pins = 705 <1 RK_PC7 3 &pcfg_pull_up>; 706 }; 707 }; 708 709 sdmmc { 710 sdmmc_clk: sdmmc-clk { 711 rockchip,pins = 712 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 713 }; 714 715 sdmmc_cmd: sdmmc-cmd { 716 rockchip,pins = 717 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 718 }; 719 720 sdmmc_pwren: sdmmc-pwren { 721 rockchip,pins = 722 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 723 }; 724 725 sdmmc_bus1: sdmmc-bus1 { 726 rockchip,pins = 727 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 728 }; 729 730 sdmmc_bus4: sdmmc-bus4 { 731 rockchip,pins = 732 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 733 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 734 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 735 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 736 }; 737 738 sdmmc_gpio: sdmmc-gpio { 739 rockchip,pins = 740 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 741 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 742 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 743 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 744 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 745 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 746 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 747 }; 748 }; 749 750 sdio { 751 sdio_clk: sdio-clk { 752 rockchip,pins = 753 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 754 }; 755 756 sdio_cmd: sdio-cmd { 757 rockchip,pins = 758 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 759 }; 760 761 sdio_pwren: sdio-pwren { 762 rockchip,pins = 763 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 764 }; 765 766 sdio_wrpt: sdio-wrpt { 767 rockchip,pins = 768 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 769 }; 770 771 sdio_intn: sdio-intn { 772 rockchip,pins = 773 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 774 }; 775 776 sdio_bus1: sdio-bus1 { 777 rockchip,pins = 778 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 779 }; 780 781 sdio_bus4: sdio-bus4 { 782 rockchip,pins = 783 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 784 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 785 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 786 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 787 }; 788 789 sdio_gpio: sdio-gpio { 790 rockchip,pins = 791 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 792 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 793 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 794 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 795 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 796 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 797 }; 798 }; 799 800 emmc { 801 emmc_clk: emmc-clk { 802 rockchip,pins = 803 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 804 }; 805 806 emmc_cmd: emmc-cmd { 807 rockchip,pins = 808 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 809 }; 810 811 emmc_pwren: emmc-pwren { 812 rockchip,pins = 813 <3 RK_PB3 2 &pcfg_pull_none>; 814 }; 815 816 emmc_rstn: emmc-rstn { 817 rockchip,pins = 818 <3 RK_PB2 2 &pcfg_pull_none>; 819 }; 820 821 emmc_bus1: emmc-bus1 { 822 rockchip,pins = 823 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 824 }; 825 826 emmc_bus4: emmc-bus4 { 827 rockchip,pins = 828 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 829 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 830 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 831 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 832 }; 833 834 emmc_bus8: emmc-bus8 { 835 rockchip,pins = 836 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 837 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 838 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 839 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 840 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 841 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 842 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 843 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 844 }; 845 }; 846 847 flash { 848 flash_csn0: flash-csn0 { 849 rockchip,pins = 850 <3 RK_PB5 1 &pcfg_pull_none>; 851 }; 852 853 flash_rdy: flash-rdy { 854 rockchip,pins = 855 <3 RK_PB4 1 &pcfg_pull_none>; 856 }; 857 858 flash_ale: flash-ale { 859 rockchip,pins = 860 <3 RK_PB3 1 &pcfg_pull_none>; 861 }; 862 863 flash_cle: flash-cle { 864 rockchip,pins = 865 <3 RK_PB1 1 &pcfg_pull_none>; 866 }; 867 868 flash_wrn: flash-wrn { 869 rockchip,pins = 870 <3 RK_PB0 1 &pcfg_pull_none>; 871 }; 872 873 flash_rdn: flash-rdn { 874 rockchip,pins = 875 <3 RK_PB2 1 &pcfg_pull_none>; 876 }; 877 878 flash_bus8: flash-bus8 { 879 rockchip,pins = 880 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 881 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 882 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 883 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 884 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 885 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 886 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 887 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 888 }; 889 }; 890 891 pwm0 { 892 pwm0_pin: pwm0-pin { 893 rockchip,pins = 894 <0 RK_PB5 1 &pcfg_pull_none>; 895 }; 896 }; 897 898 pwm1 { 899 pwm1_pin: pwm1-pin { 900 rockchip,pins = 901 <0 RK_PB6 1 &pcfg_pull_none>; 902 }; 903 }; 904 905 pwm2 { 906 pwm2_pin: pwm2-pin { 907 rockchip,pins = 908 <0 RK_PB7 1 &pcfg_pull_none>; 909 }; 910 }; 911 912 pwm3 { 913 pwm3_pin: pwm3-pin { 914 rockchip,pins = 915 <0 RK_PC0 1 &pcfg_pull_none>; 916 }; 917 }; 918 919 gmac { 920 rmii_pins: rmii-pins { 921 rockchip,pins = 922 /* mac_txen */ 923 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 924 /* mac_txd1 */ 925 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 926 /* mac_txd0 */ 927 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 928 /* mac_rxd0 */ 929 <1 RK_PC4 3 &pcfg_pull_none>, 930 /* mac_rxd1 */ 931 <1 RK_PC5 3 &pcfg_pull_none>, 932 /* mac_rxer */ 933 <1 RK_PB7 3 &pcfg_pull_none>, 934 /* mac_rxdv */ 935 <1 RK_PC0 3 &pcfg_pull_none>, 936 /* mac_mdio */ 937 <1 RK_PB6 3 &pcfg_pull_none>, 938 /* mac_mdc */ 939 <1 RK_PB5 3 &pcfg_pull_none>, 940 /* mac_clk */ 941 <1 RK_PB4 3 &pcfg_pull_none>; 942 }; 943 }; 944 }; 945}; 946