1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a35", "arm,armv8"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a35", "arm,armv8"; 42 reg = <0x0 0x1>; 43 enable-method = "psci"; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a35", "arm,armv8"; 49 reg = <0x0 0x2>; 50 enable-method = "psci"; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35", "arm,armv8"; 56 reg = <0x0 0x3>; 57 enable-method = "psci"; 58 }; 59 }; 60 61 arm-pmu { 62 compatible = "arm,cortex-a53-pmu"; 63 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 68 }; 69 70 display_subsystem: display-subsystem { 71 compatible = "rockchip,display-subsystem"; 72 ports = <&vop_out>; 73 status = "disabled"; 74 75 route { 76 route_rgb: route-rgb { 77 status = "okay"; 78 logo,uboot = "logo.bmp"; 79 logo,kernel = "logo_kernel.bmp"; 80 logo,mode = "center"; 81 charge_logo,mode = "center"; 82 connect = <&vop_out_rgb>; 83 }; 84 }; 85 }; 86 87 dmc: dmc@20004000 { 88 compatible = "rockchip,rk3308-dmc"; 89 reg = <0x0 0xff010000 0x0 0x10000>; 90 }; 91 92 psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 timer { 98 compatible = "arm,armv8-timer"; 99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 clock-frequency = <24000000>; 104 }; 105 106 clocks { 107 xin24m: xin24m { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <24000000>; 111 clock-output-names = "xin24m"; 112 }; 113 }; 114 115 grf: grf@ff000000 { 116 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 117 reg = <0x0 0xff000000 0x0 0x10000>; 118 }; 119 120 usb2phy_grf: syscon@ff008000 { 121 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 122 "simple-mfd"; 123 reg = <0x0 0xff008000 0x0 0x4000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 127 u2phy: usb2-phy@100 { 128 compatible = "rockchip,rk3308-usb2phy", 129 "rockchip,rk3328-usb2phy"; 130 reg = <0x100 0x10>; 131 clocks = <&cru SCLK_USBPHY_REF>; 132 clock-names = "phyclk"; 133 #clock-cells = <0>; 134 assigned-clocks = <&cru USB480M>; 135 assigned-clock-parents = <&u2phy>; 136 clock-output-names = "usb480m_phy"; 137 status = "disabled"; 138 139 u2phy_host: host-port { 140 #phy-cells = <0>; 141 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-names = "linestate"; 143 status = "disabled"; 144 }; 145 146 u2phy_otg: otg-port { 147 #phy-cells = <0>; 148 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-names = "otg-bvalid", "otg-id", 152 "linestate"; 153 status = "disabled"; 154 }; 155 }; 156 }; 157 158 uart0: serial@ff0a0000 { 159 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 160 reg = <0x0 0xff0a0000 0x0 0x100>; 161 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 163 clock-names = "baudclk", "apb_pclk"; 164 reg-shift = <2>; 165 reg-io-width = <4>; 166 status = "disabled"; 167 }; 168 169 uart1: serial@ff0b0000 { 170 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 171 reg = <0x0 0xff0b0000 0x0 0x100>; 172 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 174 clock-names = "baudclk", "apb_pclk"; 175 reg-shift = <2>; 176 reg-io-width = <4>; 177 status = "disabled"; 178 }; 179 180 uart2: serial@ff0c0000 { 181 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 182 reg = <0x0 0xff0c0000 0x0 0x100>; 183 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 185 clock-names = "baudclk", "apb_pclk"; 186 reg-shift = <2>; 187 reg-io-width = <4>; 188 status = "disabled"; 189 }; 190 191 uart3: serial@ff0d0000 { 192 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 193 reg = <0x0 0xff0d0000 0x0 0x100>; 194 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 196 clock-names = "baudclk", "apb_pclk"; 197 reg-shift = <2>; 198 reg-io-width = <4>; 199 status = "disabled"; 200 }; 201 202 uart4: serial@ff0e0000 { 203 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 204 reg = <0x0 0xff0e0000 0x0 0x100>; 205 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 207 clock-names = "baudclk", "apb_pclk"; 208 reg-shift = <2>; 209 reg-io-width = <4>; 210 status = "disabled"; 211 }; 212 213 vop: vop@ff2e0000 { 214 compatible = "rockchip,rk3308-vop"; 215 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 216 reg-names = "regs", "gamma_lut"; 217 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 219 <&cru HCLK_VOP>; 220 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 221 status = "disabled"; 222 223 vop_out: port { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 vop_out_rgb: endpoint@0 { 228 reg = <0>; 229 remote-endpoint = <&rgb_in_vop>; 230 }; 231 }; 232 }; 233 234 pwm0: pwm@ff180000 { 235 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 236 reg = <0x0 0xff180000 0x0 0x10>; 237 #pwm-cells = <3>; 238 pinctrl-names = "active"; 239 pinctrl-0 = <&pwm0_pin>; 240 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 241 clock-names = "pwm", "pclk"; 242 status = "disabled"; 243 }; 244 245 pwm1: pwm@ff180010 { 246 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 247 reg = <0x0 0xff180010 0x0 0x10>; 248 #pwm-cells = <3>; 249 pinctrl-names = "active"; 250 pinctrl-0 = <&pwm1_pin>; 251 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 252 clock-names = "pwm", "pclk"; 253 status = "disabled"; 254 }; 255 256 pwm2: pwm@ff180020 { 257 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 258 reg = <0x0 0xff180020 0x0 0x10>; 259 #pwm-cells = <3>; 260 pinctrl-names = "active"; 261 pinctrl-0 = <&pwm2_pin>; 262 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 263 clock-names = "pwm", "pclk"; 264 status = "disabled"; 265 }; 266 267 pwm3: pwm@ff180030 { 268 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 269 reg = <0x0 0xff180030 0x0 0x10>; 270 #pwm-cells = <3>; 271 pinctrl-names = "active"; 272 pinctrl-0 = <&pwm3_pin>; 273 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 274 clock-names = "pwm", "pclk"; 275 status = "disabled"; 276 }; 277 278 rgb: rgb { 279 compatible = "rockchip,rk3308-rgb"; 280 status = "disabled"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&lcdc_ctl>; 283 284 ports { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 port@0 { 289 reg = <0>; 290 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 rgb_in_vop: endpoint@0 { 295 reg = <0>; 296 remote-endpoint = <&vop_out_rgb>; 297 }; 298 }; 299 300 }; 301 }; 302 303 saradc: saradc@ff1e0000 { 304 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 305 reg = <0x0 0xff1e0000 0x0 0x100>; 306 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 307 #io-channel-cells = <1>; 308 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 309 clock-names = "saradc", "apb_pclk"; 310 resets = <&cru SRST_SARADC_P>; 311 reset-names = "saradc-apb"; 312 status = "disabled"; 313 }; 314 315 i2s0: i2s@ff300000 { 316 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 317 reg = <0x0 0xff300000 0x0 0x10000>; 318 }; 319 320 i2s1: i2s@ff310000 { 321 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 322 reg = <0x0 0xff100000 0x0 0x10000>; 323 }; 324 325 i2s2: i2s@ff320000 { 326 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 327 reg = <0x0 0xff320000 0x0 0x10000>; 328 }; 329 330 i2s3: i2s@ff330000 { 331 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 332 reg = <0x0 0xff330000 0x0 0x10000>; 333 }; 334 335 vad: vad@ff3c0000 { 336 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 337 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 338 reg-names = "vad", "vad-memory"; 339 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 340 rockchip,audio-src = <0>; 341 rockchip,audio-chnl-num = <8>; 342 rockchip,audio-chnl = <0>; 343 rockchip,mode = <0>; 344 }; 345 346 usb20_otg: usb@ff400000 { 347 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 348 "snps,dwc2"; 349 reg = <0x0 0xff400000 0x0 0x40000>; 350 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cru HCLK_OTG>; 352 clock-names = "otg"; 353 dr_mode = "otg"; 354 g-np-tx-fifo-size = <16>; 355 g-rx-fifo-size = <275>; 356 g-tx-fifo-size = <256 128 128 64 64 32>; 357 g-use-dma; 358 phys = <&u2phy_otg>; 359 phy-names = "usb2-phy"; 360 status = "disabled"; 361 }; 362 363 usb_host0_ehci: usb@ff440000 { 364 compatible = "generic-ehci"; 365 reg = <0x0 0xff440000 0x0 0x10000>; 366 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 368 <&u2phy>; 369 clock-names = "usbhost", "arbiter", "utmi"; 370 phys = <&u2phy_host>; 371 phy-names = "usb"; 372 status = "disabled"; 373 }; 374 375 usb_host0_ohci: usb@ff450000 { 376 compatible = "generic-ohci"; 377 reg = <0x0 0xff450000 0x0 0x10000>; 378 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 380 <&u2phy>; 381 clock-names = "usbhost", "arbiter", "utmi"; 382 phys = <&u2phy_host>; 383 phy-names = "usb"; 384 }; 385 386 sdmmc: dwmmc@ff480000 { 387 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 388 reg = <0x0 0xff480000 0x0 0x4000>; 389 max-frequency = <150000000>; 390 bus-width = <4>; 391 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 392 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 393 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 394 fifo-depth = <0x100>; 395 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 398 status = "disabled"; 399 }; 400 401 emmc: dwmmc@ff490000 { 402 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 403 reg = <0x0 0xff490000 0x0 0x4000>; 404 max-frequency = <150000000>; 405 bus-width = <8>; 406 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 407 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 408 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 409 fifo-depth = <0x100>; 410 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 411 status = "disabled"; 412 }; 413 414 sdio: dwmmc@ff4a0000 { 415 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 416 reg = <0x0 0xff4a0000 0x0 0x4000>; 417 max-frequency = <150000000>; 418 bus-width = <4>; 419 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 420 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 421 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 422 fifo-depth = <0x100>; 423 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 426 status = "disabled"; 427 }; 428 429 nandc: nandc@ff4b0000 { 430 compatible = "rockchip,rk-nandc"; 431 reg = <0x0 0xff4b0000 0x0 0x4000>; 432 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 433 nandc_id = <0>; 434 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 435 clock-names = "clk_nandc", "hclk_nandc"; 436 status = "disabled"; 437 }; 438 439 440 sfc: sfc@ff4c0000 { 441 compatible = "rockchip,rksfc"; 442 reg = <0x0 0xff4c0000 0x0 0x4000>; 443 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 445 clock-names = "clk_sfc", "hclk_sfc"; 446 status = "disabled"; 447 }; 448 449 cru: clock-controller@ff500000 { 450 compatible = "rockchip,rk3308-cru"; 451 reg = <0x0 0xff500000 0x0 0x1000>; 452 rockchip,grf = <&grf>; 453 #clock-cells = <1>; 454 #reset-cells = <1>; 455 }; 456 457 gic: interrupt-controller@ff580000 { 458 compatible = "arm,gic-400"; 459 #interrupt-cells = <3>; 460 #address-cells = <0>; 461 interrupt-controller; 462 463 reg = <0x0 0xff581000 0x0 0x1000>, 464 <0x0 0xff582000 0x0 0x2000>, 465 <0x0 0xff584000 0x0 0x2000>, 466 <0x0 0xff586000 0x0 0x2000>; 467 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 468 }; 469 470 pinctrl: pinctrl { 471 compatible = "rockchip,rk3308-pinctrl"; 472 rockchip,grf = <&grf>; 473 #address-cells = <2>; 474 #size-cells = <2>; 475 ranges; 476 477 gpio0: gpio0@ff220000 { 478 compatible = "rockchip,gpio-bank"; 479 reg = <0x0 0xff220000 0x0 0x100>; 480 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 481 //clocks = <&cru PCLK_GPIO0>; 482 clocks = <&xin24m>; 483 gpio-controller; 484 #gpio-cells = <2>; 485 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 }; 489 490 gpio1: gpio1@ff230000 { 491 compatible = "rockchip,gpio-bank"; 492 reg = <0x0 0xff230000 0x0 0x100>; 493 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 494 //clocks = <&cru PCLK_GPIO1>; 495 clocks = <&xin24m>; 496 gpio-controller; 497 #gpio-cells = <2>; 498 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 }; 502 503 gpio2: gpio2@ff240000 { 504 compatible = "rockchip,gpio-bank"; 505 reg = <0x0 0xff240000 0x0 0x100>; 506 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 507 //clocks = <&cru PCLK_GPIO2>; 508 clocks = <&xin24m>; 509 gpio-controller; 510 #gpio-cells = <2>; 511 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 }; 515 516 gpio3: gpio3@ff250000 { 517 compatible = "rockchip,gpio-bank"; 518 reg = <0x0 0xff250000 0x0 0x100>; 519 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 520 //clocks = <&cru PCLK_GPIO3>; 521 clocks = <&xin24m>; 522 gpio-controller; 523 #gpio-cells = <2>; 524 525 interrupt-controller; 526 #interrupt-cells = <2>; 527 }; 528 529 gpio4: gpio4@ff260000 { 530 compatible = "rockchip,gpio-bank"; 531 reg = <0x0 0xff260000 0x0 0x100>; 532 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 533 //clocks = <&cru PCLK_GPIO4>; 534 clocks = <&xin24m>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 538 interrupt-controller; 539 #interrupt-cells = <2>; 540 }; 541 542 pcfg_pull_up: pcfg-pull-up { 543 bias-pull-up; 544 }; 545 546 pcfg_pull_down: pcfg-pull-down { 547 bias-pull-down; 548 }; 549 550 pcfg_pull_none: pcfg-pull-none { 551 bias-disable; 552 }; 553 554 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 555 bias-disable; 556 drive-strength = <2>; 557 }; 558 559 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 560 bias-pull-up; 561 drive-strength = <2>; 562 }; 563 564 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 565 bias-pull-up; 566 drive-strength = <4>; 567 }; 568 569 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 570 bias-disable; 571 drive-strength = <4>; 572 }; 573 574 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 575 bias-pull-down; 576 drive-strength = <4>; 577 }; 578 579 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 580 bias-disable; 581 drive-strength = <8>; 582 }; 583 584 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 585 bias-pull-up; 586 drive-strength = <8>; 587 }; 588 589 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 590 bias-disable; 591 drive-strength = <12>; 592 }; 593 594 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 595 bias-pull-up; 596 drive-strength = <12>; 597 }; 598 599 pcfg_pull_none_smt: pcfg-pull-none-smt { 600 bias-disable; 601 input-schmitt-enable; 602 }; 603 604 pcfg_output_high: pcfg-output-high { 605 output-high; 606 }; 607 608 pcfg_output_low: pcfg-output-low { 609 output-low; 610 }; 611 612 pcfg_input_high: pcfg-input-high { 613 bias-pull-up; 614 input-enable; 615 }; 616 617 pcfg_input: pcfg-input { 618 input-enable; 619 }; 620 621 i2c0 { 622 i2c0_xfer: i2c0-xfer { 623 rockchip,pins = 624 <1 RK_PD0 2 &pcfg_pull_none_smt>, 625 <1 RK_PD1 2 &pcfg_pull_none_smt>; 626 }; 627 }; 628 629 i2c1 { 630 i2c1_xfer: i2c1-xfer { 631 rockchip,pins = 632 <0 RK_PB3 1 &pcfg_pull_none_smt>, 633 <0 RK_PB4 1 &pcfg_pull_none_smt>; 634 }; 635 }; 636 637 i2c2 { 638 i2c2_xfer: i2c2-xfer { 639 rockchip,pins = 640 <2 RK_PA2 3 &pcfg_pull_none_smt>, 641 <2 RK_PA3 3 &pcfg_pull_none_smt>; 642 }; 643 }; 644 645 i2c3-m0 { 646 i2c3m0_xfer: i2c3m0-xfer { 647 rockchip,pins = 648 <0 RK_PB7 2 &pcfg_pull_none_smt>, 649 <0 RK_PC0 2 &pcfg_pull_none_smt>; 650 }; 651 }; 652 653 i2c3-m1 { 654 i2c3m1_xfer: i2c3m1-xfer { 655 rockchip,pins = 656 <3 RK_PB4 2 &pcfg_pull_none_smt>, 657 <3 RK_PB5 2 &pcfg_pull_none_smt>; 658 }; 659 }; 660 661 tsadc { 662 tsadc_otp_gpio: tsadc-otp-gpio { 663 rockchip,pins = 664 <0 RK_PB2 0 &pcfg_pull_none>; 665 }; 666 667 tsadc_otp_out: tsadc-otp-out { 668 rockchip,pins = 669 <0 RK_PB2 1 &pcfg_pull_none>; 670 }; 671 }; 672 673 uart0 { 674 uart0_xfer: uart0-xfer { 675 rockchip,pins = 676 <2 RK_PA1 1 &pcfg_pull_up>, 677 <2 RK_PA0 1 &pcfg_pull_none>; 678 }; 679 680 uart0_cts: uart0-cts { 681 rockchip,pins = 682 <2 RK_PA2 1 &pcfg_pull_none>; 683 }; 684 685 uart0_rts: uart0-rts { 686 rockchip,pins = 687 <2 RK_PA3 1 &pcfg_pull_none>; 688 }; 689 }; 690 691 uart1 { 692 uart1_xfer: uart1-xfer { 693 rockchip,pins = 694 <1 RK_PD1 1 &pcfg_pull_up>, 695 <1 RK_PD0 1 &pcfg_pull_none>; 696 }; 697 698 uart1_cts: uart1-cts { 699 rockchip,pins = 700 <1 RK_PC6 1 &pcfg_pull_none>; 701 }; 702 703 uart1_rts: uart1-rts { 704 rockchip,pins = 705 <1 RK_PC7 1 &pcfg_pull_none>; 706 }; 707 }; 708 709 uart2-m0 { 710 uart2m0_xfer: uart2m0-xfer { 711 rockchip,pins = 712 <1 RK_PC7 2 &pcfg_pull_up>, 713 <1 RK_PC6 2 &pcfg_pull_none>; 714 }; 715 }; 716 717 uart2-m1 { 718 uart2m1_xfer: uart2m1-xfer { 719 rockchip,pins = 720 <4 RK_PD3 2 &pcfg_pull_up>, 721 <4 RK_PD2 2 &pcfg_pull_none>; 722 }; 723 }; 724 725 uart3 { 726 uart3_xfer: uart3-xfer { 727 rockchip,pins = 728 <3 RK_PB5 4 &pcfg_pull_up>, 729 <3 RK_PB4 4 &pcfg_pull_none>; 730 }; 731 }; 732 733 uart4 { 734 735 uart4_xfer: uart4-xfer { 736 rockchip,pins = 737 <4 RK_PB1 1 &pcfg_pull_up>, 738 <4 RK_PB0 1 &pcfg_pull_none>; 739 }; 740 741 uart4_cts: uart4-cts { 742 rockchip,pins = 743 <4 RK_PA6 1 &pcfg_pull_none>; 744 745 }; 746 747 uart4_rts: uart4-rts { 748 rockchip,pins = 749 <4 RK_PA7 1 &pcfg_pull_none>; 750 }; 751 }; 752 753 spi0 { 754 spi0_clk: spi0-clk { 755 rockchip,pins = 756 <2 RK_PA2 2 &pcfg_pull_up>; 757 }; 758 759 spi0_csn0: spi0-csn0 { 760 rockchip,pins = 761 <2 RK_PA3 2 &pcfg_pull_up>; 762 }; 763 764 spi0_miso: spi0-miso { 765 rockchip,pins = 766 <2 RK_PA0 2 &pcfg_pull_up>; 767 }; 768 769 spi0_mosi: spi0-mosi { 770 rockchip,pins = 771 <2 RK_PA1 2 &pcfg_pull_up>; 772 }; 773 }; 774 775 spi1 { 776 spi1_clk: spi1-clk { 777 rockchip,pins = 778 <3 RK_PB3 3 &pcfg_pull_up>; 779 }; 780 781 spi1_csn0: spi1-csn0 { 782 rockchip,pins = 783 <3 RK_PB5 3 &pcfg_pull_up>; 784 }; 785 786 spi1_miso: spi1-miso { 787 rockchip,pins = 788 <3 RK_PB2 3 &pcfg_pull_up>; 789 }; 790 791 spi1_mosi: spi1-mosi { 792 rockchip,pins = 793 <3 RK_PB4 3 &pcfg_pull_up>; 794 }; 795 }; 796 797 spi2 { 798 spi2_clk: spi2-clk { 799 rockchip,pins = 800 <1 RK_PD0 3 &pcfg_pull_up>; 801 }; 802 803 spi2_csn0: spi2-csn0 { 804 rockchip,pins = 805 <1 RK_PD1 3 &pcfg_pull_up>; 806 }; 807 808 spi2_miso: spi2-miso { 809 rockchip,pins = 810 <1 RK_PC6 3 &pcfg_pull_up>; 811 }; 812 813 spi2_mosi: spi2-mosi { 814 rockchip,pins = 815 <1 RK_PC7 3 &pcfg_pull_up>; 816 }; 817 }; 818 819 sdmmc { 820 sdmmc_clk: sdmmc-clk { 821 rockchip,pins = 822 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 823 }; 824 825 sdmmc_cmd: sdmmc-cmd { 826 rockchip,pins = 827 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 828 }; 829 830 sdmmc_pwren: sdmmc-pwren { 831 rockchip,pins = 832 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 833 }; 834 835 sdmmc_bus1: sdmmc-bus1 { 836 rockchip,pins = 837 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 838 }; 839 840 sdmmc_bus4: sdmmc-bus4 { 841 rockchip,pins = 842 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 843 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 844 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 845 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 846 }; 847 848 sdmmc_gpio: sdmmc-gpio { 849 rockchip,pins = 850 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 851 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 852 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 853 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 854 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 855 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 856 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 857 }; 858 }; 859 860 sdio { 861 sdio_clk: sdio-clk { 862 rockchip,pins = 863 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 864 }; 865 866 sdio_cmd: sdio-cmd { 867 rockchip,pins = 868 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 869 }; 870 871 sdio_pwren: sdio-pwren { 872 rockchip,pins = 873 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 874 }; 875 876 sdio_wrpt: sdio-wrpt { 877 rockchip,pins = 878 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 879 }; 880 881 sdio_intn: sdio-intn { 882 rockchip,pins = 883 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 884 }; 885 886 sdio_bus1: sdio-bus1 { 887 rockchip,pins = 888 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 889 }; 890 891 sdio_bus4: sdio-bus4 { 892 rockchip,pins = 893 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 894 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 895 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 896 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 897 }; 898 899 sdio_gpio: sdio-gpio { 900 rockchip,pins = 901 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 902 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 903 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 904 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 905 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 906 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 907 }; 908 }; 909 910 emmc { 911 emmc_clk: emmc-clk { 912 rockchip,pins = 913 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 914 }; 915 916 emmc_cmd: emmc-cmd { 917 rockchip,pins = 918 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 919 }; 920 921 emmc_pwren: emmc-pwren { 922 rockchip,pins = 923 <3 RK_PB3 2 &pcfg_pull_none>; 924 }; 925 926 emmc_rstn: emmc-rstn { 927 rockchip,pins = 928 <3 RK_PB2 2 &pcfg_pull_none>; 929 }; 930 931 emmc_bus1: emmc-bus1 { 932 rockchip,pins = 933 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 934 }; 935 936 emmc_bus4: emmc-bus4 { 937 rockchip,pins = 938 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 939 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 940 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 941 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 942 }; 943 944 emmc_bus8: emmc-bus8 { 945 rockchip,pins = 946 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 947 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 948 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 949 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 950 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 951 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 952 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 953 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 954 }; 955 }; 956 957 flash { 958 flash_csn0: flash-csn0 { 959 rockchip,pins = 960 <3 RK_PB5 1 &pcfg_pull_none>; 961 }; 962 963 flash_rdy: flash-rdy { 964 rockchip,pins = 965 <3 RK_PB4 1 &pcfg_pull_none>; 966 }; 967 968 flash_ale: flash-ale { 969 rockchip,pins = 970 <3 RK_PB3 1 &pcfg_pull_none>; 971 }; 972 973 flash_cle: flash-cle { 974 rockchip,pins = 975 <3 RK_PB1 1 &pcfg_pull_none>; 976 }; 977 978 flash_wrn: flash-wrn { 979 rockchip,pins = 980 <3 RK_PB0 1 &pcfg_pull_none>; 981 }; 982 983 flash_rdn: flash-rdn { 984 rockchip,pins = 985 <3 RK_PB2 1 &pcfg_pull_none>; 986 }; 987 988 flash_bus8: flash-bus8 { 989 rockchip,pins = 990 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 991 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 992 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 993 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 994 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 995 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 996 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 997 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 998 }; 999 }; 1000 1001 pwm0 { 1002 pwm0_pin: pwm0-pin { 1003 rockchip,pins = 1004 <0 RK_PB5 1 &pcfg_pull_none>; 1005 }; 1006 }; 1007 1008 pwm1 { 1009 pwm1_pin: pwm1-pin { 1010 rockchip,pins = 1011 <0 RK_PB6 1 &pcfg_pull_none>; 1012 }; 1013 }; 1014 1015 pwm2 { 1016 pwm2_pin: pwm2-pin { 1017 rockchip,pins = 1018 <0 RK_PB7 1 &pcfg_pull_none>; 1019 }; 1020 }; 1021 1022 pwm3 { 1023 pwm3_pin: pwm3-pin { 1024 rockchip,pins = 1025 <0 RK_PC0 1 &pcfg_pull_none>; 1026 }; 1027 }; 1028 1029 gmac { 1030 rmii_pins: rmii-pins { 1031 rockchip,pins = 1032 /* mac_txen */ 1033 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1034 /* mac_txd1 */ 1035 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1036 /* mac_txd0 */ 1037 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1038 /* mac_rxd0 */ 1039 <1 RK_PC4 3 &pcfg_pull_none>, 1040 /* mac_rxd1 */ 1041 <1 RK_PC5 3 &pcfg_pull_none>, 1042 /* mac_rxer */ 1043 <1 RK_PB7 3 &pcfg_pull_none>, 1044 /* mac_rxdv */ 1045 <1 RK_PC0 3 &pcfg_pull_none>, 1046 /* mac_mdio */ 1047 <1 RK_PB6 3 &pcfg_pull_none>, 1048 /* mac_mdc */ 1049 <1 RK_PB5 3 &pcfg_pull_none>, 1050 /* mac_clk */ 1051 <1 RK_PB4 3 &pcfg_pull_none>; 1052 }; 1053 }; 1054 1055 lcdc { 1056 lcdc_ctl: lcdc-ctl { 1057 rockchip,pins = 1058 /* dclk */ 1059 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1060 /* hsync */ 1061 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1062 /* vsync */ 1063 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1064 /* den */ 1065 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1066 /* d0 */ 1067 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1068 /* d1 */ 1069 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1070 /* d2 */ 1071 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1072 /* d3 */ 1073 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1074 /* d4 */ 1075 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1076 /* d5 */ 1077 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1078 /* d6 */ 1079 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1080 /* d7 */ 1081 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1082 /* d8 */ 1083 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1084 /* d9 */ 1085 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1086 /* d10 */ 1087 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1088 /* d11 */ 1089 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1090 /* d12 */ 1091 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1092 /* d13 */ 1093 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1094 /* d14 */ 1095 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1096 /* d15 */ 1097 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1098 /* d16 */ 1099 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1100 /* d17 */ 1101 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1102 }; 1103 }; 1104 }; 1105}; 1106
