xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3308-u-boot.dtsi (revision e55dfbd47140353ad2ac122e706d44b699c8162a) 
1/*
2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &emmc;
10		mmc1 = &sdmmc;
11	};
12
13	chosen {
14		stdout-path = &uart2;
15		u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
16	};
17};
18
19&psci {
20	u-boot,dm-pre-reloc;
21	status = "okay";
22};
23
24&dmc {
25	u-boot,dm-pre-reloc;
26};
27
28&cru {
29	u-boot,dm-pre-reloc;
30};
31
32&emmc {
33	u-boot,dm-pre-reloc;
34};
35
36&grf {
37	u-boot,dm-pre-reloc;
38};
39
40&nandc {
41	u-boot,dm-pre-reloc;
42	status = "okay";
43	#address-cells = <1>;
44	#size-cells = <0>;
45
46	nand@0 {
47		u-boot,dm-spl;
48		reg = <0>;
49		nand-ecc-mode = "hw";
50		nand-ecc-strength = <16>;
51		nand-ecc-step-size = <1024>;
52	};
53};
54
55&pinctrl {
56	u-boot,dm-pre-reloc;
57};
58
59&pcfg_pull_none_4ma {
60	u-boot,dm-spl;
61};
62
63&pcfg_pull_up_4ma {
64	u-boot,dm-spl;
65};
66
67&sdmmc {
68	u-boot,dm-pre-reloc;
69};
70
71&sdmmc_pin {
72	u-boot,dm-spl;
73};
74
75&sdmmc_clk {
76	u-boot,dm-spl;
77};
78
79&sdmmc_cmd {
80	u-boot,dm-spl;
81};
82
83&sdmmc_bus4 {
84	u-boot,dm-spl;
85};
86
87&sdmmc_pwren {
88	u-boot,dm-spl;
89};
90
91&sfc {
92	u-boot,dm-pre-reloc;
93	status = "okay";
94
95	#address-cells = <1>;
96	#size-cells = <0>;
97	spi_nand: flash@0 {
98		u-boot,dm-spl;
99		compatible = "spi-nand";
100		reg = <0>;
101		spi-tx-bus-width = <1>;
102		spi-rx-bus-width = <4>;
103		spi-max-frequency = <96000000>;
104	};
105	spi_nor: flash@1 {
106		u-boot,dm-spl;
107		compatible = "jedec,spi-nor";
108		label = "sfc_nor";
109		reg = <0>;
110		spi-tx-bus-width = <1>;
111		spi-rx-bus-width = <4>;
112		spi-max-frequency = <96000000>;
113	};
114};
115
116&crypto {
117	u-boot,dm-pre-reloc;
118	status = "okay";
119};
120
121&saradc {
122	u-boot,dm-pre-reloc;
123	status = "okay";
124};
125
126&secure_otp {
127	u-boot,dm-pre-reloc;
128};
129
130&uart0 {
131	u-boot,dm-pre-reloc;
132};
133
134&uart1 {
135	u-boot,dm-pre-reloc;
136};
137
138&uart2 {
139	u-boot,dm-pre-reloc;
140	clock-frequency = <24000000>;
141	status = "okay";
142};
143
144&uart3 {
145	u-boot,dm-pre-reloc;
146};
147
148&uart4 {
149	u-boot,dm-pre-reloc;
150};
151
152&usb2phy_grf {
153	u-boot,dm-pre-reloc;
154};
155
156&u2phy {
157	u-boot,dm-pre-reloc;
158	status = "okay";
159};
160
161&u2phy_otg {
162	u-boot,dm-pre-reloc;
163	status = "okay";
164};
165
166&usb20_otg {
167	u-boot,dm-pre-reloc;
168	status = "okay";
169};
170
171&route_rgb {
172	status = "disabled";
173};
174