1/* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 9 chosen { 10 stdout-path = &uart2; 11 u-boot,spl-boot-order = &sfc, &nandc, &emmc; 12 }; 13}; 14 15&dmc { 16 u-boot,dm-pre-reloc; 17}; 18 19&cru { 20 u-boot,dm-pre-reloc; 21}; 22 23&emmc { 24 u-boot,dm-pre-reloc; 25}; 26 27&grf { 28 u-boot,dm-pre-reloc; 29}; 30 31&nandc { 32 u-boot,dm-pre-reloc; 33 status = "okay"; 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 nand@0 { 38 u-boot,dm-spl; 39 reg = <0>; 40 nand-ecc-mode = "hw_syndrome"; 41 nand-ecc-strength = <16>; 42 nand-ecc-step-size = <1024>; 43 }; 44}; 45 46&sfc { 47 u-boot,dm-pre-reloc; 48 status = "okay"; 49 50 #address-cells = <1>; 51 #size-cells = <0>; 52 flash@0 { 53 u-boot,dm-spl; 54 compatible = "spi-nand"; 55 reg = <0>; 56 spi-tx-bus-width = <1>; 57 spi-rx-bus-width = <4>; 58 spi-max-frequency = <96000000>; 59 }; 60}; 61 62&crypto { 63 u-boot,dm-pre-reloc; 64 status = "okay"; 65}; 66 67&saradc { 68 u-boot,dm-pre-reloc; 69 status = "okay"; 70}; 71 72&secure_otp { 73 u-boot,dm-pre-reloc; 74}; 75 76&uart0 { 77 u-boot,dm-pre-reloc; 78}; 79 80&uart1 { 81 u-boot,dm-pre-reloc; 82}; 83 84&uart2 { 85 u-boot,dm-pre-reloc; 86 clock-frequency = <24000000>; 87 status = "okay"; 88}; 89 90&uart3 { 91 u-boot,dm-pre-reloc; 92}; 93 94&uart4 { 95 u-boot,dm-pre-reloc; 96}; 97 98&usb2phy_grf { 99 u-boot,dm-pre-reloc; 100}; 101 102&u2phy { 103 u-boot,dm-pre-reloc; 104 status = "okay"; 105}; 106 107&u2phy_otg { 108 u-boot,dm-pre-reloc; 109 status = "okay"; 110}; 111 112&usb20_otg { 113 u-boot,dm-pre-reloc; 114 status = "okay"; 115}; 116 117&route_rgb { 118 status = "disabled"; 119}; 120