xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3308-u-boot.dtsi (revision 5e8564cf419797f9095431e6eb6f0c00dfa423d2) 
1/*
2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8
9	chosen {
10		stdout-path = &uart2;
11		u-boot,spl-boot-order = &nandc, &emmc;
12	};
13};
14
15&dmc {
16	u-boot,dm-pre-reloc;
17};
18
19&cru {
20	u-boot,dm-pre-reloc;
21};
22
23&emmc {
24	u-boot,dm-pre-reloc;
25};
26
27&grf {
28	u-boot,dm-pre-reloc;
29};
30
31&nandc {
32	u-boot,dm-pre-reloc;
33	status = "okay";
34	#address-cells = <1>;
35	#size-cells = <0>;
36
37	nand@0 {
38		u-boot,dm-spl;
39		reg = <0>;
40		nand-ecc-mode = "hw_syndrome";
41		nand-ecc-strength = <16>;
42		nand-ecc-step-size = <1024>;
43	};
44};
45
46&sfc {
47	u-boot,dm-pre-reloc;
48	status = "okay";
49};
50
51&saradc {
52	u-boot,dm-pre-reloc;
53	status = "okay";
54};
55
56&uart0 {
57	u-boot,dm-pre-reloc;
58};
59
60&uart1 {
61	u-boot,dm-pre-reloc;
62};
63
64&uart2 {
65	u-boot,dm-pre-reloc;
66	clock-frequency = <24000000>;
67	status = "okay";
68};
69
70&uart3 {
71	u-boot,dm-pre-reloc;
72};
73
74&uart4 {
75	u-boot,dm-pre-reloc;
76};
77
78&usb2phy_grf {
79	u-boot,dm-pre-reloc;
80};
81
82&u2phy {
83	u-boot,dm-pre-reloc;
84	status = "okay";
85};
86
87&u2phy_otg {
88	u-boot,dm-pre-reloc;
89	status = "okay";
90};
91
92&usb20_otg {
93	u-boot,dm-pre-reloc;
94	status = "okay";
95};
96
97&route_rgb {
98	status = "disabled";
99};
100