xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3308-u-boot.dtsi (revision 8ef348381ab31740b0d14330f6ba71a2f8adba15)
1ff6f33d0SJoseph Chen/*
2ff6f33d0SJoseph Chen * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3ff6f33d0SJoseph Chen *
4ff6f33d0SJoseph Chen * SPDX-License-Identifier:     GPL-2.0+
5ff6f33d0SJoseph Chen */
6ff6f33d0SJoseph Chen
7ff6f33d0SJoseph Chen/ {
8fccb2c59SKever Yang	aliases {
9fccb2c59SKever Yang		mmc0 = &emmc;
10fccb2c59SKever Yang		mmc1 = &sdmmc;
11fccb2c59SKever Yang	};
12ff6f33d0SJoseph Chen
13ff6f33d0SJoseph Chen	chosen {
14ff6f33d0SJoseph Chen		stdout-path = &uart2;
15cddfd2aeSJon Lin		u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
16ff6f33d0SJoseph Chen	};
17*8ef34838SXuhui Lin
18*8ef34838SXuhui Lin	secure-otp@ff2a8000 {
19*8ef34838SXuhui Lin		compatible = "rockchip,rk3308-secure-otp";
20*8ef34838SXuhui Lin		reg = <0x0 0xff2a8000 0x0 0x4000>;
21*8ef34838SXuhui Lin		secure_conf = <0xff2b0004>;
22*8ef34838SXuhui Lin		mask_addr = <0xff540000>;
23*8ef34838SXuhui Lin		u-boot,dm-pre-reloc;
24*8ef34838SXuhui Lin	};
25ff6f33d0SJoseph Chen};
26ff6f33d0SJoseph Chen
27fbf3603bSJoseph Chen&psci {
28fbf3603bSJoseph Chen	u-boot,dm-pre-reloc;
29fbf3603bSJoseph Chen	status = "okay";
30fbf3603bSJoseph Chen};
31fbf3603bSJoseph Chen
32ff6f33d0SJoseph Chen&dmc {
33ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
34ff6f33d0SJoseph Chen};
35ff6f33d0SJoseph Chen
36ff6f33d0SJoseph Chen&cru {
37ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
38ff6f33d0SJoseph Chen};
39ff6f33d0SJoseph Chen
40ff6f33d0SJoseph Chen&emmc {
41ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
42ff6f33d0SJoseph Chen};
43ff6f33d0SJoseph Chen
44ff6f33d0SJoseph Chen&grf {
45ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
46ff6f33d0SJoseph Chen};
47ff6f33d0SJoseph Chen
48ff6f33d0SJoseph Chen&nandc {
49ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
50ff6f33d0SJoseph Chen	status = "okay";
51139d645eSJason Zhu	#address-cells = <1>;
52139d645eSJason Zhu	#size-cells = <0>;
53139d645eSJason Zhu
543bce84dbSYifeng Zhao	nand@0 {
553bce84dbSYifeng Zhao		u-boot,dm-spl;
563bce84dbSYifeng Zhao		reg = <0>;
5745895bf4SJon Lin		nand-ecc-mode = "hw";
583bce84dbSYifeng Zhao		nand-ecc-strength = <16>;
593bce84dbSYifeng Zhao		nand-ecc-step-size = <1024>;
603bce84dbSYifeng Zhao	};
61ff6f33d0SJoseph Chen};
62ff6f33d0SJoseph Chen
63a9bb1266SJason Zhu&pinctrl {
64a9bb1266SJason Zhu	u-boot,dm-pre-reloc;
65a9bb1266SJason Zhu};
66a9bb1266SJason Zhu
67a9bb1266SJason Zhu&pcfg_pull_none_4ma {
68a9bb1266SJason Zhu	u-boot,dm-spl;
69a9bb1266SJason Zhu};
70a9bb1266SJason Zhu
71a9bb1266SJason Zhu&pcfg_pull_up_4ma {
72a9bb1266SJason Zhu	u-boot,dm-spl;
73a9bb1266SJason Zhu};
74a9bb1266SJason Zhu
75a9bb1266SJason Zhu&sdmmc {
76a9bb1266SJason Zhu	u-boot,dm-pre-reloc;
77a9bb1266SJason Zhu};
78a9bb1266SJason Zhu
79a9bb1266SJason Zhu&sdmmc_pin {
80a9bb1266SJason Zhu	u-boot,dm-spl;
81a9bb1266SJason Zhu};
82a9bb1266SJason Zhu
83a9bb1266SJason Zhu&sdmmc_clk {
84a9bb1266SJason Zhu	u-boot,dm-spl;
85a9bb1266SJason Zhu};
86a9bb1266SJason Zhu
87a9bb1266SJason Zhu&sdmmc_cmd {
88a9bb1266SJason Zhu	u-boot,dm-spl;
89a9bb1266SJason Zhu};
90a9bb1266SJason Zhu
91a9bb1266SJason Zhu&sdmmc_bus4 {
92a9bb1266SJason Zhu	u-boot,dm-spl;
93a9bb1266SJason Zhu};
94a9bb1266SJason Zhu
95a9bb1266SJason Zhu&sdmmc_pwren {
96a9bb1266SJason Zhu	u-boot,dm-spl;
97a9bb1266SJason Zhu};
98a9bb1266SJason Zhu
99ff6f33d0SJoseph Chen&sfc {
100ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
101ff6f33d0SJoseph Chen	status = "okay";
1028f5984c0SJason Zhu
1038f5984c0SJason Zhu	#address-cells = <1>;
1048f5984c0SJason Zhu	#size-cells = <0>;
105cddfd2aeSJon Lin	spi_nand: flash@0 {
1068f5984c0SJason Zhu		u-boot,dm-spl;
1078f5984c0SJason Zhu		compatible = "spi-nand";
1088f5984c0SJason Zhu		reg = <0>;
1098f5984c0SJason Zhu		spi-tx-bus-width = <1>;
1108f5984c0SJason Zhu		spi-rx-bus-width = <4>;
1118f5984c0SJason Zhu		spi-max-frequency = <96000000>;
1128f5984c0SJason Zhu	};
113cddfd2aeSJon Lin	spi_nor: flash@1 {
114cddfd2aeSJon Lin		u-boot,dm-spl;
115cddfd2aeSJon Lin		compatible = "jedec,spi-nor";
116572e331bSJon Lin		label = "sfc_nor";
117cddfd2aeSJon Lin		reg = <0>;
118cddfd2aeSJon Lin		spi-tx-bus-width = <1>;
119cddfd2aeSJon Lin		spi-rx-bus-width = <4>;
120cddfd2aeSJon Lin		spi-max-frequency = <96000000>;
121cddfd2aeSJon Lin	};
122ff6f33d0SJoseph Chen};
123ff6f33d0SJoseph Chen
124394f2cffSLin Jinhan&crypto {
125394f2cffSLin Jinhan	u-boot,dm-pre-reloc;
126394f2cffSLin Jinhan	status = "okay";
127394f2cffSLin Jinhan};
128394f2cffSLin Jinhan
129ff6f33d0SJoseph Chen&saradc {
130ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
131ff6f33d0SJoseph Chen	status = "okay";
132ff6f33d0SJoseph Chen};
133ff6f33d0SJoseph Chen
134ff6f33d0SJoseph Chen&uart0 {
135ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
136ff6f33d0SJoseph Chen};
137ff6f33d0SJoseph Chen
138ff6f33d0SJoseph Chen&uart1 {
139ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
140ff6f33d0SJoseph Chen};
141ff6f33d0SJoseph Chen
142ff6f33d0SJoseph Chen&uart2 {
143ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
144ff6f33d0SJoseph Chen	clock-frequency = <24000000>;
145ff6f33d0SJoseph Chen	status = "okay";
146ff6f33d0SJoseph Chen};
147ff6f33d0SJoseph Chen
148ff6f33d0SJoseph Chen&uart3 {
149ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
150ff6f33d0SJoseph Chen};
151ff6f33d0SJoseph Chen
152ff6f33d0SJoseph Chen&uart4 {
153ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
154ff6f33d0SJoseph Chen};
155ff6f33d0SJoseph Chen
156ff6f33d0SJoseph Chen&usb2phy_grf {
157ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
158ff6f33d0SJoseph Chen};
159ff6f33d0SJoseph Chen
160ff6f33d0SJoseph Chen&u2phy {
161ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
162ff6f33d0SJoseph Chen	status = "okay";
163ff6f33d0SJoseph Chen};
164ff6f33d0SJoseph Chen
165ff6f33d0SJoseph Chen&u2phy_otg {
166ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
167ff6f33d0SJoseph Chen	status = "okay";
168ff6f33d0SJoseph Chen};
169ff6f33d0SJoseph Chen
170ff6f33d0SJoseph Chen&usb20_otg {
171ff6f33d0SJoseph Chen	u-boot,dm-pre-reloc;
172ff6f33d0SJoseph Chen	status = "okay";
173ff6f33d0SJoseph Chen};
174ff6f33d0SJoseph Chen
175ff6f33d0SJoseph Chen&route_rgb {
176ff6f33d0SJoseph Chen	status = "disabled";
177ff6f33d0SJoseph Chen};
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