1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3288-cru.h> 10#include <dt-bindings/power-domain/rk3288.h> 11#include <dt-bindings/thermal/thermal.h> 12#include <dt-bindings/video/rk3288.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 gpio4 = &gpio4; 25 gpio5 = &gpio5; 26 gpio6 = &gpio6; 27 gpio7 = &gpio7; 28 gpio8 = &gpio8; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 mmc2 = &sdio0; 38 mmc3 = &sdio1; 39 mshc0 = &emmc; 40 mshc1 = &sdmmc; 41 mshc2 = &sdio0; 42 mshc3 = &sdio1; 43 serial0 = &uart0; 44 serial1 = &uart1; 45 serial2 = &uart2; 46 serial3 = &uart3; 47 serial4 = &uart4; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 enable-method = "rockchip,rk3066-smp"; 57 rockchip,pmu = <&pmu>; 58 59 cpu0: cpu@500 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a12"; 62 reg = <0x500>; 63 operating-points = < 64 /* KHz uV */ 65 1800000 1400000 66 1704000 1350000 67 1608000 1300000 68 1512000 1250000 69 1416000 1200000 70 1200000 1100000 71 1008000 1050000 72 816000 1000000 73 696000 950000 74 600000 900000 75 408000 900000 76 216000 900000 77 126000 900000 78 >; 79 #cooling-cells = <2>; /* min followed by max */ 80 clock-latency = <40000>; 81 clocks = <&cru ARMCLK>; 82 resets = <&cru SRST_CORE0>; 83 }; 84 cpu@501 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a12"; 87 reg = <0x501>; 88 resets = <&cru SRST_CORE1>; 89 }; 90 cpu@502 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a12"; 93 reg = <0x502>; 94 resets = <&cru SRST_CORE2>; 95 }; 96 cpu@503 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a12"; 99 reg = <0x503>; 100 resets = <&cru SRST_CORE3>; 101 }; 102 }; 103 104 amba { 105 compatible = "arm,amba-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 dmac_peri: dma-controller@ff250000 { 111 compatible = "arm,pl330", "arm,primecell"; 112 broken-no-flushp; 113 reg = <0xff250000 0x4000>; 114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 116 #dma-cells = <1>; 117 clocks = <&cru ACLK_DMAC2>; 118 clock-names = "apb_pclk"; 119 }; 120 121 dmac_bus_ns: dma-controller@ff600000 { 122 compatible = "arm,pl330", "arm,primecell"; 123 broken-no-flushp; 124 reg = <0xff600000 0x4000>; 125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 127 #dma-cells = <1>; 128 clocks = <&cru ACLK_DMAC1>; 129 clock-names = "apb_pclk"; 130 status = "disabled"; 131 }; 132 133 dmac_bus_s: dma-controller@ffb20000 { 134 compatible = "arm,pl330", "arm,primecell"; 135 broken-no-flushp; 136 reg = <0xffb20000 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 #dma-cells = <1>; 140 clocks = <&cru ACLK_DMAC1>; 141 clock-names = "apb_pclk"; 142 }; 143 }; 144 145 xin24m: oscillator { 146 compatible = "fixed-clock"; 147 clock-frequency = <24000000>; 148 clock-output-names = "xin24m"; 149 #clock-cells = <0>; 150 }; 151 152 timer { 153 arm,use-physical-timer; 154 compatible = "arm,armv7-timer"; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 159 clock-frequency = <24000000>; 160 always-on; 161 }; 162 163 display_subsystem: display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopl_out>, <&vopb_out>; 166 status = "disabled"; 167 168 route { 169 route_hdmi: route-hdmi { 170 status = "disabled"; 171 logo,uboot = "logo.bmp"; 172 logo,kernel = "logo_kernel.bmp"; 173 logo,mode = "center"; 174 charge_logo,mode = "center"; 175 connect = <&vopb_out_hdmi>; 176 }; 177 178 route_edp: route-edp { 179 status = "disabled"; 180 logo,uboot = "logo.bmp"; 181 logo,kernel = "logo_kernel.bmp"; 182 logo,mode = "center"; 183 charge_logo,mode = "center"; 184 connect = <&vopl_out_edp>; 185 }; 186 187 route_dsi0: route-dsi0 { 188 status = "disabled"; 189 logo,uboot = "logo.bmp"; 190 logo,kernel = "logo_kernel.bmp"; 191 logo,mode = "center"; 192 charge_logo,mode = "center"; 193 connect = <&vopl_out_dsi0>; 194 }; 195 196 route_lvds: route-lvds { 197 status = "disabled"; 198 logo,uboot = "logo.bmp"; 199 logo,kernel = "logo_kernel.bmp"; 200 logo,mode = "center"; 201 charge_logo,mode = "center"; 202 connect = <&vopl_out_lvds>; 203 }; 204 }; 205 }; 206 207 sdmmc: dwmmc@ff0c0000 { 208 compatible = "rockchip,rk3288-dw-mshc"; 209 max-frequency = <150000000>; 210 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 211 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 212 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 213 fifo-depth = <0x100>; 214 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 215 reg = <0xff0c0000 0x4000>; 216 status = "disabled"; 217 }; 218 219 sdio0: dwmmc@ff0d0000 { 220 compatible = "rockchip,rk3288-dw-mshc"; 221 max-frequency = <150000000>; 222 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 223 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 224 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 225 fifo-depth = <0x100>; 226 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 227 reg = <0xff0d0000 0x4000>; 228 status = "disabled"; 229 }; 230 231 sdio1: dwmmc@ff0e0000 { 232 compatible = "rockchip,rk3288-dw-mshc"; 233 max-frequency = <150000000>; 234 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 235 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 236 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 237 fifo-depth = <0x100>; 238 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 239 reg = <0xff0e0000 0x4000>; 240 status = "disabled"; 241 }; 242 243 emmc: dwmmc@ff0f0000 { 244 compatible = "rockchip,rk3288-dw-mshc"; 245 max-frequency = <150000000>; 246 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 247 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 248 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 249 fifo-depth = <0x100>; 250 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 251 reg = <0xff0f0000 0x4000>; 252 status = "disabled"; 253 }; 254 255 saradc: saradc@ff100000 { 256 compatible = "rockchip,saradc"; 257 reg = <0xff100000 0x100>; 258 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 259 #io-channel-cells = <1>; 260 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 261 clock-names = "saradc", "apb_pclk"; 262 status = "disabled"; 263 }; 264 265 spi0: spi@ff110000 { 266 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 267 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 268 clock-names = "spiclk", "apb_pclk"; 269 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 270 dma-names = "tx", "rx"; 271 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 274 reg = <0xff110000 0x1000>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 status = "disabled"; 278 }; 279 280 spi1: spi@ff120000 { 281 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 282 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 283 clock-names = "spiclk", "apb_pclk"; 284 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 285 dma-names = "tx", "rx"; 286 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 289 reg = <0xff120000 0x1000>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 status = "disabled"; 293 }; 294 295 spi2: spi@ff130000 { 296 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 297 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 298 clock-names = "spiclk", "apb_pclk"; 299 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 300 dma-names = "tx", "rx"; 301 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 304 reg = <0xff130000 0x1000>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 status = "disabled"; 308 }; 309 310 i2c1: i2c@ff140000 { 311 compatible = "rockchip,rk3288-i2c"; 312 reg = <0xff140000 0x1000>; 313 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 clock-names = "i2c"; 317 clocks = <&cru PCLK_I2C1>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&i2c1_xfer>; 320 status = "disabled"; 321 }; 322 323 i2c3: i2c@ff150000 { 324 compatible = "rockchip,rk3288-i2c"; 325 reg = <0xff150000 0x1000>; 326 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 clock-names = "i2c"; 330 clocks = <&cru PCLK_I2C3>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&i2c3_xfer>; 333 status = "disabled"; 334 }; 335 336 i2c4: i2c@ff160000 { 337 compatible = "rockchip,rk3288-i2c"; 338 reg = <0xff160000 0x1000>; 339 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 clock-names = "i2c"; 343 clocks = <&cru PCLK_I2C4>; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&i2c4_xfer>; 346 status = "disabled"; 347 }; 348 349 i2c5: i2c@ff170000 { 350 compatible = "rockchip,rk3288-i2c"; 351 reg = <0xff170000 0x1000>; 352 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 clock-names = "i2c"; 356 clocks = <&cru PCLK_I2C5>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&i2c5_xfer>; 359 status = "disabled"; 360 }; 361 362 uart0: serial@ff180000 { 363 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 364 reg = <0xff180000 0x100>; 365 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 366 reg-shift = <2>; 367 reg-io-width = <4>; 368 clock-frequency = <24000000>; 369 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 370 clock-names = "baudclk", "apb_pclk"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&uart0_xfer>; 373 status = "disabled"; 374 }; 375 376 uart1: serial@ff190000 { 377 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 378 reg = <0xff190000 0x100>; 379 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 380 reg-shift = <2>; 381 reg-io-width = <4>; 382 clock-frequency = <24000000>; 383 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 384 clock-names = "baudclk", "apb_pclk"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&uart1_xfer>; 387 status = "disabled"; 388 }; 389 390 uart2: serial@ff690000 { 391 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 392 reg = <0xff690000 0x100>; 393 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 394 reg-shift = <2>; 395 reg-io-width = <4>; 396 clock-frequency = <24000000>; 397 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 398 clock-names = "baudclk", "apb_pclk"; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&uart2_xfer>; 401 status = "disabled"; 402 }; 403 uart3: serial@ff1b0000 { 404 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 405 reg = <0xff1b0000 0x100>; 406 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 407 reg-shift = <2>; 408 reg-io-width = <4>; 409 clock-frequency = <24000000>; 410 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 411 clock-names = "baudclk", "apb_pclk"; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&uart3_xfer>; 414 status = "disabled"; 415 }; 416 417 uart4: serial@ff1c0000 { 418 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 419 reg = <0xff1c0000 0x100>; 420 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 421 reg-shift = <2>; 422 reg-io-width = <4>; 423 clock-frequency = <24000000>; 424 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 425 clock-names = "baudclk", "apb_pclk"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&uart4_xfer>; 428 status = "disabled"; 429 }; 430 431 thermal: thermal-zones { 432 #include "rk3288-thermal.dtsi" 433 }; 434 435 tsadc: tsadc@ff280000 { 436 compatible = "rockchip,rk3288-tsadc"; 437 reg = <0xff280000 0x100>; 438 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 440 clock-names = "tsadc", "apb_pclk"; 441 resets = <&cru SRST_TSADC>; 442 reset-names = "tsadc-apb"; 443 pinctrl-names = "otp_out"; 444 pinctrl-0 = <&otp_out>; 445 #thermal-sensor-cells = <1>; 446 hw-shut-temp = <125000>; 447 status = "disabled"; 448 }; 449 450 gmac: ethernet@ff290000 { 451 compatible = "rockchip,rk3288-gmac"; 452 reg = <0xff290000 0x10000>; 453 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "macirq"; 455 rockchip,grf = <&grf>; 456 clocks = <&cru SCLK_MAC>, 457 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 458 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 459 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 460 clock-names = "stmmaceth", 461 "mac_clk_rx", "mac_clk_tx", 462 "clk_mac_ref", "clk_mac_refout", 463 "aclk_mac", "pclk_mac"; 464 }; 465 466 usb_host0_ehci: usb@ff500000 { 467 compatible = "generic-ehci"; 468 reg = <0xff500000 0x100>; 469 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cru HCLK_USBHOST0>; 471 clock-names = "usbhost"; 472 phys = <&usbphy1>; 473 phy-names = "usb"; 474 status = "disabled"; 475 }; 476 477 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 478 479 usb_host1: usb@ff540000 { 480 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 481 "snps,dwc2"; 482 reg = <0xff540000 0x40000>; 483 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&cru HCLK_USBHOST1>; 485 clock-names = "otg"; 486 phys = <&usbphy2>; 487 phy-names = "usb2-phy"; 488 status = "disabled"; 489 }; 490 491 usb_otg: usb@ff580000 { 492 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 493 "snps,dwc2"; 494 reg = <0xff580000 0x40000>; 495 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&cru HCLK_OTG0>; 497 clock-names = "otg"; 498 dr_mode = "otg"; 499 phys = <&usbphy0>; 500 phy-names = "usb2-phy"; 501 status = "disabled"; 502 }; 503 504 usb_hsic: usb@ff5c0000 { 505 compatible = "generic-ehci"; 506 reg = <0xff5c0000 0x100>; 507 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&cru HCLK_HSIC>; 509 clock-names = "usbhost"; 510 status = "disabled"; 511 }; 512 513 dmc: dmc@ff610000 { 514 compatible = "rockchip,rk3288-dmc", "syscon"; 515 rockchip,cru = <&cru>; 516 rockchip,grf = <&grf>; 517 rockchip,pmu = <&pmu>; 518 rockchip,sgrf = <&sgrf>; 519 rockchip,noc = <&noc>; 520 reg = <0xff610000 0x3fc 521 0xff620000 0x294 522 0xff630000 0x3fc 523 0xff640000 0x294>; 524 rockchip,sram = <&ddr_sram>; 525 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, 526 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, 527 <&cru ARMCLK>; 528 clock-names = "pclk_ddrupctl0", "pclk_publ0", 529 "pclk_ddrupctl1", "pclk_publ1", 530 "arm_clk"; 531 }; 532 533 i2c0: i2c@ff650000 { 534 compatible = "rockchip,rk3288-i2c"; 535 reg = <0xff650000 0x1000>; 536 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 clock-names = "i2c"; 540 clocks = <&cru PCLK_I2C0>; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&i2c0_xfer>; 543 status = "disabled"; 544 }; 545 546 i2c2: i2c@ff660000 { 547 compatible = "rockchip,rk3288-i2c"; 548 reg = <0xff660000 0x1000>; 549 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 clock-names = "i2c"; 553 clocks = <&cru PCLK_I2C2>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c2_xfer>; 556 status = "disabled"; 557 }; 558 559 pwm0: pwm@ff680000 { 560 compatible = "rockchip,rk3288-pwm"; 561 reg = <0xff680000 0x10>; 562 #pwm-cells = <3>; 563 pinctrl-names = "active"; 564 pinctrl-0 = <&pwm0_pin>; 565 clocks = <&cru PCLK_PWM>; 566 clock-names = "pwm"; 567 rockchip,grf = <&grf>; 568 status = "disabled"; 569 }; 570 571 pwm1: pwm@ff680010 { 572 compatible = "rockchip,rk3288-pwm"; 573 reg = <0xff680010 0x10>; 574 #pwm-cells = <3>; 575 pinctrl-names = "active"; 576 pinctrl-0 = <&pwm1_pin>; 577 clocks = <&cru PCLK_PWM>; 578 clock-names = "pwm"; 579 rockchip,grf = <&grf>; 580 status = "disabled"; 581 }; 582 583 pwm2: pwm@ff680020 { 584 compatible = "rockchip,rk3288-pwm"; 585 reg = <0xff680020 0x10>; 586 #pwm-cells = <3>; 587 pinctrl-names = "active"; 588 pinctrl-0 = <&pwm2_pin>; 589 clocks = <&cru PCLK_PWM>; 590 clock-names = "pwm"; 591 rockchip,grf = <&grf>; 592 status = "disabled"; 593 }; 594 595 pwm3: pwm@ff680030 { 596 compatible = "rockchip,rk3288-pwm"; 597 reg = <0xff680030 0x10>; 598 #pwm-cells = <2>; 599 pinctrl-names = "active"; 600 pinctrl-0 = <&pwm3_pin>; 601 clocks = <&cru PCLK_PWM>; 602 clock-names = "pwm"; 603 rockchip,grf = <&grf>; 604 status = "disabled"; 605 }; 606 607 bus_intmem@ff700000 { 608 compatible = "mmio-sram"; 609 reg = <0xff700000 0x18000>; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges = <0 0xff700000 0x18000>; 613 smp-sram@0 { 614 compatible = "rockchip,rk3066-smp-sram"; 615 reg = <0x00 0x10>; 616 }; 617 ddr_sram: ddr-sram@1000 { 618 compatible = "rockchip,rk3288-ddr-sram"; 619 reg = <0x1000 0x4000>; 620 }; 621 }; 622 623 sram@ff720000 { 624 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 625 reg = <0xff720000 0x1000>; 626 }; 627 628 pmu: power-management@ff730000 { 629 compatible = "rockchip,rk3288-pmu", "syscon"; 630 reg = <0xff730000 0x100>; 631 }; 632 633 sgrf: syscon@ff740000 { 634 compatible = "rockchip,rk3288-sgrf", "syscon"; 635 reg = <0xff740000 0x1000>; 636 }; 637 638 cru: clock-controller@ff760000 { 639 compatible = "rockchip,rk3288-cru"; 640 reg = <0xff760000 0x1000>; 641 rockchip,grf = <&grf>; 642 #clock-cells = <1>; 643 #reset-cells = <1>; 644 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 645 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 646 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 647 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 648 <&cru PCLK_PERI>; 649 assigned-clock-rates = <594000000>, <400000000>, 650 <500000000>, <300000000>, 651 <150000000>, <75000000>, 652 <300000000>, <150000000>, 653 <75000000>; 654 }; 655 656 grf: syscon@ff770000 { 657 compatible = "rockchip,rk3288-grf", "syscon"; 658 reg = <0xff770000 0x1000>; 659 }; 660 661 wdt: watchdog@ff800000 { 662 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 663 reg = <0xff800000 0x100>; 664 clocks = <&cru PCLK_WDT>; 665 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 666 status = "disabled"; 667 }; 668 669 spdif: sound@ff88b0000 { 670 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 671 reg = <0xff8b0000 0x10000>; 672 #sound-dai-cells = <0>; 673 clock-names = "hclk", "mclk"; 674 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 675 dmas = <&dmac_bus_s 3>; 676 dma-names = "tx"; 677 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&spdif_tx>; 680 rockchip,grf = <&grf>; 681 status = "disabled"; 682 }; 683 684 i2s: i2s@ff890000 { 685 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 686 reg = <0xff890000 0x10000>; 687 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 691 dma-names = "tx", "rx"; 692 clock-names = "i2s_hclk", "i2s_clk"; 693 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&i2s0_bus>; 696 status = "disabled"; 697 }; 698 699 vopb: vop@ff930000 { 700 compatible = "rockchip,rk3288-vop-big"; 701 reg = <0xff930000 0x19c>; 702 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 704 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 705 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 706 reset-names = "axi", "ahb", "dclk"; 707 iommus = <&vopb_mmu>; 708 power-domains = <&power RK3288_PD_VIO>; 709 status = "disabled"; 710 vopb_out: port { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 vopb_out_edp: endpoint@0 { 714 reg = <0>; 715 remote-endpoint = <&edp_in_vopb>; 716 }; 717 vopb_out_hdmi: endpoint@1 { 718 reg = <1>; 719 remote-endpoint = <&hdmi_in_vopb>; 720 }; 721 vopb_out_lvds: endpoint@2 { 722 reg = <2>; 723 remote-endpoint = <&lvds_in_vopb>; 724 }; 725 vopb_out_dsi0: endpoint@3 { 726 reg = <3>; 727 remote-endpoint = <&dsi0_in_vopb>; 728 }; 729 730 }; 731 }; 732 733 vopb_mmu: iommu@ff930300 { 734 compatible = "rockchip,iommu"; 735 reg = <0xff930300 0x100>; 736 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 737 interrupt-names = "vopb_mmu"; 738 power-domains = <&power RK3288_PD_VIO>; 739 #iommu-cells = <0>; 740 status = "disabled"; 741 }; 742 743 vopl: vop@ff940000 { 744 compatible = "rockchip,rk3288-vop-lit"; 745 reg = <0xff940000 0x19c>; 746 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 748 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 749 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 750 reset-names = "axi", "ahb", "dclk"; 751 iommus = <&vopl_mmu>; 752 power-domains = <&power RK3288_PD_VIO>; 753 status = "disabled"; 754 vopl_out: port { 755 #address-cells = <1>; 756 #size-cells = <0>; 757 vopl_out_edp: endpoint@0 { 758 reg = <0>; 759 remote-endpoint = <&edp_in_vopl>; 760 }; 761 vopl_out_hdmi: endpoint@1 { 762 reg = <1>; 763 remote-endpoint = <&hdmi_in_vopl>; 764 }; 765 vopl_out_lvds: endpoint@2 { 766 reg = <2>; 767 remote-endpoint = <&lvds_in_vopl>; 768 }; 769 vopl_out_dsi0: endpoint@3 { 770 reg = <3>; 771 remote-endpoint = <&dsi0_in_vopl>; 772 }; 773 774 }; 775 }; 776 777 vopl_mmu: iommu@ff940300 { 778 compatible = "rockchip,iommu"; 779 reg = <0xff940300 0x100>; 780 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 781 interrupt-names = "vopl_mmu"; 782 power-domains = <&power RK3288_PD_VIO>; 783 #iommu-cells = <0>; 784 status = "disabled"; 785 }; 786 787 edp: edp@ff970000 { 788 compatible = "rockchip,rk3288-dp"; 789 reg = <0xff970000 0x4000>; 790 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; 792 rockchip,grf = <&grf>; 793 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; 794 resets = <&cru 111>; 795 reset-names = "edp"; 796 power-domains = <&power RK3288_PD_VIO>; 797 status = "disabled"; 798 ports { 799 #address-cells = <1>; 800 #size-cells = <0>; 801 802 edp_in: port { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 edp_in_vopb: endpoint@0 { 806 reg = <0>; 807 remote-endpoint = <&vopb_out_edp>; 808 }; 809 edp_in_vopl: endpoint@1 { 810 reg = <1>; 811 remote-endpoint = <&vopl_out_edp>; 812 }; 813 }; 814 }; 815 }; 816 817 hdmi: hdmi@ff980000 { 818 compatible = "rockchip,rk3288-dw-hdmi"; 819 reg = <0xff980000 0x20000>; 820 reg-io-width = <4>; 821 rockchip,grf = <&grf>; 822 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 824 clock-names = "iahb", "isfr"; 825 pinctrl-names = "default"; 826 pinctrl-0 = <&hdmi_ddc>; 827 status = "disabled"; 828 ports { 829 hdmi_in: port { 830 #address-cells = <1>; 831 #size-cells = <0>; 832 hdmi_in_vopb: endpoint@0 { 833 reg = <0>; 834 remote-endpoint = <&vopb_out_hdmi>; 835 }; 836 hdmi_in_vopl: endpoint@1 { 837 reg = <1>; 838 remote-endpoint = <&vopl_out_hdmi>; 839 }; 840 }; 841 }; 842 }; 843 844 lvds: lvds@ff96c000 { 845 compatible = "rockchip,rk3288-lvds"; 846 reg = <0xff96c000 0x4000>; 847 clocks = <&cru PCLK_LVDS_PHY>; 848 clock-names = "pclk_lvds"; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&lcdc0_ctl>; 851 rockchip,grf = <&grf>; 852 status = "disabled"; 853 ports { 854 #address-cells = <1>; 855 #size-cells = <0>; 856 lvds_in: port@0 { 857 reg = <0>; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 lvds_in_vopb: endpoint@0 { 861 reg = <0>; 862 remote-endpoint = <&vopb_out_lvds>; 863 }; 864 lvds_in_vopl: endpoint@1 { 865 reg = <1>; 866 remote-endpoint = <&vopl_out_lvds>; 867 }; 868 }; 869 }; 870 }; 871 872 dsi0: mipi@ff960000 { 873 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 874 reg = <0xff960000 0x4000>; 875 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 877 clock-names = "ref", "pclk"; 878 resets = <&cru SRST_MIPIDSI0>; 879 reset-names = "apb"; 880 power-domains = <&power RK3288_PD_VIO>; 881 rockchip,grf = <&grf>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 status = "disabled"; 885 ports { 886 #address-cells = <1>; 887 #size-cells = <0>; 888 reg = <1>; 889 mipi_in: port { 890 #address-cells = <1>; 891 #size-cells = <0>; 892 dsi0_in_vopb: endpoint@0 { 893 reg = <0>; 894 remote-endpoint = <&vopb_out_dsi0>; 895 }; 896 dsi0_in_vopl: endpoint@1 { 897 reg = <1>; 898 remote-endpoint = <&vopl_out_dsi0>; 899 }; 900 }; 901 }; 902 }; 903 904 hdmi_audio: hdmi_audio { 905 compatible = "rockchip,rk3288-hdmi-audio"; 906 i2s-controller = <&i2s>; 907 status = "disable"; 908 }; 909 910 vpu: video-codec@ff9a0000 { 911 compatible = "rockchip,rk3288-vpu"; 912 reg = <0xff9a0000 0x800>; 913 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "vepu", "vdpu"; 916 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 917 clock-names = "aclk_vcodec", "hclk_vcodec"; 918 power-domains = <&power RK3288_PD_VIDEO>; 919 iommus = <&vpu_mmu>; 920 }; 921 922 vpu_mmu: iommu@ff9a0800 { 923 compatible = "rockchip,iommu"; 924 reg = <0xff9a0800 0x100>; 925 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "vpu_mmu"; 927 power-domains = <&power RK3288_PD_VIDEO>; 928 #iommu-cells = <0>; 929 }; 930 931 gpu: gpu@ffa30000 { 932 compatible = "arm,malit764", 933 "arm,malit76x", 934 "arm,malit7xx", 935 "arm,mali-midgard"; 936 reg = <0xffa30000 0x10000>; 937 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 940 interrupt-names = "JOB", "MMU", "GPU"; 941 clocks = <&cru ACLK_GPU>; 942 clock-names = "aclk_gpu"; 943 operating-points = < 944 /* KHz uV */ 945 100000 950000 946 200000 950000 947 300000 1000000 948 400000 1100000 949 /* 500000 1200000 - See crosbug.com/p/33857 */ 950 600000 1250000 951 >; 952 power-domains = <&power RK3288_PD_GPU>; 953 status = "disabled"; 954 }; 955 956 noc: syscon@ffac0000 { 957 compatible = "rockchip,rk3288-noc", "syscon"; 958 reg = <0xffac0000 0x2000>; 959 }; 960 961 efuse: efuse@ffb40000 { 962 compatible = "rockchip,rk3288-efuse"; 963 reg = <0xffb40000 0x10000>; 964 status = "disabled"; 965 }; 966 967 gic: interrupt-controller@ffc01000 { 968 compatible = "arm,gic-400"; 969 interrupt-controller; 970 #interrupt-cells = <3>; 971 #address-cells = <0>; 972 973 reg = <0xffc01000 0x1000>, 974 <0xffc02000 0x1000>, 975 <0xffc04000 0x2000>, 976 <0xffc06000 0x2000>; 977 interrupts = <GIC_PPI 9 0xf04>; 978 }; 979 980 cpuidle: cpuidle { 981 compatible = "rockchip,rk3288-cpuidle"; 982 }; 983 984 usbphy: phy { 985 compatible = "rockchip,rk3288-usb-phy"; 986 rockchip,grf = <&grf>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 991 usbphy0: usb-phy0 { 992 #phy-cells = <0>; 993 reg = <0x320>; 994 clocks = <&cru SCLK_OTGPHY0>; 995 clock-names = "phyclk"; 996 }; 997 998 usbphy1: usb-phy1 { 999 #phy-cells = <0>; 1000 reg = <0x334>; 1001 clocks = <&cru SCLK_OTGPHY1>; 1002 clock-names = "phyclk"; 1003 }; 1004 1005 usbphy2: usb-phy2 { 1006 #phy-cells = <0>; 1007 reg = <0x348>; 1008 clocks = <&cru SCLK_OTGPHY2>; 1009 clock-names = "phyclk"; 1010 }; 1011 }; 1012 1013 pinctrl: pinctrl { 1014 compatible = "rockchip,rk3288-pinctrl"; 1015 rockchip,grf = <&grf>; 1016 rockchip,pmu = <&pmu>; 1017 #address-cells = <1>; 1018 #size-cells = <1>; 1019 ranges; 1020 1021 gpio0: gpio0@ff750000 { 1022 compatible = "rockchip,gpio-bank"; 1023 reg = <0xff750000 0x100>; 1024 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&cru PCLK_GPIO0>; 1026 1027 gpio-controller; 1028 #gpio-cells = <2>; 1029 1030 interrupt-controller; 1031 #interrupt-cells = <2>; 1032 }; 1033 1034 gpio1: gpio1@ff780000 { 1035 compatible = "rockchip,gpio-bank"; 1036 reg = <0xff780000 0x100>; 1037 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&cru PCLK_GPIO1>; 1039 1040 gpio-controller; 1041 #gpio-cells = <2>; 1042 1043 interrupt-controller; 1044 #interrupt-cells = <2>; 1045 }; 1046 1047 gpio2: gpio2@ff790000 { 1048 compatible = "rockchip,gpio-bank"; 1049 reg = <0xff790000 0x100>; 1050 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&cru PCLK_GPIO2>; 1052 1053 gpio-controller; 1054 #gpio-cells = <2>; 1055 1056 interrupt-controller; 1057 #interrupt-cells = <2>; 1058 }; 1059 1060 gpio3: gpio3@ff7a0000 { 1061 compatible = "rockchip,gpio-bank"; 1062 reg = <0xff7a0000 0x100>; 1063 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&cru PCLK_GPIO3>; 1065 1066 gpio-controller; 1067 #gpio-cells = <2>; 1068 1069 interrupt-controller; 1070 #interrupt-cells = <2>; 1071 }; 1072 1073 gpio4: gpio4@ff7b0000 { 1074 compatible = "rockchip,gpio-bank"; 1075 reg = <0xff7b0000 0x100>; 1076 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&cru PCLK_GPIO4>; 1078 1079 gpio-controller; 1080 #gpio-cells = <2>; 1081 1082 interrupt-controller; 1083 #interrupt-cells = <2>; 1084 }; 1085 1086 gpio5: gpio5@ff7c0000 { 1087 compatible = "rockchip,gpio-bank"; 1088 reg = <0xff7c0000 0x100>; 1089 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&cru PCLK_GPIO5>; 1091 1092 gpio-controller; 1093 #gpio-cells = <2>; 1094 1095 interrupt-controller; 1096 #interrupt-cells = <2>; 1097 }; 1098 1099 gpio6: gpio6@ff7d0000 { 1100 compatible = "rockchip,gpio-bank"; 1101 reg = <0xff7d0000 0x100>; 1102 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&cru PCLK_GPIO6>; 1104 1105 gpio-controller; 1106 #gpio-cells = <2>; 1107 1108 interrupt-controller; 1109 #interrupt-cells = <2>; 1110 }; 1111 1112 gpio7: gpio7@ff7e0000 { 1113 compatible = "rockchip,gpio-bank"; 1114 reg = <0xff7e0000 0x100>; 1115 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&cru PCLK_GPIO7>; 1117 1118 gpio-controller; 1119 #gpio-cells = <2>; 1120 1121 interrupt-controller; 1122 #interrupt-cells = <2>; 1123 }; 1124 1125 gpio8: gpio8@ff7f0000 { 1126 compatible = "rockchip,gpio-bank"; 1127 reg = <0xff7f0000 0x100>; 1128 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&cru PCLK_GPIO8>; 1130 1131 gpio-controller; 1132 #gpio-cells = <2>; 1133 1134 interrupt-controller; 1135 #interrupt-cells = <2>; 1136 }; 1137 1138 hdmi { 1139 hdmi_ddc: hdmi-ddc { 1140 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, 1141 <7 20 RK_FUNC_2 &pcfg_pull_none>; 1142 }; 1143 }; 1144 1145 pcfg_pull_up: pcfg-pull-up { 1146 bias-pull-up; 1147 }; 1148 1149 pcfg_pull_down: pcfg-pull-down { 1150 bias-pull-down; 1151 }; 1152 1153 pcfg_pull_none: pcfg-pull-none { 1154 bias-disable; 1155 }; 1156 1157 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1158 bias-disable; 1159 drive-strength = <12>; 1160 }; 1161 1162 sleep { 1163 global_pwroff: global-pwroff { 1164 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1165 }; 1166 1167 ddrio_pwroff: ddrio-pwroff { 1168 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1169 }; 1170 1171 ddr0_retention: ddr0-retention { 1172 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1173 }; 1174 1175 ddr1_retention: ddr1-retention { 1176 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1177 }; 1178 }; 1179 1180 i2c0 { 1181 i2c0_xfer: i2c0-xfer { 1182 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1183 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1184 }; 1185 }; 1186 1187 i2c1 { 1188 i2c1_xfer: i2c1-xfer { 1189 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1190 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1191 }; 1192 }; 1193 1194 i2c2 { 1195 i2c2_xfer: i2c2-xfer { 1196 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1197 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1198 }; 1199 }; 1200 1201 i2c3 { 1202 i2c3_xfer: i2c3-xfer { 1203 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1204 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1205 }; 1206 }; 1207 1208 i2c4 { 1209 i2c4_xfer: i2c4-xfer { 1210 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1211 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1212 }; 1213 }; 1214 1215 i2c5 { 1216 i2c5_xfer: i2c5-xfer { 1217 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1218 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1219 }; 1220 }; 1221 1222 i2s0 { 1223 i2s0_bus: i2s0-bus { 1224 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1225 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1226 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1227 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1228 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1229 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1230 }; 1231 }; 1232 1233 lcdc0 { 1234 lcdc0_ctl: lcdc0-ctl { 1235 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1236 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1237 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1238 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1239 }; 1240 }; 1241 1242 sdmmc { 1243 sdmmc_clk: sdmmc-clk { 1244 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1245 }; 1246 1247 sdmmc_cmd: sdmmc-cmd { 1248 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1249 }; 1250 1251 sdmmc_cd: sdmcc-cd { 1252 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1253 }; 1254 1255 sdmmc_bus1: sdmmc-bus1 { 1256 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1257 }; 1258 1259 sdmmc_bus4: sdmmc-bus4 { 1260 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1261 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1262 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1263 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1264 }; 1265 }; 1266 1267 sdio0 { 1268 sdio0_bus1: sdio0-bus1 { 1269 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1270 }; 1271 1272 sdio0_bus4: sdio0-bus4 { 1273 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1274 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1275 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1276 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1277 }; 1278 1279 sdio0_cmd: sdio0-cmd { 1280 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1281 }; 1282 1283 sdio0_clk: sdio0-clk { 1284 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1285 }; 1286 1287 sdio0_cd: sdio0-cd { 1288 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1289 }; 1290 1291 sdio0_wp: sdio0-wp { 1292 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1293 }; 1294 1295 sdio0_pwr: sdio0-pwr { 1296 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1297 }; 1298 1299 sdio0_bkpwr: sdio0-bkpwr { 1300 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1301 }; 1302 1303 sdio0_int: sdio0-int { 1304 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1305 }; 1306 }; 1307 1308 sdio1 { 1309 sdio1_bus1: sdio1-bus1 { 1310 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; 1311 }; 1312 1313 sdio1_bus4: sdio1-bus4 { 1314 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, 1315 <3 25 RK_FUNC_4 &pcfg_pull_up>, 1316 <3 26 RK_FUNC_4 &pcfg_pull_up>, 1317 <3 27 RK_FUNC_4 &pcfg_pull_up>; 1318 }; 1319 1320 sdio1_cd: sdio1-cd { 1321 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; 1322 }; 1323 1324 sdio1_wp: sdio1-wp { 1325 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; 1326 }; 1327 1328 sdio1_bkpwr: sdio1-bkpwr { 1329 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; 1330 }; 1331 1332 sdio1_int: sdio1-int { 1333 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; 1334 }; 1335 1336 sdio1_cmd: sdio1-cmd { 1337 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; 1338 }; 1339 1340 sdio1_clk: sdio1-clk { 1341 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; 1342 }; 1343 1344 sdio1_pwr: sdio1-pwr { 1345 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; 1346 }; 1347 }; 1348 1349 emmc { 1350 emmc_clk: emmc-clk { 1351 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1352 }; 1353 1354 emmc_cmd: emmc-cmd { 1355 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1356 }; 1357 1358 emmc_pwr: emmc-pwr { 1359 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1360 }; 1361 1362 emmc_bus1: emmc-bus1 { 1363 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1364 }; 1365 1366 emmc_bus4: emmc-bus4 { 1367 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1368 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1369 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1370 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1371 }; 1372 1373 emmc_bus8: emmc-bus8 { 1374 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1375 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1376 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1377 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1378 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1379 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1380 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1381 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1382 }; 1383 }; 1384 1385 spi0 { 1386 spi0_clk: spi0-clk { 1387 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1388 }; 1389 spi0_cs0: spi0-cs0 { 1390 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1391 }; 1392 spi0_tx: spi0-tx { 1393 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1394 }; 1395 spi0_rx: spi0-rx { 1396 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1397 }; 1398 spi0_cs1: spi0-cs1 { 1399 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1400 }; 1401 }; 1402 spi1 { 1403 spi1_clk: spi1-clk { 1404 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1405 }; 1406 spi1_cs0: spi1-cs0 { 1407 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1408 }; 1409 spi1_rx: spi1-rx { 1410 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1411 }; 1412 spi1_tx: spi1-tx { 1413 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1414 }; 1415 }; 1416 1417 spi2 { 1418 spi2_cs1: spi2-cs1 { 1419 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1420 }; 1421 spi2_clk: spi2-clk { 1422 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1423 }; 1424 spi2_cs0: spi2-cs0 { 1425 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1426 }; 1427 spi2_rx: spi2-rx { 1428 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1429 }; 1430 spi2_tx: spi2-tx { 1431 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1432 }; 1433 }; 1434 1435 uart0 { 1436 uart0_xfer: uart0-xfer { 1437 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1438 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1439 }; 1440 1441 uart0_cts: uart0-cts { 1442 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; 1443 }; 1444 1445 uart0_rts: uart0-rts { 1446 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1447 }; 1448 }; 1449 1450 uart1 { 1451 uart1_xfer: uart1-xfer { 1452 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1453 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1454 }; 1455 1456 uart1_cts: uart1-cts { 1457 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; 1458 }; 1459 1460 uart1_rts: uart1-rts { 1461 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1462 }; 1463 }; 1464 1465 uart2 { 1466 uart2_xfer: uart2-xfer { 1467 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1468 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1469 }; 1470 /* no rts / cts for uart2 */ 1471 }; 1472 1473 uart3 { 1474 uart3_xfer: uart3-xfer { 1475 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1476 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1477 }; 1478 1479 uart3_cts: uart3-cts { 1480 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; 1481 }; 1482 1483 uart3_rts: uart3-rts { 1484 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1485 }; 1486 }; 1487 1488 uart4 { 1489 uart4_xfer: uart4-xfer { 1490 rockchip,pins = <5 12 3 &pcfg_pull_up>, 1491 <5 13 3 &pcfg_pull_none>; 1492 }; 1493 1494 uart4_cts: uart4-cts { 1495 rockchip,pins = <5 14 3 &pcfg_pull_none>; 1496 }; 1497 1498 uart4_rts: uart4-rts { 1499 rockchip,pins = <5 15 3 &pcfg_pull_none>; 1500 }; 1501 }; 1502 1503 tsadc { 1504 otp_out: otp-out { 1505 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1506 }; 1507 }; 1508 1509 pwm0 { 1510 pwm0_pin: pwm0-pin { 1511 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1512 }; 1513 }; 1514 1515 pwm1 { 1516 pwm1_pin: pwm1-pin { 1517 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1518 }; 1519 }; 1520 1521 pwm2 { 1522 pwm2_pin: pwm2-pin { 1523 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; 1524 }; 1525 }; 1526 1527 pwm3 { 1528 pwm3_pin: pwm3-pin { 1529 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; 1530 }; 1531 }; 1532 1533 gmac { 1534 rgmii_pins: rgmii-pins { 1535 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1536 <3 31 3 &pcfg_pull_none>, 1537 <3 26 3 &pcfg_pull_none>, 1538 <3 27 3 &pcfg_pull_none>, 1539 <3 28 3 &pcfg_pull_none_12ma>, 1540 <3 29 3 &pcfg_pull_none_12ma>, 1541 <3 24 3 &pcfg_pull_none_12ma>, 1542 <3 25 3 &pcfg_pull_none_12ma>, 1543 <4 0 3 &pcfg_pull_none>, 1544 <4 5 3 &pcfg_pull_none>, 1545 <4 6 3 &pcfg_pull_none>, 1546 <4 9 3 &pcfg_pull_none_12ma>, 1547 <4 4 3 &pcfg_pull_none_12ma>, 1548 <4 1 3 &pcfg_pull_none>, 1549 <4 3 3 &pcfg_pull_none>; 1550 }; 1551 1552 rmii_pins: rmii-pins { 1553 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1554 <3 31 3 &pcfg_pull_none>, 1555 <3 28 3 &pcfg_pull_none>, 1556 <3 29 3 &pcfg_pull_none>, 1557 <4 0 3 &pcfg_pull_none>, 1558 <4 5 3 &pcfg_pull_none>, 1559 <4 4 3 &pcfg_pull_none>, 1560 <4 1 3 &pcfg_pull_none>, 1561 <4 2 3 &pcfg_pull_none>, 1562 <4 3 3 &pcfg_pull_none>; 1563 }; 1564 }; 1565 1566 spdif { 1567 spdif_tx: spdif-tx { 1568 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1569 }; 1570 }; 1571 }; 1572 1573 power: power-controller { 1574 compatible = "rockchip,rk3288-power-controller"; 1575 #power-domain-cells = <1>; 1576 rockchip,pmu = <&pmu>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 1580 pd_gpu { 1581 reg = <RK3288_PD_GPU>; 1582 clocks = <&cru ACLK_GPU>; 1583 }; 1584 1585 pd_hevc { 1586 reg = <RK3288_PD_HEVC>; 1587 clocks = <&cru ACLK_HEVC>, 1588 <&cru SCLK_HEVC_CABAC>, 1589 <&cru SCLK_HEVC_CORE>, 1590 <&cru HCLK_HEVC>; 1591 }; 1592 1593 pd_vio { 1594 reg = <RK3288_PD_VIO>; 1595 clocks = <&cru ACLK_IEP>, 1596 <&cru ACLK_ISP>, 1597 <&cru ACLK_RGA>, 1598 <&cru ACLK_VIP>, 1599 <&cru ACLK_VOP0>, 1600 <&cru ACLK_VOP1>, 1601 <&cru DCLK_VOP0>, 1602 <&cru DCLK_VOP1>, 1603 <&cru HCLK_IEP>, 1604 <&cru HCLK_ISP>, 1605 <&cru HCLK_RGA>, 1606 <&cru HCLK_VIP>, 1607 <&cru HCLK_VOP0>, 1608 <&cru HCLK_VOP1>, 1609 <&cru PCLK_EDP_CTRL>, 1610 <&cru PCLK_HDMI_CTRL>, 1611 <&cru PCLK_LVDS_PHY>, 1612 <&cru PCLK_MIPI_CSI>, 1613 <&cru PCLK_MIPI_DSI0>, 1614 <&cru PCLK_MIPI_DSI1>, 1615 <&cru SCLK_EDP_24M>, 1616 <&cru SCLK_EDP>, 1617 <&cru SCLK_HDMI_CEC>, 1618 <&cru SCLK_HDMI_HDCP>, 1619 <&cru SCLK_ISP_JPE>, 1620 <&cru SCLK_ISP>, 1621 <&cru SCLK_RGA>; 1622 }; 1623 1624 pd_video { 1625 reg = <RK3288_PD_VIDEO>; 1626 clocks = <&cru ACLK_VCODEC>, 1627 <&cru HCLK_VCODEC>; 1628 }; 1629 }; 1630}; 1631
