1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3288-cru.h> 10#include <dt-bindings/power-domain/rk3288.h> 11#include <dt-bindings/thermal/thermal.h> 12#include <dt-bindings/video/rk3288.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 gpio4 = &gpio4; 25 gpio5 = &gpio5; 26 gpio6 = &gpio6; 27 gpio7 = &gpio7; 28 gpio8 = &gpio8; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 mmc2 = &sdio0; 38 mmc3 = &sdio1; 39 mshc0 = &emmc; 40 mshc1 = &sdmmc; 41 mshc2 = &sdio0; 42 mshc3 = &sdio1; 43 serial0 = &uart0; 44 serial1 = &uart1; 45 serial2 = &uart2; 46 serial3 = &uart3; 47 serial4 = &uart4; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 enable-method = "rockchip,rk3066-smp"; 57 rockchip,pmu = <&pmu>; 58 59 cpu0: cpu@500 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a12"; 62 reg = <0x500>; 63 operating-points = < 64 /* KHz uV */ 65 1800000 1400000 66 1704000 1350000 67 1608000 1300000 68 1512000 1250000 69 1416000 1200000 70 1200000 1100000 71 1008000 1050000 72 816000 1000000 73 696000 950000 74 600000 900000 75 408000 900000 76 216000 900000 77 126000 900000 78 >; 79 #cooling-cells = <2>; /* min followed by max */ 80 clock-latency = <40000>; 81 clocks = <&cru ARMCLK>; 82 resets = <&cru SRST_CORE0>; 83 }; 84 cpu@501 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a12"; 87 reg = <0x501>; 88 resets = <&cru SRST_CORE1>; 89 }; 90 cpu@502 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a12"; 93 reg = <0x502>; 94 resets = <&cru SRST_CORE2>; 95 }; 96 cpu@503 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a12"; 99 reg = <0x503>; 100 resets = <&cru SRST_CORE3>; 101 }; 102 }; 103 104 amba { 105 compatible = "arm,amba-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 dmac_peri: dma-controller@ff250000 { 111 compatible = "arm,pl330", "arm,primecell"; 112 broken-no-flushp; 113 reg = <0xff250000 0x4000>; 114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 116 #dma-cells = <1>; 117 clocks = <&cru ACLK_DMAC2>; 118 clock-names = "apb_pclk"; 119 }; 120 121 dmac_bus_ns: dma-controller@ff600000 { 122 compatible = "arm,pl330", "arm,primecell"; 123 broken-no-flushp; 124 reg = <0xff600000 0x4000>; 125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 127 #dma-cells = <1>; 128 clocks = <&cru ACLK_DMAC1>; 129 clock-names = "apb_pclk"; 130 status = "disabled"; 131 }; 132 133 dmac_bus_s: dma-controller@ffb20000 { 134 compatible = "arm,pl330", "arm,primecell"; 135 broken-no-flushp; 136 reg = <0xffb20000 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 #dma-cells = <1>; 140 clocks = <&cru ACLK_DMAC1>; 141 clock-names = "apb_pclk"; 142 }; 143 }; 144 145 xin24m: oscillator { 146 compatible = "fixed-clock"; 147 clock-frequency = <24000000>; 148 clock-output-names = "xin24m"; 149 #clock-cells = <0>; 150 }; 151 152 timer { 153 arm,use-physical-timer; 154 compatible = "arm,armv7-timer"; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 159 clock-frequency = <24000000>; 160 always-on; 161 }; 162 163 display_subsystem: display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopl_out>, <&vopb_out>; 166 status = "disabled"; 167 168 route { 169 route_hdmi: route-hdmi { 170 status = "disabled"; 171 logo,uboot = "logo.bmp"; 172 logo,kernel = "logo_kernel.bmp"; 173 logo,mode = "center"; 174 charge_logo,mode = "center"; 175 connect = <&vopb_out_hdmi>; 176 }; 177 178 route_edp: route-edp { 179 status = "disabled"; 180 logo,uboot = "logo.bmp"; 181 logo,kernel = "logo_kernel.bmp"; 182 logo,mode = "center"; 183 charge_logo,mode = "center"; 184 connect = <&vopl_out_edp>; 185 }; 186 187 route_dsi0: route-dsi0 { 188 status = "disabled"; 189 logo,uboot = "logo.bmp"; 190 logo,kernel = "logo_kernel.bmp"; 191 logo,mode = "center"; 192 charge_logo,mode = "center"; 193 connect = <&vopl_out_dsi0>; 194 }; 195 196 route_lvds: route-lvds { 197 status = "disabled"; 198 logo,uboot = "logo.bmp"; 199 logo,kernel = "logo_kernel.bmp"; 200 logo,mode = "center"; 201 charge_logo,mode = "center"; 202 connect = <&vopl_out_lvds>; 203 }; 204 }; 205 }; 206 207 sdmmc: dwmmc@ff0c0000 { 208 compatible = "rockchip,rk3288-dw-mshc"; 209 max-frequency = <150000000>; 210 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 211 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 212 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 213 fifo-depth = <0x100>; 214 cd-gpios = <&gpio6 RK_PC6 GPIO_ACTIVE_HIGH>; 215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 216 reg = <0xff0c0000 0x4000>; 217 status = "disabled"; 218 }; 219 220 sdio0: dwmmc@ff0d0000 { 221 compatible = "rockchip,rk3288-dw-mshc"; 222 max-frequency = <150000000>; 223 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 224 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 225 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 226 fifo-depth = <0x100>; 227 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 228 reg = <0xff0d0000 0x4000>; 229 status = "disabled"; 230 }; 231 232 sdio1: dwmmc@ff0e0000 { 233 compatible = "rockchip,rk3288-dw-mshc"; 234 max-frequency = <150000000>; 235 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 236 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 237 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 238 fifo-depth = <0x100>; 239 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 240 reg = <0xff0e0000 0x4000>; 241 status = "disabled"; 242 }; 243 244 emmc: dwmmc@ff0f0000 { 245 compatible = "rockchip,rk3288-dw-mshc"; 246 max-frequency = <150000000>; 247 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 248 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 249 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 250 fifo-depth = <0x100>; 251 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 252 reg = <0xff0f0000 0x4000>; 253 status = "disabled"; 254 }; 255 256 saradc: saradc@ff100000 { 257 compatible = "rockchip,saradc"; 258 reg = <0xff100000 0x100>; 259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 260 #io-channel-cells = <1>; 261 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 262 clock-names = "saradc", "apb_pclk"; 263 status = "disabled"; 264 }; 265 266 spi0: spi@ff110000 { 267 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 268 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 269 clock-names = "spiclk", "apb_pclk"; 270 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 271 dma-names = "tx", "rx"; 272 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 275 reg = <0xff110000 0x1000>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 status = "disabled"; 279 }; 280 281 spi1: spi@ff120000 { 282 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 283 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 284 clock-names = "spiclk", "apb_pclk"; 285 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 286 dma-names = "tx", "rx"; 287 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 290 reg = <0xff120000 0x1000>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 status = "disabled"; 294 }; 295 296 spi2: spi@ff130000 { 297 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 298 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 299 clock-names = "spiclk", "apb_pclk"; 300 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 301 dma-names = "tx", "rx"; 302 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 305 reg = <0xff130000 0x1000>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 311 i2c1: i2c@ff140000 { 312 compatible = "rockchip,rk3288-i2c"; 313 reg = <0xff140000 0x1000>; 314 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 clock-names = "i2c"; 318 clocks = <&cru PCLK_I2C1>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&i2c1_xfer>; 321 status = "disabled"; 322 }; 323 324 i2c3: i2c@ff150000 { 325 compatible = "rockchip,rk3288-i2c"; 326 reg = <0xff150000 0x1000>; 327 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 clock-names = "i2c"; 331 clocks = <&cru PCLK_I2C3>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&i2c3_xfer>; 334 status = "disabled"; 335 }; 336 337 i2c4: i2c@ff160000 { 338 compatible = "rockchip,rk3288-i2c"; 339 reg = <0xff160000 0x1000>; 340 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 clock-names = "i2c"; 344 clocks = <&cru PCLK_I2C4>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&i2c4_xfer>; 347 status = "disabled"; 348 }; 349 350 i2c5: i2c@ff170000 { 351 compatible = "rockchip,rk3288-i2c"; 352 reg = <0xff170000 0x1000>; 353 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 clock-names = "i2c"; 357 clocks = <&cru PCLK_I2C5>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&i2c5_xfer>; 360 status = "disabled"; 361 }; 362 363 uart0: serial@ff180000 { 364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 365 reg = <0xff180000 0x100>; 366 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 367 reg-shift = <2>; 368 reg-io-width = <4>; 369 clock-frequency = <24000000>; 370 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 371 clock-names = "baudclk", "apb_pclk"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&uart0_xfer>; 374 status = "disabled"; 375 }; 376 377 uart1: serial@ff190000 { 378 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 379 reg = <0xff190000 0x100>; 380 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 381 reg-shift = <2>; 382 reg-io-width = <4>; 383 clock-frequency = <24000000>; 384 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 385 clock-names = "baudclk", "apb_pclk"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&uart1_xfer>; 388 status = "disabled"; 389 }; 390 391 uart2: serial@ff690000 { 392 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 393 reg = <0xff690000 0x100>; 394 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 395 reg-shift = <2>; 396 reg-io-width = <4>; 397 clock-frequency = <24000000>; 398 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 399 clock-names = "baudclk", "apb_pclk"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&uart2_xfer>; 402 status = "disabled"; 403 }; 404 uart3: serial@ff1b0000 { 405 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 406 reg = <0xff1b0000 0x100>; 407 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 408 reg-shift = <2>; 409 reg-io-width = <4>; 410 clock-frequency = <24000000>; 411 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 412 clock-names = "baudclk", "apb_pclk"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&uart3_xfer>; 415 status = "disabled"; 416 }; 417 418 uart4: serial@ff1c0000 { 419 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 420 reg = <0xff1c0000 0x100>; 421 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 422 reg-shift = <2>; 423 reg-io-width = <4>; 424 clock-frequency = <24000000>; 425 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 426 clock-names = "baudclk", "apb_pclk"; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&uart4_xfer>; 429 status = "disabled"; 430 }; 431 432 thermal: thermal-zones { 433 #include "rk3288-thermal.dtsi" 434 }; 435 436 tsadc: tsadc@ff280000 { 437 compatible = "rockchip,rk3288-tsadc"; 438 reg = <0xff280000 0x100>; 439 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 441 clock-names = "tsadc", "apb_pclk"; 442 resets = <&cru SRST_TSADC>; 443 reset-names = "tsadc-apb"; 444 pinctrl-names = "otp_out"; 445 pinctrl-0 = <&otp_out>; 446 #thermal-sensor-cells = <1>; 447 hw-shut-temp = <125000>; 448 status = "disabled"; 449 }; 450 451 gmac: ethernet@ff290000 { 452 compatible = "rockchip,rk3288-gmac"; 453 reg = <0xff290000 0x10000>; 454 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 455 interrupt-names = "macirq"; 456 rockchip,grf = <&grf>; 457 clocks = <&cru SCLK_MAC>, 458 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 459 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 460 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 461 clock-names = "stmmaceth", 462 "mac_clk_rx", "mac_clk_tx", 463 "clk_mac_ref", "clk_mac_refout", 464 "aclk_mac", "pclk_mac"; 465 }; 466 467 usb_host0_ehci: usb@ff500000 { 468 compatible = "generic-ehci"; 469 reg = <0xff500000 0x100>; 470 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cru HCLK_USBHOST0>; 472 clock-names = "usbhost"; 473 phys = <&usbphy1>; 474 phy-names = "usb"; 475 status = "disabled"; 476 }; 477 478 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 479 480 usb_host1: usb@ff540000 { 481 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 482 "snps,dwc2"; 483 reg = <0xff540000 0x40000>; 484 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cru HCLK_USBHOST1>; 486 clock-names = "otg"; 487 phys = <&usbphy2>; 488 phy-names = "usb2-phy"; 489 status = "disabled"; 490 }; 491 492 usb_otg: usb@ff580000 { 493 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 494 "snps,dwc2"; 495 reg = <0xff580000 0x40000>; 496 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cru HCLK_OTG0>; 498 clock-names = "otg"; 499 dr_mode = "otg"; 500 phys = <&usbphy0>; 501 phy-names = "usb2-phy"; 502 status = "disabled"; 503 }; 504 505 usb_hsic: usb@ff5c0000 { 506 compatible = "generic-ehci"; 507 reg = <0xff5c0000 0x100>; 508 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cru HCLK_HSIC>; 510 clock-names = "usbhost"; 511 status = "disabled"; 512 }; 513 514 dmc: dmc@ff610000 { 515 compatible = "rockchip,rk3288-dmc", "syscon"; 516 rockchip,cru = <&cru>; 517 rockchip,grf = <&grf>; 518 rockchip,pmu = <&pmu>; 519 rockchip,sgrf = <&sgrf>; 520 rockchip,noc = <&noc>; 521 reg = <0xff610000 0x3fc 522 0xff620000 0x294 523 0xff630000 0x3fc 524 0xff640000 0x294>; 525 rockchip,sram = <&ddr_sram>; 526 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, 527 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, 528 <&cru ARMCLK>; 529 clock-names = "pclk_ddrupctl0", "pclk_publ0", 530 "pclk_ddrupctl1", "pclk_publ1", 531 "arm_clk"; 532 }; 533 534 i2c0: i2c@ff650000 { 535 compatible = "rockchip,rk3288-i2c"; 536 reg = <0xff650000 0x1000>; 537 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clock-names = "i2c"; 541 clocks = <&cru PCLK_I2C0>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&i2c0_xfer>; 544 status = "disabled"; 545 }; 546 547 i2c2: i2c@ff660000 { 548 compatible = "rockchip,rk3288-i2c"; 549 reg = <0xff660000 0x1000>; 550 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 clock-names = "i2c"; 554 clocks = <&cru PCLK_I2C2>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&i2c2_xfer>; 557 status = "disabled"; 558 }; 559 560 pwm0: pwm@ff680000 { 561 compatible = "rockchip,rk3288-pwm"; 562 reg = <0xff680000 0x10>; 563 #pwm-cells = <3>; 564 pinctrl-names = "active"; 565 pinctrl-0 = <&pwm0_pin>; 566 clocks = <&cru PCLK_PWM>; 567 clock-names = "pwm"; 568 rockchip,grf = <&grf>; 569 status = "disabled"; 570 }; 571 572 pwm1: pwm@ff680010 { 573 compatible = "rockchip,rk3288-pwm"; 574 reg = <0xff680010 0x10>; 575 #pwm-cells = <3>; 576 pinctrl-names = "active"; 577 pinctrl-0 = <&pwm1_pin>; 578 clocks = <&cru PCLK_PWM>; 579 clock-names = "pwm"; 580 rockchip,grf = <&grf>; 581 status = "disabled"; 582 }; 583 584 pwm2: pwm@ff680020 { 585 compatible = "rockchip,rk3288-pwm"; 586 reg = <0xff680020 0x10>; 587 #pwm-cells = <3>; 588 pinctrl-names = "active"; 589 pinctrl-0 = <&pwm2_pin>; 590 clocks = <&cru PCLK_PWM>; 591 clock-names = "pwm"; 592 rockchip,grf = <&grf>; 593 status = "disabled"; 594 }; 595 596 pwm3: pwm@ff680030 { 597 compatible = "rockchip,rk3288-pwm"; 598 reg = <0xff680030 0x10>; 599 #pwm-cells = <2>; 600 pinctrl-names = "active"; 601 pinctrl-0 = <&pwm3_pin>; 602 clocks = <&cru PCLK_PWM>; 603 clock-names = "pwm"; 604 rockchip,grf = <&grf>; 605 status = "disabled"; 606 }; 607 608 bus_intmem@ff700000 { 609 compatible = "mmio-sram"; 610 reg = <0xff700000 0x18000>; 611 #address-cells = <1>; 612 #size-cells = <1>; 613 ranges = <0 0xff700000 0x18000>; 614 smp-sram@0 { 615 compatible = "rockchip,rk3066-smp-sram"; 616 reg = <0x00 0x10>; 617 }; 618 ddr_sram: ddr-sram@1000 { 619 compatible = "rockchip,rk3288-ddr-sram"; 620 reg = <0x1000 0x4000>; 621 }; 622 }; 623 624 sram@ff720000 { 625 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 626 reg = <0xff720000 0x1000>; 627 }; 628 629 pmu: power-management@ff730000 { 630 compatible = "rockchip,rk3288-pmu", "syscon"; 631 reg = <0xff730000 0x100>; 632 }; 633 634 sgrf: syscon@ff740000 { 635 compatible = "rockchip,rk3288-sgrf", "syscon"; 636 reg = <0xff740000 0x1000>; 637 }; 638 639 cru: clock-controller@ff760000 { 640 compatible = "rockchip,rk3288-cru"; 641 reg = <0xff760000 0x1000>; 642 rockchip,grf = <&grf>; 643 #clock-cells = <1>; 644 #reset-cells = <1>; 645 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 646 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 647 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 648 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 649 <&cru PCLK_PERI>; 650 assigned-clock-rates = <594000000>, <400000000>, 651 <500000000>, <300000000>, 652 <150000000>, <75000000>, 653 <300000000>, <150000000>, 654 <75000000>; 655 }; 656 657 grf: syscon@ff770000 { 658 compatible = "rockchip,rk3288-grf", "syscon"; 659 reg = <0xff770000 0x1000>; 660 }; 661 662 wdt: watchdog@ff800000 { 663 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 664 reg = <0xff800000 0x100>; 665 clocks = <&cru PCLK_WDT>; 666 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 667 status = "disabled"; 668 }; 669 670 spdif: sound@ff88b0000 { 671 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 672 reg = <0xff8b0000 0x10000>; 673 #sound-dai-cells = <0>; 674 clock-names = "hclk", "mclk"; 675 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 676 dmas = <&dmac_bus_s 3>; 677 dma-names = "tx"; 678 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&spdif_tx>; 681 rockchip,grf = <&grf>; 682 status = "disabled"; 683 }; 684 685 i2s: i2s@ff890000 { 686 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 687 reg = <0xff890000 0x10000>; 688 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 692 dma-names = "tx", "rx"; 693 clock-names = "i2s_hclk", "i2s_clk"; 694 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&i2s0_bus>; 697 status = "disabled"; 698 }; 699 700 vopb: vop@ff930000 { 701 compatible = "rockchip,rk3288-vop-big"; 702 reg = <0xff930000 0x19c>; 703 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 705 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 706 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 707 reset-names = "axi", "ahb", "dclk"; 708 iommus = <&vopb_mmu>; 709 power-domains = <&power RK3288_PD_VIO>; 710 status = "disabled"; 711 vopb_out: port { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 vopb_out_edp: endpoint@0 { 715 reg = <0>; 716 remote-endpoint = <&edp_in_vopb>; 717 }; 718 vopb_out_hdmi: endpoint@1 { 719 reg = <1>; 720 remote-endpoint = <&hdmi_in_vopb>; 721 }; 722 vopb_out_lvds: endpoint@2 { 723 reg = <2>; 724 remote-endpoint = <&lvds_in_vopb>; 725 }; 726 vopb_out_dsi0: endpoint@3 { 727 reg = <3>; 728 remote-endpoint = <&dsi0_in_vopb>; 729 }; 730 731 }; 732 }; 733 734 vopb_mmu: iommu@ff930300 { 735 compatible = "rockchip,iommu"; 736 reg = <0xff930300 0x100>; 737 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "vopb_mmu"; 739 power-domains = <&power RK3288_PD_VIO>; 740 #iommu-cells = <0>; 741 status = "disabled"; 742 }; 743 744 vopl: vop@ff940000 { 745 compatible = "rockchip,rk3288-vop-lit"; 746 reg = <0xff940000 0x19c>; 747 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 749 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 750 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 751 reset-names = "axi", "ahb", "dclk"; 752 iommus = <&vopl_mmu>; 753 power-domains = <&power RK3288_PD_VIO>; 754 status = "disabled"; 755 vopl_out: port { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 vopl_out_edp: endpoint@0 { 759 reg = <0>; 760 remote-endpoint = <&edp_in_vopl>; 761 }; 762 vopl_out_hdmi: endpoint@1 { 763 reg = <1>; 764 remote-endpoint = <&hdmi_in_vopl>; 765 }; 766 vopl_out_lvds: endpoint@2 { 767 reg = <2>; 768 remote-endpoint = <&lvds_in_vopl>; 769 }; 770 vopl_out_dsi0: endpoint@3 { 771 reg = <3>; 772 remote-endpoint = <&dsi0_in_vopl>; 773 }; 774 775 }; 776 }; 777 778 vopl_mmu: iommu@ff940300 { 779 compatible = "rockchip,iommu"; 780 reg = <0xff940300 0x100>; 781 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 782 interrupt-names = "vopl_mmu"; 783 power-domains = <&power RK3288_PD_VIO>; 784 #iommu-cells = <0>; 785 status = "disabled"; 786 }; 787 788 edp: edp@ff970000 { 789 compatible = "rockchip,rk3288-dp"; 790 reg = <0xff970000 0x4000>; 791 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; 793 rockchip,grf = <&grf>; 794 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; 795 resets = <&cru 111>; 796 reset-names = "edp"; 797 power-domains = <&power RK3288_PD_VIO>; 798 status = "disabled"; 799 ports { 800 #address-cells = <1>; 801 #size-cells = <0>; 802 803 edp_in: port { 804 #address-cells = <1>; 805 #size-cells = <0>; 806 edp_in_vopb: endpoint@0 { 807 reg = <0>; 808 remote-endpoint = <&vopb_out_edp>; 809 }; 810 edp_in_vopl: endpoint@1 { 811 reg = <1>; 812 remote-endpoint = <&vopl_out_edp>; 813 }; 814 }; 815 }; 816 }; 817 818 hdmi: hdmi@ff980000 { 819 compatible = "rockchip,rk3288-dw-hdmi"; 820 reg = <0xff980000 0x20000>; 821 reg-io-width = <4>; 822 rockchip,grf = <&grf>; 823 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 825 clock-names = "iahb", "isfr"; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&hdmi_ddc>; 828 status = "disabled"; 829 ports { 830 hdmi_in: port { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 hdmi_in_vopb: endpoint@0 { 834 reg = <0>; 835 remote-endpoint = <&vopb_out_hdmi>; 836 }; 837 hdmi_in_vopl: endpoint@1 { 838 reg = <1>; 839 remote-endpoint = <&vopl_out_hdmi>; 840 }; 841 }; 842 }; 843 }; 844 845 lvds: lvds@ff96c000 { 846 compatible = "rockchip,rk3288-lvds"; 847 reg = <0xff96c000 0x4000>; 848 clocks = <&cru PCLK_LVDS_PHY>; 849 clock-names = "pclk_lvds"; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&lcdc0_ctl>; 852 rockchip,grf = <&grf>; 853 status = "disabled"; 854 ports { 855 #address-cells = <1>; 856 #size-cells = <0>; 857 lvds_in: port@0 { 858 reg = <0>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 lvds_in_vopb: endpoint@0 { 862 reg = <0>; 863 remote-endpoint = <&vopb_out_lvds>; 864 }; 865 lvds_in_vopl: endpoint@1 { 866 reg = <1>; 867 remote-endpoint = <&vopl_out_lvds>; 868 }; 869 }; 870 }; 871 }; 872 873 dsi0: mipi@ff960000 { 874 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 875 reg = <0xff960000 0x4000>; 876 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 878 clock-names = "ref", "pclk"; 879 resets = <&cru SRST_MIPIDSI0>; 880 reset-names = "apb"; 881 power-domains = <&power RK3288_PD_VIO>; 882 rockchip,grf = <&grf>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 status = "disabled"; 886 ports { 887 #address-cells = <1>; 888 #size-cells = <0>; 889 reg = <1>; 890 mipi_in: port { 891 #address-cells = <1>; 892 #size-cells = <0>; 893 dsi0_in_vopb: endpoint@0 { 894 reg = <0>; 895 remote-endpoint = <&vopb_out_dsi0>; 896 }; 897 dsi0_in_vopl: endpoint@1 { 898 reg = <1>; 899 remote-endpoint = <&vopl_out_dsi0>; 900 }; 901 }; 902 }; 903 }; 904 905 hdmi_audio: hdmi_audio { 906 compatible = "rockchip,rk3288-hdmi-audio"; 907 i2s-controller = <&i2s>; 908 status = "disable"; 909 }; 910 911 vpu: video-codec@ff9a0000 { 912 compatible = "rockchip,rk3288-vpu"; 913 reg = <0xff9a0000 0x800>; 914 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "vepu", "vdpu"; 917 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 918 clock-names = "aclk_vcodec", "hclk_vcodec"; 919 power-domains = <&power RK3288_PD_VIDEO>; 920 iommus = <&vpu_mmu>; 921 }; 922 923 vpu_mmu: iommu@ff9a0800 { 924 compatible = "rockchip,iommu"; 925 reg = <0xff9a0800 0x100>; 926 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-names = "vpu_mmu"; 928 power-domains = <&power RK3288_PD_VIDEO>; 929 #iommu-cells = <0>; 930 }; 931 932 gpu: gpu@ffa30000 { 933 compatible = "arm,malit764", 934 "arm,malit76x", 935 "arm,malit7xx", 936 "arm,mali-midgard"; 937 reg = <0xffa30000 0x10000>; 938 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-names = "JOB", "MMU", "GPU"; 942 clocks = <&cru ACLK_GPU>; 943 clock-names = "aclk_gpu"; 944 operating-points = < 945 /* KHz uV */ 946 100000 950000 947 200000 950000 948 300000 1000000 949 400000 1100000 950 /* 500000 1200000 - See crosbug.com/p/33857 */ 951 600000 1250000 952 >; 953 power-domains = <&power RK3288_PD_GPU>; 954 status = "disabled"; 955 }; 956 957 noc: syscon@ffac0000 { 958 compatible = "rockchip,rk3288-noc", "syscon"; 959 reg = <0xffac0000 0x2000>; 960 }; 961 962 efuse: efuse@ffb40000 { 963 compatible = "rockchip,rk3288-efuse"; 964 reg = <0xffb40000 0x10000>; 965 status = "disabled"; 966 }; 967 968 gic: interrupt-controller@ffc01000 { 969 compatible = "arm,gic-400"; 970 interrupt-controller; 971 #interrupt-cells = <3>; 972 #address-cells = <0>; 973 974 reg = <0xffc01000 0x1000>, 975 <0xffc02000 0x1000>, 976 <0xffc04000 0x2000>, 977 <0xffc06000 0x2000>; 978 interrupts = <GIC_PPI 9 0xf04>; 979 }; 980 981 cpuidle: cpuidle { 982 compatible = "rockchip,rk3288-cpuidle"; 983 }; 984 985 usbphy: phy { 986 compatible = "rockchip,rk3288-usb-phy"; 987 rockchip,grf = <&grf>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 992 usbphy0: usb-phy0 { 993 #phy-cells = <0>; 994 reg = <0x320>; 995 clocks = <&cru SCLK_OTGPHY0>; 996 clock-names = "phyclk"; 997 }; 998 999 usbphy1: usb-phy1 { 1000 #phy-cells = <0>; 1001 reg = <0x334>; 1002 clocks = <&cru SCLK_OTGPHY1>; 1003 clock-names = "phyclk"; 1004 }; 1005 1006 usbphy2: usb-phy2 { 1007 #phy-cells = <0>; 1008 reg = <0x348>; 1009 clocks = <&cru SCLK_OTGPHY2>; 1010 clock-names = "phyclk"; 1011 }; 1012 }; 1013 1014 pinctrl: pinctrl { 1015 compatible = "rockchip,rk3288-pinctrl"; 1016 rockchip,grf = <&grf>; 1017 rockchip,pmu = <&pmu>; 1018 #address-cells = <1>; 1019 #size-cells = <1>; 1020 ranges; 1021 1022 gpio0: gpio0@ff750000 { 1023 compatible = "rockchip,gpio-bank"; 1024 reg = <0xff750000 0x100>; 1025 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&cru PCLK_GPIO0>; 1027 1028 gpio-controller; 1029 #gpio-cells = <2>; 1030 1031 interrupt-controller; 1032 #interrupt-cells = <2>; 1033 }; 1034 1035 gpio1: gpio1@ff780000 { 1036 compatible = "rockchip,gpio-bank"; 1037 reg = <0xff780000 0x100>; 1038 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cru PCLK_GPIO1>; 1040 1041 gpio-controller; 1042 #gpio-cells = <2>; 1043 1044 interrupt-controller; 1045 #interrupt-cells = <2>; 1046 }; 1047 1048 gpio2: gpio2@ff790000 { 1049 compatible = "rockchip,gpio-bank"; 1050 reg = <0xff790000 0x100>; 1051 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&cru PCLK_GPIO2>; 1053 1054 gpio-controller; 1055 #gpio-cells = <2>; 1056 1057 interrupt-controller; 1058 #interrupt-cells = <2>; 1059 }; 1060 1061 gpio3: gpio3@ff7a0000 { 1062 compatible = "rockchip,gpio-bank"; 1063 reg = <0xff7a0000 0x100>; 1064 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cru PCLK_GPIO3>; 1066 1067 gpio-controller; 1068 #gpio-cells = <2>; 1069 1070 interrupt-controller; 1071 #interrupt-cells = <2>; 1072 }; 1073 1074 gpio4: gpio4@ff7b0000 { 1075 compatible = "rockchip,gpio-bank"; 1076 reg = <0xff7b0000 0x100>; 1077 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&cru PCLK_GPIO4>; 1079 1080 gpio-controller; 1081 #gpio-cells = <2>; 1082 1083 interrupt-controller; 1084 #interrupt-cells = <2>; 1085 }; 1086 1087 gpio5: gpio5@ff7c0000 { 1088 compatible = "rockchip,gpio-bank"; 1089 reg = <0xff7c0000 0x100>; 1090 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&cru PCLK_GPIO5>; 1092 1093 gpio-controller; 1094 #gpio-cells = <2>; 1095 1096 interrupt-controller; 1097 #interrupt-cells = <2>; 1098 }; 1099 1100 gpio6: gpio6@ff7d0000 { 1101 compatible = "rockchip,gpio-bank"; 1102 reg = <0xff7d0000 0x100>; 1103 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&cru PCLK_GPIO6>; 1105 1106 gpio-controller; 1107 #gpio-cells = <2>; 1108 1109 interrupt-controller; 1110 #interrupt-cells = <2>; 1111 }; 1112 1113 gpio7: gpio7@ff7e0000 { 1114 compatible = "rockchip,gpio-bank"; 1115 reg = <0xff7e0000 0x100>; 1116 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&cru PCLK_GPIO7>; 1118 1119 gpio-controller; 1120 #gpio-cells = <2>; 1121 1122 interrupt-controller; 1123 #interrupt-cells = <2>; 1124 }; 1125 1126 gpio8: gpio8@ff7f0000 { 1127 compatible = "rockchip,gpio-bank"; 1128 reg = <0xff7f0000 0x100>; 1129 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&cru PCLK_GPIO8>; 1131 1132 gpio-controller; 1133 #gpio-cells = <2>; 1134 1135 interrupt-controller; 1136 #interrupt-cells = <2>; 1137 }; 1138 1139 hdmi { 1140 hdmi_ddc: hdmi-ddc { 1141 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, 1142 <7 20 RK_FUNC_2 &pcfg_pull_none>; 1143 }; 1144 }; 1145 1146 pcfg_pull_up: pcfg-pull-up { 1147 bias-pull-up; 1148 }; 1149 1150 pcfg_pull_down: pcfg-pull-down { 1151 bias-pull-down; 1152 }; 1153 1154 pcfg_pull_none: pcfg-pull-none { 1155 bias-disable; 1156 }; 1157 1158 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1159 bias-disable; 1160 drive-strength = <12>; 1161 }; 1162 1163 sleep { 1164 global_pwroff: global-pwroff { 1165 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1166 }; 1167 1168 ddrio_pwroff: ddrio-pwroff { 1169 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1170 }; 1171 1172 ddr0_retention: ddr0-retention { 1173 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1174 }; 1175 1176 ddr1_retention: ddr1-retention { 1177 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1178 }; 1179 }; 1180 1181 i2c0 { 1182 i2c0_xfer: i2c0-xfer { 1183 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1184 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1185 }; 1186 }; 1187 1188 i2c1 { 1189 i2c1_xfer: i2c1-xfer { 1190 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1191 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1192 }; 1193 }; 1194 1195 i2c2 { 1196 i2c2_xfer: i2c2-xfer { 1197 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1198 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1199 }; 1200 }; 1201 1202 i2c3 { 1203 i2c3_xfer: i2c3-xfer { 1204 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1205 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1206 }; 1207 }; 1208 1209 i2c4 { 1210 i2c4_xfer: i2c4-xfer { 1211 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1212 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1213 }; 1214 }; 1215 1216 i2c5 { 1217 i2c5_xfer: i2c5-xfer { 1218 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1219 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1220 }; 1221 }; 1222 1223 i2s0 { 1224 i2s0_bus: i2s0-bus { 1225 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1226 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1227 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1228 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1229 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1230 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1231 }; 1232 }; 1233 1234 lcdc0 { 1235 lcdc0_ctl: lcdc0-ctl { 1236 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1237 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1238 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1239 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1240 }; 1241 }; 1242 1243 sdmmc { 1244 sdmmc_clk: sdmmc-clk { 1245 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1246 }; 1247 1248 sdmmc_cmd: sdmmc-cmd { 1249 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1250 }; 1251 1252 sdmmc_cd: sdmcc-cd { 1253 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1254 }; 1255 1256 sdmmc_bus1: sdmmc-bus1 { 1257 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1258 }; 1259 1260 sdmmc_bus4: sdmmc-bus4 { 1261 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1262 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1263 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1264 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1265 }; 1266 }; 1267 1268 sdio0 { 1269 sdio0_bus1: sdio0-bus1 { 1270 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1271 }; 1272 1273 sdio0_bus4: sdio0-bus4 { 1274 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1275 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1276 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1277 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1278 }; 1279 1280 sdio0_cmd: sdio0-cmd { 1281 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1282 }; 1283 1284 sdio0_clk: sdio0-clk { 1285 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1286 }; 1287 1288 sdio0_cd: sdio0-cd { 1289 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1290 }; 1291 1292 sdio0_wp: sdio0-wp { 1293 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1294 }; 1295 1296 sdio0_pwr: sdio0-pwr { 1297 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1298 }; 1299 1300 sdio0_bkpwr: sdio0-bkpwr { 1301 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1302 }; 1303 1304 sdio0_int: sdio0-int { 1305 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1306 }; 1307 }; 1308 1309 sdio1 { 1310 sdio1_bus1: sdio1-bus1 { 1311 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; 1312 }; 1313 1314 sdio1_bus4: sdio1-bus4 { 1315 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, 1316 <3 25 RK_FUNC_4 &pcfg_pull_up>, 1317 <3 26 RK_FUNC_4 &pcfg_pull_up>, 1318 <3 27 RK_FUNC_4 &pcfg_pull_up>; 1319 }; 1320 1321 sdio1_cd: sdio1-cd { 1322 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; 1323 }; 1324 1325 sdio1_wp: sdio1-wp { 1326 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; 1327 }; 1328 1329 sdio1_bkpwr: sdio1-bkpwr { 1330 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; 1331 }; 1332 1333 sdio1_int: sdio1-int { 1334 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; 1335 }; 1336 1337 sdio1_cmd: sdio1-cmd { 1338 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; 1339 }; 1340 1341 sdio1_clk: sdio1-clk { 1342 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; 1343 }; 1344 1345 sdio1_pwr: sdio1-pwr { 1346 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; 1347 }; 1348 }; 1349 1350 emmc { 1351 emmc_clk: emmc-clk { 1352 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1353 }; 1354 1355 emmc_cmd: emmc-cmd { 1356 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1357 }; 1358 1359 emmc_pwr: emmc-pwr { 1360 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1361 }; 1362 1363 emmc_bus1: emmc-bus1 { 1364 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1365 }; 1366 1367 emmc_bus4: emmc-bus4 { 1368 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1369 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1370 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1371 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1372 }; 1373 1374 emmc_bus8: emmc-bus8 { 1375 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1376 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1377 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1378 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1379 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1380 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1381 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1382 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1383 }; 1384 }; 1385 1386 spi0 { 1387 spi0_clk: spi0-clk { 1388 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1389 }; 1390 spi0_cs0: spi0-cs0 { 1391 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1392 }; 1393 spi0_tx: spi0-tx { 1394 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1395 }; 1396 spi0_rx: spi0-rx { 1397 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1398 }; 1399 spi0_cs1: spi0-cs1 { 1400 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1401 }; 1402 }; 1403 spi1 { 1404 spi1_clk: spi1-clk { 1405 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1406 }; 1407 spi1_cs0: spi1-cs0 { 1408 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1409 }; 1410 spi1_rx: spi1-rx { 1411 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1412 }; 1413 spi1_tx: spi1-tx { 1414 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1415 }; 1416 }; 1417 1418 spi2 { 1419 spi2_cs1: spi2-cs1 { 1420 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1421 }; 1422 spi2_clk: spi2-clk { 1423 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1424 }; 1425 spi2_cs0: spi2-cs0 { 1426 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1427 }; 1428 spi2_rx: spi2-rx { 1429 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1430 }; 1431 spi2_tx: spi2-tx { 1432 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1433 }; 1434 }; 1435 1436 uart0 { 1437 uart0_xfer: uart0-xfer { 1438 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1439 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1440 }; 1441 1442 uart0_cts: uart0-cts { 1443 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; 1444 }; 1445 1446 uart0_rts: uart0-rts { 1447 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1448 }; 1449 }; 1450 1451 uart1 { 1452 uart1_xfer: uart1-xfer { 1453 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1454 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1455 }; 1456 1457 uart1_cts: uart1-cts { 1458 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; 1459 }; 1460 1461 uart1_rts: uart1-rts { 1462 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1463 }; 1464 }; 1465 1466 uart2 { 1467 uart2_xfer: uart2-xfer { 1468 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1469 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1470 }; 1471 /* no rts / cts for uart2 */ 1472 }; 1473 1474 uart3 { 1475 uart3_xfer: uart3-xfer { 1476 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1477 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1478 }; 1479 1480 uart3_cts: uart3-cts { 1481 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; 1482 }; 1483 1484 uart3_rts: uart3-rts { 1485 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1486 }; 1487 }; 1488 1489 uart4 { 1490 uart4_xfer: uart4-xfer { 1491 rockchip,pins = <5 12 3 &pcfg_pull_up>, 1492 <5 13 3 &pcfg_pull_none>; 1493 }; 1494 1495 uart4_cts: uart4-cts { 1496 rockchip,pins = <5 14 3 &pcfg_pull_none>; 1497 }; 1498 1499 uart4_rts: uart4-rts { 1500 rockchip,pins = <5 15 3 &pcfg_pull_none>; 1501 }; 1502 }; 1503 1504 tsadc { 1505 otp_out: otp-out { 1506 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1507 }; 1508 }; 1509 1510 pwm0 { 1511 pwm0_pin: pwm0-pin { 1512 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1513 }; 1514 }; 1515 1516 pwm1 { 1517 pwm1_pin: pwm1-pin { 1518 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1519 }; 1520 }; 1521 1522 pwm2 { 1523 pwm2_pin: pwm2-pin { 1524 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; 1525 }; 1526 }; 1527 1528 pwm3 { 1529 pwm3_pin: pwm3-pin { 1530 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; 1531 }; 1532 }; 1533 1534 gmac { 1535 rgmii_pins: rgmii-pins { 1536 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1537 <3 31 3 &pcfg_pull_none>, 1538 <3 26 3 &pcfg_pull_none>, 1539 <3 27 3 &pcfg_pull_none>, 1540 <3 28 3 &pcfg_pull_none_12ma>, 1541 <3 29 3 &pcfg_pull_none_12ma>, 1542 <3 24 3 &pcfg_pull_none_12ma>, 1543 <3 25 3 &pcfg_pull_none_12ma>, 1544 <4 0 3 &pcfg_pull_none>, 1545 <4 5 3 &pcfg_pull_none>, 1546 <4 6 3 &pcfg_pull_none>, 1547 <4 9 3 &pcfg_pull_none_12ma>, 1548 <4 4 3 &pcfg_pull_none_12ma>, 1549 <4 1 3 &pcfg_pull_none>, 1550 <4 3 3 &pcfg_pull_none>; 1551 }; 1552 1553 rmii_pins: rmii-pins { 1554 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1555 <3 31 3 &pcfg_pull_none>, 1556 <3 28 3 &pcfg_pull_none>, 1557 <3 29 3 &pcfg_pull_none>, 1558 <4 0 3 &pcfg_pull_none>, 1559 <4 5 3 &pcfg_pull_none>, 1560 <4 4 3 &pcfg_pull_none>, 1561 <4 1 3 &pcfg_pull_none>, 1562 <4 2 3 &pcfg_pull_none>, 1563 <4 3 3 &pcfg_pull_none>; 1564 }; 1565 }; 1566 1567 spdif { 1568 spdif_tx: spdif-tx { 1569 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1570 }; 1571 }; 1572 }; 1573 1574 power: power-controller { 1575 compatible = "rockchip,rk3288-power-controller"; 1576 #power-domain-cells = <1>; 1577 rockchip,pmu = <&pmu>; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 1581 pd_gpu { 1582 reg = <RK3288_PD_GPU>; 1583 clocks = <&cru ACLK_GPU>; 1584 }; 1585 1586 pd_hevc { 1587 reg = <RK3288_PD_HEVC>; 1588 clocks = <&cru ACLK_HEVC>, 1589 <&cru SCLK_HEVC_CABAC>, 1590 <&cru SCLK_HEVC_CORE>, 1591 <&cru HCLK_HEVC>; 1592 }; 1593 1594 pd_vio { 1595 reg = <RK3288_PD_VIO>; 1596 clocks = <&cru ACLK_IEP>, 1597 <&cru ACLK_ISP>, 1598 <&cru ACLK_RGA>, 1599 <&cru ACLK_VIP>, 1600 <&cru ACLK_VOP0>, 1601 <&cru ACLK_VOP1>, 1602 <&cru DCLK_VOP0>, 1603 <&cru DCLK_VOP1>, 1604 <&cru HCLK_IEP>, 1605 <&cru HCLK_ISP>, 1606 <&cru HCLK_RGA>, 1607 <&cru HCLK_VIP>, 1608 <&cru HCLK_VOP0>, 1609 <&cru HCLK_VOP1>, 1610 <&cru PCLK_EDP_CTRL>, 1611 <&cru PCLK_HDMI_CTRL>, 1612 <&cru PCLK_LVDS_PHY>, 1613 <&cru PCLK_MIPI_CSI>, 1614 <&cru PCLK_MIPI_DSI0>, 1615 <&cru PCLK_MIPI_DSI1>, 1616 <&cru SCLK_EDP_24M>, 1617 <&cru SCLK_EDP>, 1618 <&cru SCLK_HDMI_CEC>, 1619 <&cru SCLK_HDMI_HDCP>, 1620 <&cru SCLK_ISP_JPE>, 1621 <&cru SCLK_ISP>, 1622 <&cru SCLK_RGA>; 1623 }; 1624 1625 pd_video { 1626 reg = <RK3288_PD_VIDEO>; 1627 clocks = <&cru ACLK_VCODEC>, 1628 <&cru HCLK_VCODEC>; 1629 }; 1630 }; 1631}; 1632
