1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3288-cru.h> 10#include <dt-bindings/power-domain/rk3288.h> 11#include <dt-bindings/thermal/thermal.h> 12#include <dt-bindings/video/rk3288.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 gpio4 = &gpio4; 25 gpio5 = &gpio5; 26 gpio6 = &gpio6; 27 gpio7 = &gpio7; 28 gpio8 = &gpio8; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 mmc2 = &sdio0; 38 mmc3 = &sdio1; 39 mshc0 = &emmc; 40 mshc1 = &sdmmc; 41 mshc2 = &sdio0; 42 mshc3 = &sdio1; 43 serial0 = &uart0; 44 serial1 = &uart1; 45 serial2 = &uart2; 46 serial3 = &uart3; 47 serial4 = &uart4; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 enable-method = "rockchip,rk3066-smp"; 57 rockchip,pmu = <&pmu>; 58 59 cpu0: cpu@500 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a12"; 62 reg = <0x500>; 63 operating-points = < 64 /* KHz uV */ 65 1800000 1400000 66 1704000 1350000 67 1608000 1300000 68 1512000 1250000 69 1416000 1200000 70 1200000 1100000 71 1008000 1050000 72 816000 1000000 73 696000 950000 74 600000 900000 75 408000 900000 76 216000 900000 77 126000 900000 78 >; 79 #cooling-cells = <2>; /* min followed by max */ 80 clock-latency = <40000>; 81 clocks = <&cru ARMCLK>; 82 resets = <&cru SRST_CORE0>; 83 }; 84 cpu@501 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a12"; 87 reg = <0x501>; 88 resets = <&cru SRST_CORE1>; 89 }; 90 cpu@502 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a12"; 93 reg = <0x502>; 94 resets = <&cru SRST_CORE2>; 95 }; 96 cpu@503 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a12"; 99 reg = <0x503>; 100 resets = <&cru SRST_CORE3>; 101 }; 102 }; 103 104 amba { 105 compatible = "arm,amba-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 dmac_peri: dma-controller@ff250000 { 111 compatible = "arm,pl330", "arm,primecell"; 112 broken-no-flushp; 113 reg = <0xff250000 0x4000>; 114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 116 #dma-cells = <1>; 117 clocks = <&cru ACLK_DMAC2>; 118 clock-names = "apb_pclk"; 119 }; 120 121 dmac_bus_ns: dma-controller@ff600000 { 122 compatible = "arm,pl330", "arm,primecell"; 123 broken-no-flushp; 124 reg = <0xff600000 0x4000>; 125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 127 #dma-cells = <1>; 128 clocks = <&cru ACLK_DMAC1>; 129 clock-names = "apb_pclk"; 130 status = "disabled"; 131 }; 132 133 dmac_bus_s: dma-controller@ffb20000 { 134 compatible = "arm,pl330", "arm,primecell"; 135 broken-no-flushp; 136 reg = <0xffb20000 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 #dma-cells = <1>; 140 clocks = <&cru ACLK_DMAC1>; 141 clock-names = "apb_pclk"; 142 }; 143 }; 144 145 xin24m: oscillator { 146 compatible = "fixed-clock"; 147 clock-frequency = <24000000>; 148 clock-output-names = "xin24m"; 149 #clock-cells = <0>; 150 }; 151 152 timer { 153 arm,use-physical-timer; 154 compatible = "arm,armv7-timer"; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 159 clock-frequency = <24000000>; 160 always-on; 161 }; 162 163 display_subsystem: display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopl_out>, <&vopb_out>; 166 status = "disabled"; 167 168 route { 169 route_hdmi: route-hdmi { 170 status = "disabled"; 171 logo,uboot = "logo.bmp"; 172 logo,kernel = "logo_kernel.bmp"; 173 logo,mode = "center"; 174 charge_logo,mode = "center"; 175 connect = <&vopb_out_hdmi>; 176 }; 177 178 route_edp: route-edp { 179 status = "disabled"; 180 logo,uboot = "logo.bmp"; 181 logo,kernel = "logo_kernel.bmp"; 182 logo,mode = "center"; 183 charge_logo,mode = "center"; 184 connect = <&vopl_out_edp>; 185 }; 186 187 route_dsi0: route-dsi0 { 188 status = "disabled"; 189 logo,uboot = "logo.bmp"; 190 logo,kernel = "logo_kernel.bmp"; 191 logo,mode = "center"; 192 charge_logo,mode = "center"; 193 connect = <&vopl_out_dsi0>; 194 }; 195 196 route_lvds: route-lvds { 197 status = "disabled"; 198 logo,uboot = "logo.bmp"; 199 logo,kernel = "logo_kernel.bmp"; 200 logo,mode = "center"; 201 charge_logo,mode = "center"; 202 connect = <&vopl_out_lvds>; 203 }; 204 }; 205 }; 206 207 sdmmc: dwmmc@ff0c0000 { 208 compatible = "rockchip,rk3288-dw-mshc"; 209 max-frequency = <150000000>; 210 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 211 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 212 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 213 fifo-depth = <0x100>; 214 cd-gpios = <&gpio6 RK_PC6 GPIO_ACTIVE_HIGH>; 215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 216 reg = <0xff0c0000 0x4000>; 217 status = "disabled"; 218 }; 219 220 sdio0: dwmmc@ff0d0000 { 221 compatible = "rockchip,rk3288-dw-mshc"; 222 max-frequency = <150000000>; 223 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 224 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 225 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 226 fifo-depth = <0x100>; 227 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 228 reg = <0xff0d0000 0x4000>; 229 status = "disabled"; 230 }; 231 232 sdio1: dwmmc@ff0e0000 { 233 compatible = "rockchip,rk3288-dw-mshc"; 234 max-frequency = <150000000>; 235 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 236 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 237 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 238 fifo-depth = <0x100>; 239 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 240 reg = <0xff0e0000 0x4000>; 241 status = "disabled"; 242 }; 243 244 emmc: dwmmc@ff0f0000 { 245 compatible = "rockchip,rk3288-dw-mshc"; 246 max-frequency = <150000000>; 247 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 248 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 249 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 250 fifo-depth = <0x100>; 251 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 252 reg = <0xff0f0000 0x4000>; 253 status = "disabled"; 254 }; 255 256 saradc: saradc@ff100000 { 257 compatible = "rockchip,saradc"; 258 reg = <0xff100000 0x100>; 259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 260 #io-channel-cells = <1>; 261 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 262 clock-names = "saradc", "apb_pclk"; 263 status = "disabled"; 264 }; 265 266 spi0: spi@ff110000 { 267 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 268 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 269 clock-names = "spiclk", "apb_pclk"; 270 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 271 dma-names = "tx", "rx"; 272 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 275 reg = <0xff110000 0x1000>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 status = "disabled"; 279 }; 280 281 spi1: spi@ff120000 { 282 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 283 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 284 clock-names = "spiclk", "apb_pclk"; 285 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 286 dma-names = "tx", "rx"; 287 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 290 reg = <0xff120000 0x1000>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 status = "disabled"; 294 }; 295 296 spi2: spi@ff130000 { 297 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 298 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 299 clock-names = "spiclk", "apb_pclk"; 300 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 301 dma-names = "tx", "rx"; 302 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 305 reg = <0xff130000 0x1000>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 311 i2c1: i2c@ff140000 { 312 compatible = "rockchip,rk3288-i2c"; 313 reg = <0xff140000 0x1000>; 314 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 clock-names = "i2c"; 318 clocks = <&cru PCLK_I2C1>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&i2c1_xfer>; 321 status = "disabled"; 322 }; 323 324 i2c3: i2c@ff150000 { 325 compatible = "rockchip,rk3288-i2c"; 326 reg = <0xff150000 0x1000>; 327 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 clock-names = "i2c"; 331 clocks = <&cru PCLK_I2C3>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&i2c3_xfer>; 334 status = "disabled"; 335 }; 336 337 i2c4: i2c@ff160000 { 338 compatible = "rockchip,rk3288-i2c"; 339 reg = <0xff160000 0x1000>; 340 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 clock-names = "i2c"; 344 clocks = <&cru PCLK_I2C4>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&i2c4_xfer>; 347 status = "disabled"; 348 }; 349 350 i2c5: i2c@ff170000 { 351 compatible = "rockchip,rk3288-i2c"; 352 reg = <0xff170000 0x1000>; 353 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 clock-names = "i2c"; 357 clocks = <&cru PCLK_I2C5>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&i2c5_xfer>; 360 status = "disabled"; 361 }; 362 363 uart0: serial@ff180000 { 364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 365 reg = <0xff180000 0x100>; 366 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 367 reg-shift = <2>; 368 reg-io-width = <4>; 369 clock-frequency = <24000000>; 370 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 371 clock-names = "baudclk", "apb_pclk"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&uart0_xfer>; 374 status = "disabled"; 375 }; 376 377 uart1: serial@ff190000 { 378 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 379 reg = <0xff190000 0x100>; 380 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 381 reg-shift = <2>; 382 reg-io-width = <4>; 383 clock-frequency = <24000000>; 384 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 385 clock-names = "baudclk", "apb_pclk"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&uart1_xfer>; 388 status = "disabled"; 389 }; 390 391 uart2: serial@ff690000 { 392 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 393 reg = <0xff690000 0x100>; 394 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 395 reg-shift = <2>; 396 reg-io-width = <4>; 397 clock-frequency = <24000000>; 398 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 399 clock-names = "baudclk", "apb_pclk"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&uart2_xfer>; 402 status = "disabled"; 403 }; 404 uart3: serial@ff1b0000 { 405 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 406 reg = <0xff1b0000 0x100>; 407 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 408 reg-shift = <2>; 409 reg-io-width = <4>; 410 clock-frequency = <24000000>; 411 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 412 clock-names = "baudclk", "apb_pclk"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&uart3_xfer>; 415 status = "disabled"; 416 }; 417 418 uart4: serial@ff1c0000 { 419 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 420 reg = <0xff1c0000 0x100>; 421 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 422 reg-shift = <2>; 423 reg-io-width = <4>; 424 clock-frequency = <24000000>; 425 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 426 clock-names = "baudclk", "apb_pclk"; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&uart4_xfer>; 429 status = "disabled"; 430 }; 431 432 thermal: thermal-zones { 433 #include "rk3288-thermal.dtsi" 434 }; 435 436 tsadc: tsadc@ff280000 { 437 compatible = "rockchip,rk3288-tsadc"; 438 reg = <0xff280000 0x100>; 439 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 441 clock-names = "tsadc", "apb_pclk"; 442 resets = <&cru SRST_TSADC>; 443 reset-names = "tsadc-apb"; 444 pinctrl-names = "otp_out"; 445 pinctrl-0 = <&otp_out>; 446 #thermal-sensor-cells = <1>; 447 hw-shut-temp = <125000>; 448 status = "disabled"; 449 }; 450 451 gmac: ethernet@ff290000 { 452 compatible = "rockchip,rk3288-gmac"; 453 reg = <0xff290000 0x10000>; 454 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 455 interrupt-names = "macirq"; 456 rockchip,grf = <&grf>; 457 clocks = <&cru SCLK_MAC>, 458 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 459 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 460 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 461 clock-names = "stmmaceth", 462 "mac_clk_rx", "mac_clk_tx", 463 "clk_mac_ref", "clk_mac_refout", 464 "aclk_mac", "pclk_mac"; 465 }; 466 467 usb_host0_ehci: usb@ff500000 { 468 compatible = "generic-ehci"; 469 reg = <0xff500000 0x100>; 470 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cru HCLK_USBHOST0>; 472 clock-names = "usbhost"; 473 phys = <&usbphy1>; 474 phy-names = "usb"; 475 status = "disabled"; 476 }; 477 478 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 479 480 usb_host1: usb@ff540000 { 481 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 482 "snps,dwc2"; 483 reg = <0xff540000 0x40000>; 484 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cru HCLK_USBHOST1>; 486 clock-names = "otg"; 487 phys = <&usbphy2>; 488 phy-names = "usb2-phy"; 489 status = "disabled"; 490 }; 491 492 usb_otg: usb@ff580000 { 493 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 494 "snps,dwc2"; 495 reg = <0xff580000 0x40000>; 496 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cru HCLK_OTG0>; 498 clock-names = "otg"; 499 dr_mode = "otg"; 500 phys = <&usbphy0>; 501 phy-names = "usb2-phy"; 502 status = "disabled"; 503 }; 504 505 usb_hsic: usb@ff5c0000 { 506 compatible = "generic-ehci"; 507 reg = <0xff5c0000 0x100>; 508 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cru HCLK_HSIC>; 510 clock-names = "usbhost"; 511 status = "disabled"; 512 }; 513 514 dmc: dmc@ff610000 { 515 compatible = "rockchip,rk3288-dmc", "syscon"; 516 rockchip,cru = <&cru>; 517 rockchip,grf = <&grf>; 518 rockchip,pmu = <&pmu>; 519 rockchip,sgrf = <&sgrf>; 520 rockchip,noc = <&noc>; 521 reg = <0xff610000 0x3fc 522 0xff620000 0x294 523 0xff630000 0x3fc 524 0xff640000 0x294>; 525 rockchip,sram = <&ddr_sram>; 526 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, 527 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, 528 <&cru ARMCLK>; 529 clock-names = "pclk_ddrupctl0", "pclk_publ0", 530 "pclk_ddrupctl1", "pclk_publ1", 531 "arm_clk"; 532 }; 533 534 i2c0: i2c@ff650000 { 535 compatible = "rockchip,rk3288-i2c"; 536 reg = <0xff650000 0x1000>; 537 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clock-names = "i2c"; 541 clocks = <&cru PCLK_I2C0>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&i2c0_xfer>; 544 status = "disabled"; 545 }; 546 547 i2c2: i2c@ff660000 { 548 compatible = "rockchip,rk3288-i2c"; 549 reg = <0xff660000 0x1000>; 550 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 clock-names = "i2c"; 554 clocks = <&cru PCLK_I2C2>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&i2c2_xfer>; 557 status = "disabled"; 558 }; 559 560 pwm0: pwm@ff680000 { 561 compatible = "rockchip,rk3288-pwm"; 562 reg = <0xff680000 0x10>; 563 #pwm-cells = <3>; 564 pinctrl-names = "active"; 565 pinctrl-0 = <&pwm0_pin>; 566 clocks = <&cru PCLK_PWM>; 567 clock-names = "pwm"; 568 rockchip,grf = <&grf>; 569 status = "disabled"; 570 }; 571 572 pwm1: pwm@ff680010 { 573 compatible = "rockchip,rk3288-pwm"; 574 reg = <0xff680010 0x10>; 575 #pwm-cells = <3>; 576 pinctrl-names = "active"; 577 pinctrl-0 = <&pwm1_pin>; 578 clocks = <&cru PCLK_PWM>; 579 clock-names = "pwm"; 580 rockchip,grf = <&grf>; 581 status = "disabled"; 582 }; 583 584 pwm2: pwm@ff680020 { 585 compatible = "rockchip,rk3288-pwm"; 586 reg = <0xff680020 0x10>; 587 #pwm-cells = <3>; 588 pinctrl-names = "active"; 589 pinctrl-0 = <&pwm2_pin>; 590 clocks = <&cru PCLK_PWM>; 591 clock-names = "pwm"; 592 rockchip,grf = <&grf>; 593 status = "disabled"; 594 }; 595 596 pwm3: pwm@ff680030 { 597 compatible = "rockchip,rk3288-pwm"; 598 reg = <0xff680030 0x10>; 599 #pwm-cells = <2>; 600 pinctrl-names = "active"; 601 pinctrl-0 = <&pwm3_pin>; 602 clocks = <&cru PCLK_PWM>; 603 clock-names = "pwm"; 604 rockchip,grf = <&grf>; 605 status = "disabled"; 606 }; 607 608 bus_intmem@ff700000 { 609 compatible = "mmio-sram"; 610 reg = <0xff700000 0x18000>; 611 #address-cells = <1>; 612 #size-cells = <1>; 613 ranges = <0 0xff700000 0x18000>; 614 smp-sram@0 { 615 compatible = "rockchip,rk3066-smp-sram"; 616 reg = <0x00 0x10>; 617 }; 618 ddr_sram: ddr-sram@1000 { 619 compatible = "rockchip,rk3288-ddr-sram"; 620 reg = <0x1000 0x4000>; 621 }; 622 }; 623 624 sram@ff720000 { 625 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 626 reg = <0xff720000 0x1000>; 627 }; 628 629 pmu: power-management@ff730000 { 630 compatible = "rockchip,rk3288-pmu", "syscon"; 631 reg = <0xff730000 0x100>; 632 }; 633 634 sgrf: syscon@ff740000 { 635 compatible = "rockchip,rk3288-sgrf", "syscon"; 636 reg = <0xff740000 0x1000>; 637 }; 638 639 cru: clock-controller@ff760000 { 640 compatible = "rockchip,rk3288-cru"; 641 reg = <0xff760000 0x1000>; 642 rockchip,grf = <&grf>; 643 #clock-cells = <1>; 644 #reset-cells = <1>; 645 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 646 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 647 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 648 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 649 <&cru PCLK_PERI>; 650 assigned-clock-rates = <594000000>, <400000000>, 651 <500000000>, <300000000>, 652 <150000000>, <75000000>, 653 <300000000>, <150000000>, 654 <75000000>; 655 }; 656 657 grf: syscon@ff770000 { 658 compatible = "rockchip,rk3288-grf", "syscon"; 659 reg = <0xff770000 0x1000>; 660 }; 661 662 wdt: watchdog@ff800000 { 663 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 664 reg = <0xff800000 0x100>; 665 clocks = <&cru PCLK_WDT>; 666 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 667 status = "disabled"; 668 }; 669 670 spdif: sound@ff88b0000 { 671 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 672 reg = <0xff8b0000 0x10000>; 673 #sound-dai-cells = <0>; 674 clock-names = "hclk", "mclk"; 675 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 676 dmas = <&dmac_bus_s 3>; 677 dma-names = "tx"; 678 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&spdif_tx>; 681 rockchip,grf = <&grf>; 682 status = "disabled"; 683 }; 684 685 i2s: i2s@ff890000 { 686 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 687 reg = <0xff890000 0x10000>; 688 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 692 dma-names = "tx", "rx"; 693 clock-names = "i2s_hclk", "i2s_clk"; 694 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&i2s0_bus>; 697 status = "disabled"; 698 }; 699 700 crypto: crypto@ff8a0000 { 701 compatible = "rockchip,rk3288-crypto"; 702 reg = <0xff8a0000 0x10000>; 703 clock-names = "sclk_crypto"; 704 clocks = <&cru SCLK_CRYPTO>; 705 status = "disabled"; 706 }; 707 708 vopb: vop@ff930000 { 709 compatible = "rockchip,rk3288-vop-big"; 710 reg = <0xff930000 0x19c>; 711 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 713 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 714 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 715 reset-names = "axi", "ahb", "dclk"; 716 iommus = <&vopb_mmu>; 717 power-domains = <&power RK3288_PD_VIO>; 718 status = "disabled"; 719 vopb_out: port { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 vopb_out_edp: endpoint@0 { 723 reg = <0>; 724 remote-endpoint = <&edp_in_vopb>; 725 }; 726 vopb_out_hdmi: endpoint@1 { 727 reg = <1>; 728 remote-endpoint = <&hdmi_in_vopb>; 729 }; 730 vopb_out_lvds: endpoint@2 { 731 reg = <2>; 732 remote-endpoint = <&lvds_in_vopb>; 733 }; 734 vopb_out_dsi0: endpoint@3 { 735 reg = <3>; 736 remote-endpoint = <&dsi0_in_vopb>; 737 }; 738 739 }; 740 }; 741 742 vopb_mmu: iommu@ff930300 { 743 compatible = "rockchip,iommu"; 744 reg = <0xff930300 0x100>; 745 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 746 interrupt-names = "vopb_mmu"; 747 power-domains = <&power RK3288_PD_VIO>; 748 #iommu-cells = <0>; 749 status = "disabled"; 750 }; 751 752 vopl: vop@ff940000 { 753 compatible = "rockchip,rk3288-vop-lit"; 754 reg = <0xff940000 0x19c>; 755 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 757 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 758 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 759 reset-names = "axi", "ahb", "dclk"; 760 iommus = <&vopl_mmu>; 761 power-domains = <&power RK3288_PD_VIO>; 762 status = "disabled"; 763 vopl_out: port { 764 #address-cells = <1>; 765 #size-cells = <0>; 766 vopl_out_edp: endpoint@0 { 767 reg = <0>; 768 remote-endpoint = <&edp_in_vopl>; 769 }; 770 vopl_out_hdmi: endpoint@1 { 771 reg = <1>; 772 remote-endpoint = <&hdmi_in_vopl>; 773 }; 774 vopl_out_lvds: endpoint@2 { 775 reg = <2>; 776 remote-endpoint = <&lvds_in_vopl>; 777 }; 778 vopl_out_dsi0: endpoint@3 { 779 reg = <3>; 780 remote-endpoint = <&dsi0_in_vopl>; 781 }; 782 783 }; 784 }; 785 786 vopl_mmu: iommu@ff940300 { 787 compatible = "rockchip,iommu"; 788 reg = <0xff940300 0x100>; 789 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 790 interrupt-names = "vopl_mmu"; 791 power-domains = <&power RK3288_PD_VIO>; 792 #iommu-cells = <0>; 793 status = "disabled"; 794 }; 795 796 edp: edp@ff970000 { 797 compatible = "rockchip,rk3288-dp"; 798 reg = <0xff970000 0x4000>; 799 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; 801 rockchip,grf = <&grf>; 802 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; 803 resets = <&cru 111>; 804 reset-names = "edp"; 805 power-domains = <&power RK3288_PD_VIO>; 806 status = "disabled"; 807 ports { 808 #address-cells = <1>; 809 #size-cells = <0>; 810 811 edp_in: port { 812 #address-cells = <1>; 813 #size-cells = <0>; 814 edp_in_vopb: endpoint@0 { 815 reg = <0>; 816 remote-endpoint = <&vopb_out_edp>; 817 }; 818 edp_in_vopl: endpoint@1 { 819 reg = <1>; 820 remote-endpoint = <&vopl_out_edp>; 821 }; 822 }; 823 }; 824 }; 825 826 hdmi: hdmi@ff980000 { 827 compatible = "rockchip,rk3288-dw-hdmi"; 828 reg = <0xff980000 0x20000>; 829 reg-io-width = <4>; 830 rockchip,grf = <&grf>; 831 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 833 clock-names = "iahb", "isfr"; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&hdmi_ddc>; 836 status = "disabled"; 837 ports { 838 hdmi_in: port { 839 #address-cells = <1>; 840 #size-cells = <0>; 841 hdmi_in_vopb: endpoint@0 { 842 reg = <0>; 843 remote-endpoint = <&vopb_out_hdmi>; 844 }; 845 hdmi_in_vopl: endpoint@1 { 846 reg = <1>; 847 remote-endpoint = <&vopl_out_hdmi>; 848 }; 849 }; 850 }; 851 }; 852 853 lvds: lvds@ff96c000 { 854 compatible = "rockchip,rk3288-lvds"; 855 reg = <0xff96c000 0x4000>; 856 clocks = <&cru PCLK_LVDS_PHY>; 857 clock-names = "pclk_lvds"; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&lcdc0_ctl>; 860 rockchip,grf = <&grf>; 861 status = "disabled"; 862 ports { 863 #address-cells = <1>; 864 #size-cells = <0>; 865 lvds_in: port@0 { 866 reg = <0>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 lvds_in_vopb: endpoint@0 { 870 reg = <0>; 871 remote-endpoint = <&vopb_out_lvds>; 872 }; 873 lvds_in_vopl: endpoint@1 { 874 reg = <1>; 875 remote-endpoint = <&vopl_out_lvds>; 876 }; 877 }; 878 }; 879 }; 880 881 dsi0: mipi@ff960000 { 882 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 883 reg = <0xff960000 0x4000>; 884 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 886 clock-names = "ref", "pclk"; 887 resets = <&cru SRST_MIPIDSI0>; 888 reset-names = "apb"; 889 power-domains = <&power RK3288_PD_VIO>; 890 rockchip,grf = <&grf>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 status = "disabled"; 894 ports { 895 #address-cells = <1>; 896 #size-cells = <0>; 897 reg = <1>; 898 mipi_in: port { 899 #address-cells = <1>; 900 #size-cells = <0>; 901 dsi0_in_vopb: endpoint@0 { 902 reg = <0>; 903 remote-endpoint = <&vopb_out_dsi0>; 904 }; 905 dsi0_in_vopl: endpoint@1 { 906 reg = <1>; 907 remote-endpoint = <&vopl_out_dsi0>; 908 }; 909 }; 910 }; 911 }; 912 913 hdmi_audio: hdmi_audio { 914 compatible = "rockchip,rk3288-hdmi-audio"; 915 i2s-controller = <&i2s>; 916 status = "disable"; 917 }; 918 919 vpu: video-codec@ff9a0000 { 920 compatible = "rockchip,rk3288-vpu"; 921 reg = <0xff9a0000 0x800>; 922 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 924 interrupt-names = "vepu", "vdpu"; 925 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 926 clock-names = "aclk_vcodec", "hclk_vcodec"; 927 power-domains = <&power RK3288_PD_VIDEO>; 928 iommus = <&vpu_mmu>; 929 }; 930 931 vpu_mmu: iommu@ff9a0800 { 932 compatible = "rockchip,iommu"; 933 reg = <0xff9a0800 0x100>; 934 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 935 interrupt-names = "vpu_mmu"; 936 power-domains = <&power RK3288_PD_VIDEO>; 937 #iommu-cells = <0>; 938 }; 939 940 gpu: gpu@ffa30000 { 941 compatible = "arm,malit764", 942 "arm,malit76x", 943 "arm,malit7xx", 944 "arm,mali-midgard"; 945 reg = <0xffa30000 0x10000>; 946 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "JOB", "MMU", "GPU"; 950 clocks = <&cru ACLK_GPU>; 951 clock-names = "aclk_gpu"; 952 operating-points = < 953 /* KHz uV */ 954 100000 950000 955 200000 950000 956 300000 1000000 957 400000 1100000 958 /* 500000 1200000 - See crosbug.com/p/33857 */ 959 600000 1250000 960 >; 961 power-domains = <&power RK3288_PD_GPU>; 962 status = "disabled"; 963 }; 964 965 noc: syscon@ffac0000 { 966 compatible = "rockchip,rk3288-noc", "syscon"; 967 reg = <0xffac0000 0x2000>; 968 }; 969 970 efuse: efuse@ffb40000 { 971 compatible = "rockchip,rk3288-efuse"; 972 reg = <0xffb40000 0x10000>; 973 status = "disabled"; 974 }; 975 976 gic: interrupt-controller@ffc01000 { 977 compatible = "arm,gic-400"; 978 interrupt-controller; 979 #interrupt-cells = <3>; 980 #address-cells = <0>; 981 982 reg = <0xffc01000 0x1000>, 983 <0xffc02000 0x1000>, 984 <0xffc04000 0x2000>, 985 <0xffc06000 0x2000>; 986 interrupts = <GIC_PPI 9 0xf04>; 987 }; 988 989 cpuidle: cpuidle { 990 compatible = "rockchip,rk3288-cpuidle"; 991 }; 992 993 usbphy: phy { 994 compatible = "rockchip,rk3288-usb-phy"; 995 rockchip,grf = <&grf>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 status = "disabled"; 999 1000 usbphy0: usb-phy0 { 1001 #phy-cells = <0>; 1002 reg = <0x320>; 1003 clocks = <&cru SCLK_OTGPHY0>; 1004 clock-names = "phyclk"; 1005 }; 1006 1007 usbphy1: usb-phy1 { 1008 #phy-cells = <0>; 1009 reg = <0x334>; 1010 clocks = <&cru SCLK_OTGPHY1>; 1011 clock-names = "phyclk"; 1012 }; 1013 1014 usbphy2: usb-phy2 { 1015 #phy-cells = <0>; 1016 reg = <0x348>; 1017 clocks = <&cru SCLK_OTGPHY2>; 1018 clock-names = "phyclk"; 1019 }; 1020 }; 1021 1022 pinctrl: pinctrl { 1023 compatible = "rockchip,rk3288-pinctrl"; 1024 rockchip,grf = <&grf>; 1025 rockchip,pmu = <&pmu>; 1026 #address-cells = <1>; 1027 #size-cells = <1>; 1028 ranges; 1029 1030 gpio0: gpio0@ff750000 { 1031 compatible = "rockchip,gpio-bank"; 1032 reg = <0xff750000 0x100>; 1033 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cru PCLK_GPIO0>; 1035 1036 gpio-controller; 1037 #gpio-cells = <2>; 1038 1039 interrupt-controller; 1040 #interrupt-cells = <2>; 1041 }; 1042 1043 gpio1: gpio1@ff780000 { 1044 compatible = "rockchip,gpio-bank"; 1045 reg = <0xff780000 0x100>; 1046 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&cru PCLK_GPIO1>; 1048 1049 gpio-controller; 1050 #gpio-cells = <2>; 1051 1052 interrupt-controller; 1053 #interrupt-cells = <2>; 1054 }; 1055 1056 gpio2: gpio2@ff790000 { 1057 compatible = "rockchip,gpio-bank"; 1058 reg = <0xff790000 0x100>; 1059 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&cru PCLK_GPIO2>; 1061 1062 gpio-controller; 1063 #gpio-cells = <2>; 1064 1065 interrupt-controller; 1066 #interrupt-cells = <2>; 1067 }; 1068 1069 gpio3: gpio3@ff7a0000 { 1070 compatible = "rockchip,gpio-bank"; 1071 reg = <0xff7a0000 0x100>; 1072 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&cru PCLK_GPIO3>; 1074 1075 gpio-controller; 1076 #gpio-cells = <2>; 1077 1078 interrupt-controller; 1079 #interrupt-cells = <2>; 1080 }; 1081 1082 gpio4: gpio4@ff7b0000 { 1083 compatible = "rockchip,gpio-bank"; 1084 reg = <0xff7b0000 0x100>; 1085 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&cru PCLK_GPIO4>; 1087 1088 gpio-controller; 1089 #gpio-cells = <2>; 1090 1091 interrupt-controller; 1092 #interrupt-cells = <2>; 1093 }; 1094 1095 gpio5: gpio5@ff7c0000 { 1096 compatible = "rockchip,gpio-bank"; 1097 reg = <0xff7c0000 0x100>; 1098 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cru PCLK_GPIO5>; 1100 1101 gpio-controller; 1102 #gpio-cells = <2>; 1103 1104 interrupt-controller; 1105 #interrupt-cells = <2>; 1106 }; 1107 1108 gpio6: gpio6@ff7d0000 { 1109 compatible = "rockchip,gpio-bank"; 1110 reg = <0xff7d0000 0x100>; 1111 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&cru PCLK_GPIO6>; 1113 1114 gpio-controller; 1115 #gpio-cells = <2>; 1116 1117 interrupt-controller; 1118 #interrupt-cells = <2>; 1119 }; 1120 1121 gpio7: gpio7@ff7e0000 { 1122 compatible = "rockchip,gpio-bank"; 1123 reg = <0xff7e0000 0x100>; 1124 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&cru PCLK_GPIO7>; 1126 1127 gpio-controller; 1128 #gpio-cells = <2>; 1129 1130 interrupt-controller; 1131 #interrupt-cells = <2>; 1132 }; 1133 1134 gpio8: gpio8@ff7f0000 { 1135 compatible = "rockchip,gpio-bank"; 1136 reg = <0xff7f0000 0x100>; 1137 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&cru PCLK_GPIO8>; 1139 1140 gpio-controller; 1141 #gpio-cells = <2>; 1142 1143 interrupt-controller; 1144 #interrupt-cells = <2>; 1145 }; 1146 1147 hdmi { 1148 hdmi_ddc: hdmi-ddc { 1149 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, 1150 <7 20 RK_FUNC_2 &pcfg_pull_none>; 1151 }; 1152 }; 1153 1154 pcfg_pull_up: pcfg-pull-up { 1155 bias-pull-up; 1156 }; 1157 1158 pcfg_pull_down: pcfg-pull-down { 1159 bias-pull-down; 1160 }; 1161 1162 pcfg_pull_none: pcfg-pull-none { 1163 bias-disable; 1164 }; 1165 1166 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1167 bias-disable; 1168 drive-strength = <12>; 1169 }; 1170 1171 sleep { 1172 global_pwroff: global-pwroff { 1173 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1174 }; 1175 1176 ddrio_pwroff: ddrio-pwroff { 1177 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1178 }; 1179 1180 ddr0_retention: ddr0-retention { 1181 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1182 }; 1183 1184 ddr1_retention: ddr1-retention { 1185 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1186 }; 1187 }; 1188 1189 i2c0 { 1190 i2c0_xfer: i2c0-xfer { 1191 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1192 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1193 }; 1194 }; 1195 1196 i2c1 { 1197 i2c1_xfer: i2c1-xfer { 1198 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1199 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1200 }; 1201 }; 1202 1203 i2c2 { 1204 i2c2_xfer: i2c2-xfer { 1205 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1206 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1207 }; 1208 }; 1209 1210 i2c3 { 1211 i2c3_xfer: i2c3-xfer { 1212 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1213 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1214 }; 1215 }; 1216 1217 i2c4 { 1218 i2c4_xfer: i2c4-xfer { 1219 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1220 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1221 }; 1222 }; 1223 1224 i2c5 { 1225 i2c5_xfer: i2c5-xfer { 1226 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1227 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1228 }; 1229 }; 1230 1231 i2s0 { 1232 i2s0_bus: i2s0-bus { 1233 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1234 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1235 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1236 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1237 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1238 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1239 }; 1240 }; 1241 1242 lcdc0 { 1243 lcdc0_ctl: lcdc0-ctl { 1244 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1245 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1246 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1247 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1248 }; 1249 }; 1250 1251 sdmmc { 1252 sdmmc_clk: sdmmc-clk { 1253 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1254 }; 1255 1256 sdmmc_cmd: sdmmc-cmd { 1257 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1258 }; 1259 1260 sdmmc_cd: sdmcc-cd { 1261 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1262 }; 1263 1264 sdmmc_bus1: sdmmc-bus1 { 1265 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1266 }; 1267 1268 sdmmc_bus4: sdmmc-bus4 { 1269 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1270 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1271 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1272 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1273 }; 1274 }; 1275 1276 sdio0 { 1277 sdio0_bus1: sdio0-bus1 { 1278 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1279 }; 1280 1281 sdio0_bus4: sdio0-bus4 { 1282 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1283 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1284 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1285 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1286 }; 1287 1288 sdio0_cmd: sdio0-cmd { 1289 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1290 }; 1291 1292 sdio0_clk: sdio0-clk { 1293 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1294 }; 1295 1296 sdio0_cd: sdio0-cd { 1297 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1298 }; 1299 1300 sdio0_wp: sdio0-wp { 1301 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1302 }; 1303 1304 sdio0_pwr: sdio0-pwr { 1305 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1306 }; 1307 1308 sdio0_bkpwr: sdio0-bkpwr { 1309 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1310 }; 1311 1312 sdio0_int: sdio0-int { 1313 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1314 }; 1315 }; 1316 1317 sdio1 { 1318 sdio1_bus1: sdio1-bus1 { 1319 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; 1320 }; 1321 1322 sdio1_bus4: sdio1-bus4 { 1323 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, 1324 <3 25 RK_FUNC_4 &pcfg_pull_up>, 1325 <3 26 RK_FUNC_4 &pcfg_pull_up>, 1326 <3 27 RK_FUNC_4 &pcfg_pull_up>; 1327 }; 1328 1329 sdio1_cd: sdio1-cd { 1330 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; 1331 }; 1332 1333 sdio1_wp: sdio1-wp { 1334 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; 1335 }; 1336 1337 sdio1_bkpwr: sdio1-bkpwr { 1338 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; 1339 }; 1340 1341 sdio1_int: sdio1-int { 1342 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; 1343 }; 1344 1345 sdio1_cmd: sdio1-cmd { 1346 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; 1347 }; 1348 1349 sdio1_clk: sdio1-clk { 1350 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; 1351 }; 1352 1353 sdio1_pwr: sdio1-pwr { 1354 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; 1355 }; 1356 }; 1357 1358 emmc { 1359 emmc_clk: emmc-clk { 1360 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1361 }; 1362 1363 emmc_cmd: emmc-cmd { 1364 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1365 }; 1366 1367 emmc_pwr: emmc-pwr { 1368 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1369 }; 1370 1371 emmc_bus1: emmc-bus1 { 1372 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1373 }; 1374 1375 emmc_bus4: emmc-bus4 { 1376 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1377 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1378 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1379 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1380 }; 1381 1382 emmc_bus8: emmc-bus8 { 1383 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1384 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1385 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1386 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1387 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1388 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1389 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1390 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1391 }; 1392 }; 1393 1394 spi0 { 1395 spi0_clk: spi0-clk { 1396 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1397 }; 1398 spi0_cs0: spi0-cs0 { 1399 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1400 }; 1401 spi0_tx: spi0-tx { 1402 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1403 }; 1404 spi0_rx: spi0-rx { 1405 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1406 }; 1407 spi0_cs1: spi0-cs1 { 1408 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1409 }; 1410 }; 1411 spi1 { 1412 spi1_clk: spi1-clk { 1413 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1414 }; 1415 spi1_cs0: spi1-cs0 { 1416 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1417 }; 1418 spi1_rx: spi1-rx { 1419 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1420 }; 1421 spi1_tx: spi1-tx { 1422 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1423 }; 1424 }; 1425 1426 spi2 { 1427 spi2_cs1: spi2-cs1 { 1428 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1429 }; 1430 spi2_clk: spi2-clk { 1431 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1432 }; 1433 spi2_cs0: spi2-cs0 { 1434 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1435 }; 1436 spi2_rx: spi2-rx { 1437 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1438 }; 1439 spi2_tx: spi2-tx { 1440 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1441 }; 1442 }; 1443 1444 uart0 { 1445 uart0_xfer: uart0-xfer { 1446 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1447 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1448 }; 1449 1450 uart0_cts: uart0-cts { 1451 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; 1452 }; 1453 1454 uart0_rts: uart0-rts { 1455 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1456 }; 1457 }; 1458 1459 uart1 { 1460 uart1_xfer: uart1-xfer { 1461 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1462 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1463 }; 1464 1465 uart1_cts: uart1-cts { 1466 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; 1467 }; 1468 1469 uart1_rts: uart1-rts { 1470 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1471 }; 1472 }; 1473 1474 uart2 { 1475 uart2_xfer: uart2-xfer { 1476 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1477 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1478 }; 1479 /* no rts / cts for uart2 */ 1480 }; 1481 1482 uart3 { 1483 uart3_xfer: uart3-xfer { 1484 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1485 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1486 }; 1487 1488 uart3_cts: uart3-cts { 1489 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; 1490 }; 1491 1492 uart3_rts: uart3-rts { 1493 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1494 }; 1495 }; 1496 1497 uart4 { 1498 uart4_xfer: uart4-xfer { 1499 rockchip,pins = <5 12 3 &pcfg_pull_up>, 1500 <5 13 3 &pcfg_pull_none>; 1501 }; 1502 1503 uart4_cts: uart4-cts { 1504 rockchip,pins = <5 14 3 &pcfg_pull_none>; 1505 }; 1506 1507 uart4_rts: uart4-rts { 1508 rockchip,pins = <5 15 3 &pcfg_pull_none>; 1509 }; 1510 }; 1511 1512 tsadc { 1513 otp_out: otp-out { 1514 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1515 }; 1516 }; 1517 1518 pwm0 { 1519 pwm0_pin: pwm0-pin { 1520 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1521 }; 1522 }; 1523 1524 pwm1 { 1525 pwm1_pin: pwm1-pin { 1526 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1527 }; 1528 }; 1529 1530 pwm2 { 1531 pwm2_pin: pwm2-pin { 1532 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; 1533 }; 1534 }; 1535 1536 pwm3 { 1537 pwm3_pin: pwm3-pin { 1538 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; 1539 }; 1540 }; 1541 1542 gmac { 1543 rgmii_pins: rgmii-pins { 1544 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1545 <3 31 3 &pcfg_pull_none>, 1546 <3 26 3 &pcfg_pull_none>, 1547 <3 27 3 &pcfg_pull_none>, 1548 <3 28 3 &pcfg_pull_none_12ma>, 1549 <3 29 3 &pcfg_pull_none_12ma>, 1550 <3 24 3 &pcfg_pull_none_12ma>, 1551 <3 25 3 &pcfg_pull_none_12ma>, 1552 <4 0 3 &pcfg_pull_none>, 1553 <4 5 3 &pcfg_pull_none>, 1554 <4 6 3 &pcfg_pull_none>, 1555 <4 9 3 &pcfg_pull_none_12ma>, 1556 <4 4 3 &pcfg_pull_none_12ma>, 1557 <4 1 3 &pcfg_pull_none>, 1558 <4 3 3 &pcfg_pull_none>; 1559 }; 1560 1561 rmii_pins: rmii-pins { 1562 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1563 <3 31 3 &pcfg_pull_none>, 1564 <3 28 3 &pcfg_pull_none>, 1565 <3 29 3 &pcfg_pull_none>, 1566 <4 0 3 &pcfg_pull_none>, 1567 <4 5 3 &pcfg_pull_none>, 1568 <4 4 3 &pcfg_pull_none>, 1569 <4 1 3 &pcfg_pull_none>, 1570 <4 2 3 &pcfg_pull_none>, 1571 <4 3 3 &pcfg_pull_none>; 1572 }; 1573 }; 1574 1575 spdif { 1576 spdif_tx: spdif-tx { 1577 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1578 }; 1579 }; 1580 }; 1581 1582 power: power-controller { 1583 compatible = "rockchip,rk3288-power-controller"; 1584 #power-domain-cells = <1>; 1585 rockchip,pmu = <&pmu>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 1589 pd_gpu { 1590 reg = <RK3288_PD_GPU>; 1591 clocks = <&cru ACLK_GPU>; 1592 }; 1593 1594 pd_hevc { 1595 reg = <RK3288_PD_HEVC>; 1596 clocks = <&cru ACLK_HEVC>, 1597 <&cru SCLK_HEVC_CABAC>, 1598 <&cru SCLK_HEVC_CORE>, 1599 <&cru HCLK_HEVC>; 1600 }; 1601 1602 pd_vio { 1603 reg = <RK3288_PD_VIO>; 1604 clocks = <&cru ACLK_IEP>, 1605 <&cru ACLK_ISP>, 1606 <&cru ACLK_RGA>, 1607 <&cru ACLK_VIP>, 1608 <&cru ACLK_VOP0>, 1609 <&cru ACLK_VOP1>, 1610 <&cru DCLK_VOP0>, 1611 <&cru DCLK_VOP1>, 1612 <&cru HCLK_IEP>, 1613 <&cru HCLK_ISP>, 1614 <&cru HCLK_RGA>, 1615 <&cru HCLK_VIP>, 1616 <&cru HCLK_VOP0>, 1617 <&cru HCLK_VOP1>, 1618 <&cru PCLK_EDP_CTRL>, 1619 <&cru PCLK_HDMI_CTRL>, 1620 <&cru PCLK_LVDS_PHY>, 1621 <&cru PCLK_MIPI_CSI>, 1622 <&cru PCLK_MIPI_DSI0>, 1623 <&cru PCLK_MIPI_DSI1>, 1624 <&cru SCLK_EDP_24M>, 1625 <&cru SCLK_EDP>, 1626 <&cru SCLK_HDMI_CEC>, 1627 <&cru SCLK_HDMI_HDCP>, 1628 <&cru SCLK_ISP_JPE>, 1629 <&cru SCLK_ISP>, 1630 <&cru SCLK_RGA>; 1631 }; 1632 1633 pd_video { 1634 reg = <RK3288_PD_VIDEO>; 1635 clocks = <&cru ACLK_VCODEC>, 1636 <&cru HCLK_VCODEC>; 1637 }; 1638 }; 1639}; 1640
