1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3228-cru.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 mmc0 = &emmc; 25 mmc1 = &sdmmc; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 resets = <&cru SRST_CORE0>; 37 operating-points = < 38 /* KHz uV */ 39 816000 1000000 40 >; 41 #cooling-cells = <2>; /* min followed by max */ 42 clock-latency = <40000>; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu1: cpu@f01 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf01>; 50 resets = <&cru SRST_CORE1>; 51 }; 52 53 cpu2: cpu@f02 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf02>; 57 resets = <&cru SRST_CORE2>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 }; 66 }; 67 68 amba { 69 compatible = "simple-bus"; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges; 73 74 pdma: pdma@110f0000 { 75 compatible = "arm,pl330", "arm,primecell"; 76 reg = <0x110f0000 0x4000>; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 79 #dma-cells = <1>; 80 clocks = <&cru ACLK_DMAC>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 arm-pmu { 86 compatible = "arm,cortex-a7-pmu"; 87 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 92 }; 93 94 memory@60000000 { 95 device_type = "memory"; 96 reg = <0x60000000 0x40000000>; 97 }; 98 99 timer { 100 compatible = "arm,armv7-timer"; 101 arm,cpu-registers-not-fw-configured; 102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 103 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 104 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 105 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 106 clock-frequency = <24000000>; 107 }; 108 109 xin24m: oscillator { 110 compatible = "fixed-clock"; 111 clock-frequency = <24000000>; 112 clock-output-names = "xin24m"; 113 #clock-cells = <0>; 114 }; 115 116 bus_intmem@10080000 { 117 compatible = "mmio-sram"; 118 reg = <0x10080000 0x9000>; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges = <0 0x10080000 0x9000>; 122 smp-sram@0 { 123 compatible = "rockchip,rk322x-smp-sram"; 124 reg = <0x00 0x10>; 125 }; 126 ddr_sram: ddr-sram@1000 { 127 compatible = "rockchip,rk322x-ddr-sram"; 128 reg = <0x1000 0x8000>; 129 }; 130 }; 131 132 crypto: crypto@100a0000 { 133 compatible = "rockchip,rk322x-crypto"; 134 reg = <0x100a0000 0x10000>; 135 clock-names = "sclk_crypto"; 136 clocks = <&cru SCLK_CRYPTO>; 137 status = "disabled"; 138 }; 139 140 i2s1: i2s1@100b0000 { 141 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 142 reg = <0x100b0000 0x4000>; 143 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 clock-names = "i2s_clk", "i2s_hclk"; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 dmas = <&pdma 14>, <&pdma 15>; 149 dma-names = "tx", "rx"; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&i2s1_bus>; 152 status = "disabled"; 153 }; 154 155 i2s0: i2s0@100c0000 { 156 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x100c0000 0x4000>; 158 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 clock-names = "i2s_clk", "i2s_hclk"; 162 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 163 dmas = <&pdma 11>, <&pdma 12>; 164 dma-names = "tx", "rx"; 165 status = "disabled"; 166 }; 167 168 i2s2: i2s2@100e0000 { 169 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 170 reg = <0x100e0000 0x4000>; 171 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 clock-names = "i2s_clk", "i2s_hclk"; 175 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 176 dmas = <&pdma 0>, <&pdma 1>; 177 dma-names = "tx", "rx"; 178 status = "disabled"; 179 }; 180 181 grf: syscon@11000000 { 182 compatible = "rockchip,rk3228-grf", "syscon"; 183 reg = <0x11000000 0x1000>; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 187 u2phy0: usb2-phy@760 { 188 compatible = "rockchip,rk322x-usb2phy"; 189 reg = <0x0760 0x0c>; 190 status = "disabled"; 191 192 u2phy0_otg: otg-port { 193 #phy-cells = <0>; 194 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 197 interrupt-names = "otg-bvalid", "otg-id", 198 "linestate"; 199 status = "disabled"; 200 }; 201 202 u2phy0_host: host-port { 203 #phy-cells = <0>; 204 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 205 interrupt-names = "linestate"; 206 status = "disabled"; 207 }; 208 }; 209 210 u2phy1: usb2-phy@800 { 211 compatible = "rockchip,rk322x-usb2phy"; 212 reg = <0x0800 0x0c>; 213 status = "disabled"; 214 215 u2phy1_otg: otg-port { 216 #phy-cells = <0>; 217 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 218 interrupt-names = "linestate"; 219 status = "disabled"; 220 }; 221 222 u2phy1_host: host-port { 223 #phy-cells = <0>; 224 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 225 interrupt-names = "linestate"; 226 status = "disabled"; 227 }; 228 }; 229 }; 230 231 uart0: serial@11010000 { 232 compatible = "snps,dw-apb-uart"; 233 reg = <0x11010000 0x100>; 234 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 235 clock-frequency = <24000000>; 236 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 237 clock-names = "baudclk", "apb_pclk"; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 240 reg-shift = <2>; 241 reg-io-width = <4>; 242 status = "disabled"; 243 }; 244 245 uart1: serial@11020000 { 246 compatible = "snps,dw-apb-uart"; 247 reg = <0x11020000 0x100>; 248 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 249 clock-frequency = <24000000>; 250 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 251 clock-names = "baudclk", "apb_pclk"; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&uart1_xfer>; 254 reg-shift = <2>; 255 reg-io-width = <4>; 256 status = "disabled"; 257 }; 258 259 uart2: serial@11030000 { 260 compatible = "snps,dw-apb-uart"; 261 reg = <0x11030000 0x100>; 262 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 263 clock-frequency = <24000000>; 264 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 265 clock-names = "baudclk", "apb_pclk"; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&uart21_xfer>; 268 reg-shift = <2>; 269 reg-io-width = <4>; 270 status = "disabled"; 271 }; 272 273 efuse: efuse@11040000 { 274 compatible = "rockchip,rk322x-efuse"; 275 reg = <0x11040000 0x20>; 276 #address-cells = <1>; 277 #size-cells = <1>; 278 clocks = <&cru PCLK_EFUSE_256>; 279 clock-names = "pclk_efuse"; 280 281 /* Data cells */ 282 efuse_id: id@7 { 283 reg = <0x7 0x10>; 284 }; 285 cpu_leakage: cpu_leakage@17 { 286 reg = <0x17 0x1>; 287 }; 288 }; 289 290 i2c0: i2c@11050000 { 291 compatible = "rockchip,rk3228-i2c"; 292 reg = <0x11050000 0x1000>; 293 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 clock-names = "i2c"; 297 clocks = <&cru PCLK_I2C0>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&i2c0_xfer>; 300 status = "disabled"; 301 }; 302 303 i2c1: i2c@11060000 { 304 compatible = "rockchip,rk3228-i2c"; 305 reg = <0x11060000 0x1000>; 306 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 clock-names = "i2c"; 310 clocks = <&cru PCLK_I2C1>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&i2c1_xfer>; 313 status = "disabled"; 314 }; 315 316 i2c2: i2c@11070000 { 317 compatible = "rockchip,rk3228-i2c"; 318 reg = <0x11070000 0x1000>; 319 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 clock-names = "i2c"; 323 clocks = <&cru PCLK_I2C2>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c2_xfer>; 326 status = "disabled"; 327 }; 328 329 i2c3: i2c@11080000 { 330 compatible = "rockchip,rk3228-i2c"; 331 reg = <0x11080000 0x1000>; 332 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 clock-names = "i2c"; 336 clocks = <&cru PCLK_I2C3>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&i2c3_xfer>; 339 status = "disabled"; 340 }; 341 342 pwm0: pwm@110b0000 { 343 compatible = "rockchip,rk3288-pwm"; 344 reg = <0x110b0000 0x10>; 345 #pwm-cells = <3>; 346 clocks = <&cru PCLK_PWM>; 347 clock-names = "pwm"; 348 pinctrl-names = "active"; 349 pinctrl-0 = <&pwm0_pin>; 350 status = "disabled"; 351 }; 352 353 pwm1: pwm@110b0010 { 354 compatible = "rockchip,rk3288-pwm"; 355 reg = <0x110b0010 0x10>; 356 #pwm-cells = <3>; 357 clocks = <&cru PCLK_PWM>; 358 clock-names = "pwm"; 359 pinctrl-names = "active"; 360 pinctrl-0 = <&pwm1_pin>; 361 status = "disabled"; 362 }; 363 364 pwm2: pwm@110b0020 { 365 compatible = "rockchip,rk3288-pwm"; 366 reg = <0x110b0020 0x10>; 367 #pwm-cells = <3>; 368 clocks = <&cru PCLK_PWM>; 369 clock-names = "pwm"; 370 pinctrl-names = "active"; 371 pinctrl-0 = <&pwm2_pin>; 372 status = "disabled"; 373 }; 374 375 pwm3: pwm@110b0030 { 376 compatible = "rockchip,rk3288-pwm"; 377 reg = <0x110b0030 0x10>; 378 #pwm-cells = <2>; 379 clocks = <&cru PCLK_PWM>; 380 clock-names = "pwm"; 381 pinctrl-names = "active"; 382 pinctrl-0 = <&pwm3_pin>; 383 status = "disabled"; 384 }; 385 386 timer: timer@110c0000 { 387 compatible = "rockchip,rk3288-timer"; 388 reg = <0x110c0000 0x20>; 389 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&xin24m>, <&cru PCLK_TIMER>; 391 clock-names = "timer", "pclk"; 392 }; 393 394 cru: clock-controller@110e0000 { 395 compatible = "rockchip,rk3228-cru"; 396 reg = <0x110e0000 0x1000>; 397 rockchip,grf = <&grf>; 398 #clock-cells = <1>; 399 #reset-cells = <1>; 400 assigned-clocks = <&cru PLL_GPLL>; 401 assigned-clock-rates = <594000000>; 402 }; 403 404 thermal-zones { 405 cpu_thermal: cpu-thermal { 406 polling-delay-passive = <100>; /* milliseconds */ 407 polling-delay = <5000>; /* milliseconds */ 408 409 thermal-sensors = <&tsadc 0>; 410 411 trips { 412 cpu_alert0: cpu_alert0 { 413 temperature = <70000>; /* millicelsius */ 414 hysteresis = <2000>; /* millicelsius */ 415 type = "passive"; 416 }; 417 cpu_alert1: cpu_alert1 { 418 temperature = <75000>; /* millicelsius */ 419 hysteresis = <2000>; /* millicelsius */ 420 type = "passive"; 421 }; 422 cpu_crit: cpu_crit { 423 temperature = <90000>; /* millicelsius */ 424 hysteresis = <2000>; /* millicelsius */ 425 type = "critical"; 426 }; 427 }; 428 429 cooling-maps { 430 map0 { 431 trip = <&cpu_alert0>; 432 cooling-device = 433 <&cpu0 THERMAL_NO_LIMIT 6>; 434 }; 435 map1 { 436 trip = <&cpu_alert1>; 437 cooling-device = 438 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 439 }; 440 }; 441 }; 442 }; 443 444 tsadc: tsadc@11150000 { 445 compatible = "rockchip,rk3228-tsadc"; 446 reg = <0x11150000 0x100>; 447 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 449 clock-names = "tsadc", "apb_pclk"; 450 resets = <&cru SRST_TSADC>; 451 reset-names = "tsadc-apb"; 452 pinctrl-names = "init", "default", "sleep"; 453 pinctrl-0 = <&otp_gpio>; 454 pinctrl-1 = <&otp_out>; 455 pinctrl-2 = <&otp_gpio>; 456 #thermal-sensor-cells = <0>; 457 rockchip,hw-tshut-temp = <95000>; 458 status = "disabled"; 459 }; 460 461 sdmmc: dwmmc@30000000 { 462 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 463 reg = <0x30000000 0x4000>; 464 max-frequency = <150000000>; 465 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 467 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 468 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 469 fifo-depth = <0x100>; 470 cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 473 status = "disabled"; 474 }; 475 476 sdio: dwmmc@30010000 { 477 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 478 reg = <0x30010000 0x4000>; 479 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 481 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 482 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 483 fifo-depth = <0x100>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 486 status = "disabled"; 487 }; 488 489 emmc: dwmmc@30020000 { 490 compatible = "rockchip,rk3288-dw-mshc"; 491 reg = <0x30020000 0x4000>; 492 max-frequency = <150000000>; 493 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 495 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 496 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 497 bus-width = <8>; 498 default-sample-phase = <158>; 499 num-slots = <1>; 500 fifo-depth = <0x100>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 503 resets = <&cru SRST_EMMC>; 504 reset-names = "reset"; 505 status = "disabled"; 506 }; 507 508 usb20_otg: usb@30040000 { 509 compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", 510 "snps,dwc2"; 511 reg = <0x30040000 0x40000>; 512 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 513 hnp-srp-disable; 514 dr_mode = "otg"; 515 phys = <&u2phy0_otg>; 516 phy-names = "usb2-phy"; 517 status = "disabled"; 518 }; 519 520 gmac: ethernet@30200000 { 521 compatible = "rockchip,rk3228-gmac"; 522 reg = <0x30200000 0x10000>; 523 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 524 interrupt-names = "macirq"; 525 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 526 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 527 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 528 <&cru PCLK_GMAC>; 529 clock-names = "stmmaceth", "mac_clk_rx", 530 "mac_clk_tx", "clk_mac_ref", 531 "clk_mac_refout", "aclk_mac", 532 "pclk_mac"; 533 resets = <&cru SRST_GMAC>; 534 reset-names = "stmmaceth"; 535 rockchip,grf = <&grf>; 536 status = "disabled"; 537 }; 538 539 gic: interrupt-controller@32010000 { 540 compatible = "arm,gic-400"; 541 interrupt-controller; 542 #interrupt-cells = <3>; 543 #address-cells = <0>; 544 545 reg = <0x32011000 0x1000>, 546 <0x32012000 0x2000>, 547 <0x32014000 0x2000>, 548 <0x32016000 0x2000>; 549 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 550 }; 551 552 pinctrl: pinctrl { 553 compatible = "rockchip,rk3228-pinctrl"; 554 rockchip,grf = <&grf>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 ranges; 558 559 gpio0: gpio0@11110000 { 560 compatible = "rockchip,gpio-bank"; 561 reg = <0x11110000 0x100>; 562 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&cru PCLK_GPIO0>; 564 565 gpio-controller; 566 #gpio-cells = <2>; 567 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 }; 571 572 gpio1: gpio1@11120000 { 573 compatible = "rockchip,gpio-bank"; 574 reg = <0x11120000 0x100>; 575 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cru PCLK_GPIO1>; 577 578 gpio-controller; 579 #gpio-cells = <2>; 580 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 }; 584 585 gpio2: gpio2@11130000 { 586 compatible = "rockchip,gpio-bank"; 587 reg = <0x11130000 0x100>; 588 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&cru PCLK_GPIO2>; 590 591 gpio-controller; 592 #gpio-cells = <2>; 593 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 }; 597 598 gpio3: gpio3@11140000 { 599 compatible = "rockchip,gpio-bank"; 600 reg = <0x11140000 0x100>; 601 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&cru PCLK_GPIO3>; 603 604 gpio-controller; 605 #gpio-cells = <2>; 606 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 611 pcfg_pull_up: pcfg-pull-up { 612 bias-pull-up; 613 }; 614 615 pcfg_pull_down: pcfg-pull-down { 616 bias-pull-down; 617 }; 618 619 pcfg_pull_none: pcfg-pull-none { 620 bias-disable; 621 }; 622 623 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 624 drive-strength = <12>; 625 }; 626 627 sdmmc { 628 sdmmc_clk: sdmmc-clk { 629 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 630 }; 631 632 sdmmc_cmd: sdmmc-cmd { 633 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 634 }; 635 636 sdmmc_bus4: sdmmc-bus4 { 637 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 638 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 639 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 640 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 641 }; 642 }; 643 644 sdio { 645 sdio_clk: sdio-clk { 646 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 647 }; 648 649 sdio_cmd: sdio-cmd { 650 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 651 }; 652 653 sdio_bus4: sdio-bus4 { 654 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 655 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 656 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 657 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 658 }; 659 }; 660 661 emmc { 662 emmc_clk: emmc-clk { 663 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 664 }; 665 666 emmc_cmd: emmc-cmd { 667 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 668 }; 669 670 emmc_bus8: emmc-bus8 { 671 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, 672 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, 673 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, 674 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, 675 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, 676 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 677 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, 678 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 679 }; 680 }; 681 682 gmac { 683 rgmii_pins: rgmii-pins { 684 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 685 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 686 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 687 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 688 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 689 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 690 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 691 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 692 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 693 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 694 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 695 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 696 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 697 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 698 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 699 }; 700 701 rmii_pins: rmii-pins { 702 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 703 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 704 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 705 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 706 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 707 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 708 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 709 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 710 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 711 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 712 }; 713 714 phy_pins: phy-pins { 715 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, 716 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 717 }; 718 }; 719 720 i2c0 { 721 i2c0_xfer: i2c0-xfer { 722 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 723 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 724 }; 725 }; 726 727 i2c1 { 728 i2c1_xfer: i2c1-xfer { 729 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 730 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 731 }; 732 }; 733 734 i2c2 { 735 i2c2_xfer: i2c2-xfer { 736 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 737 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 738 }; 739 }; 740 741 i2c3 { 742 i2c3_xfer: i2c3-xfer { 743 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 744 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 745 }; 746 }; 747 748 i2s1 { 749 i2s1_bus: i2s1-bus { 750 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 751 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 752 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 753 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 754 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 755 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 756 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 757 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 758 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 759 }; 760 }; 761 762 pwm0 { 763 pwm0_pin: pwm0-pin { 764 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 765 }; 766 }; 767 768 pwm1 { 769 pwm1_pin: pwm1-pin { 770 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 771 }; 772 }; 773 774 pwm2 { 775 pwm2_pin: pwm2-pin { 776 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 777 }; 778 }; 779 780 pwm3 { 781 pwm3_pin: pwm3-pin { 782 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 783 }; 784 }; 785 786 tsadc { 787 otp_gpio: otp-gpio { 788 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 789 }; 790 791 otp_out: otp-out { 792 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 793 }; 794 }; 795 796 uart0 { 797 uart0_xfer: uart0-xfer { 798 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 799 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; 800 }; 801 802 uart0_cts: uart0-cts { 803 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 804 }; 805 806 uart0_rts: uart0-rts { 807 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 808 }; 809 }; 810 811 uart1 { 812 uart1_xfer: uart1-xfer { 813 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 814 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 815 }; 816 817 uart1_cts: uart1-cts { 818 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 819 }; 820 821 uart1_rts: uart1-rts { 822 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 823 }; 824 }; 825 826 uart2 { 827 uart2_xfer: uart2-xfer { 828 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, 829 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 830 }; 831 832 uart2_cts: uart2-cts { 833 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 834 }; 835 836 uart2_rts: uart2-rts { 837 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 838 }; 839 }; 840 841 uart2-1 { 842 uart21_xfer: uart21-xfer { 843 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, 844 <1 9 RK_FUNC_2 &pcfg_pull_none>; 845 }; 846 }; 847 }; 848 849 dmc: dmc@11200000 { 850 compatible = "rockchip,rk3228-dmc", "syscon"; 851 rockchip,cru = <&cru>; 852 rockchip,grf = <&grf>; 853 rockchip,msch = <&service_msch>; 854 reg = <0x11200000 0x3fc 855 0x12000000 0x400>; 856 rockchip,sram = <&ddr_sram>; 857 }; 858 859 service_msch: syscon@31090000 { 860 compatible = "rockchip,rk3228-msch", "syscon"; 861 reg = <0x31090000 0x2000>; 862 }; 863 864 nandc: nandc@30030000 { 865 compatible = "rockchip,rk-nandc"; 866 reg = <0x30030000 0x4000>; 867 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 868 nandc_id = <0>; 869 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 870 clock-names = "clk_nandc", "hclk_nandc"; 871 status = "disabled"; 872 }; 873}; 874