1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3228-cru.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 mmc0 = &emmc; 25 mmc1 = &sdmmc; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 resets = <&cru SRST_CORE0>; 37 operating-points = < 38 /* KHz uV */ 39 816000 1000000 40 >; 41 #cooling-cells = <2>; /* min followed by max */ 42 clock-latency = <40000>; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu1: cpu@f01 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf01>; 50 resets = <&cru SRST_CORE1>; 51 }; 52 53 cpu2: cpu@f02 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf02>; 57 resets = <&cru SRST_CORE2>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 }; 66 }; 67 68 amba { 69 compatible = "simple-bus"; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges; 73 74 pdma: pdma@110f0000 { 75 compatible = "arm,pl330", "arm,primecell"; 76 reg = <0x110f0000 0x4000>; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 79 #dma-cells = <1>; 80 clocks = <&cru ACLK_DMAC>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 arm-pmu { 86 compatible = "arm,cortex-a7-pmu"; 87 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 92 }; 93 94 memory@60000000 { 95 device_type = "memory"; 96 reg = <0x60000000 0x40000000>; 97 }; 98 99 timer { 100 compatible = "arm,armv7-timer"; 101 arm,cpu-registers-not-fw-configured; 102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 103 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 104 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 105 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 106 clock-frequency = <24000000>; 107 }; 108 109 xin24m: oscillator { 110 compatible = "fixed-clock"; 111 clock-frequency = <24000000>; 112 clock-output-names = "xin24m"; 113 #clock-cells = <0>; 114 }; 115 116 bus_intmem@10080000 { 117 compatible = "mmio-sram"; 118 reg = <0x10080000 0x9000>; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges = <0 0x10080000 0x9000>; 122 smp-sram@0 { 123 compatible = "rockchip,rk322x-smp-sram"; 124 reg = <0x00 0x10>; 125 }; 126 ddr_sram: ddr-sram@1000 { 127 compatible = "rockchip,rk322x-ddr-sram"; 128 reg = <0x1000 0x8000>; 129 }; 130 }; 131 132 i2s1: i2s1@100b0000 { 133 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 134 reg = <0x100b0000 0x4000>; 135 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 clock-names = "i2s_clk", "i2s_hclk"; 139 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 140 dmas = <&pdma 14>, <&pdma 15>; 141 dma-names = "tx", "rx"; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&i2s1_bus>; 144 status = "disabled"; 145 }; 146 147 i2s0: i2s0@100c0000 { 148 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 149 reg = <0x100c0000 0x4000>; 150 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clock-names = "i2s_clk", "i2s_hclk"; 154 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 155 dmas = <&pdma 11>, <&pdma 12>; 156 dma-names = "tx", "rx"; 157 status = "disabled"; 158 }; 159 160 i2s2: i2s2@100e0000 { 161 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 162 reg = <0x100e0000 0x4000>; 163 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clock-names = "i2s_clk", "i2s_hclk"; 167 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 168 dmas = <&pdma 0>, <&pdma 1>; 169 dma-names = "tx", "rx"; 170 status = "disabled"; 171 }; 172 173 grf: syscon@11000000 { 174 compatible = "rockchip,rk3228-grf", "syscon"; 175 reg = <0x11000000 0x1000>; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 179 u2phy0: usb2-phy@760 { 180 compatible = "rockchip,rk322x-usb2phy"; 181 reg = <0x0760 0x0c>; 182 status = "disabled"; 183 184 u2phy0_otg: otg-port { 185 #phy-cells = <0>; 186 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 189 interrupt-names = "otg-bvalid", "otg-id", 190 "linestate"; 191 status = "disabled"; 192 }; 193 194 u2phy0_host: host-port { 195 #phy-cells = <0>; 196 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 197 interrupt-names = "linestate"; 198 status = "disabled"; 199 }; 200 }; 201 202 u2phy1: usb2-phy@800 { 203 compatible = "rockchip,rk322x-usb2phy"; 204 reg = <0x0800 0x0c>; 205 status = "disabled"; 206 207 u2phy1_otg: otg-port { 208 #phy-cells = <0>; 209 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-names = "linestate"; 211 status = "disabled"; 212 }; 213 214 u2phy1_host: host-port { 215 #phy-cells = <0>; 216 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 217 interrupt-names = "linestate"; 218 status = "disabled"; 219 }; 220 }; 221 }; 222 223 uart0: serial@11010000 { 224 compatible = "snps,dw-apb-uart"; 225 reg = <0x11010000 0x100>; 226 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 227 clock-frequency = <24000000>; 228 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 229 clock-names = "baudclk", "apb_pclk"; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 232 reg-shift = <2>; 233 reg-io-width = <4>; 234 status = "disabled"; 235 }; 236 237 uart1: serial@11020000 { 238 compatible = "snps,dw-apb-uart"; 239 reg = <0x11020000 0x100>; 240 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 241 clock-frequency = <24000000>; 242 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 243 clock-names = "baudclk", "apb_pclk"; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&uart1_xfer>; 246 reg-shift = <2>; 247 reg-io-width = <4>; 248 status = "disabled"; 249 }; 250 251 uart2: serial@11030000 { 252 compatible = "snps,dw-apb-uart"; 253 reg = <0x11030000 0x100>; 254 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 255 clock-frequency = <24000000>; 256 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 257 clock-names = "baudclk", "apb_pclk"; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&uart21_xfer>; 260 reg-shift = <2>; 261 reg-io-width = <4>; 262 status = "disabled"; 263 }; 264 265 efuse: efuse@11040000 { 266 compatible = "rockchip,rk322x-efuse"; 267 reg = <0x11040000 0x20>; 268 #address-cells = <1>; 269 #size-cells = <1>; 270 clocks = <&cru PCLK_EFUSE_256>; 271 clock-names = "pclk_efuse"; 272 273 /* Data cells */ 274 efuse_id: id@7 { 275 reg = <0x7 0x10>; 276 }; 277 cpu_leakage: cpu_leakage@17 { 278 reg = <0x17 0x1>; 279 }; 280 }; 281 282 i2c0: i2c@11050000 { 283 compatible = "rockchip,rk3228-i2c"; 284 reg = <0x11050000 0x1000>; 285 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 clock-names = "i2c"; 289 clocks = <&cru PCLK_I2C0>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&i2c0_xfer>; 292 status = "disabled"; 293 }; 294 295 i2c1: i2c@11060000 { 296 compatible = "rockchip,rk3228-i2c"; 297 reg = <0x11060000 0x1000>; 298 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 clock-names = "i2c"; 302 clocks = <&cru PCLK_I2C1>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&i2c1_xfer>; 305 status = "disabled"; 306 }; 307 308 i2c2: i2c@11070000 { 309 compatible = "rockchip,rk3228-i2c"; 310 reg = <0x11070000 0x1000>; 311 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clock-names = "i2c"; 315 clocks = <&cru PCLK_I2C2>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&i2c2_xfer>; 318 status = "disabled"; 319 }; 320 321 i2c3: i2c@11080000 { 322 compatible = "rockchip,rk3228-i2c"; 323 reg = <0x11080000 0x1000>; 324 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 clock-names = "i2c"; 328 clocks = <&cru PCLK_I2C3>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&i2c3_xfer>; 331 status = "disabled"; 332 }; 333 334 pwm0: pwm@110b0000 { 335 compatible = "rockchip,rk3288-pwm"; 336 reg = <0x110b0000 0x10>; 337 #pwm-cells = <3>; 338 clocks = <&cru PCLK_PWM>; 339 clock-names = "pwm"; 340 pinctrl-names = "active"; 341 pinctrl-0 = <&pwm0_pin>; 342 status = "disabled"; 343 }; 344 345 pwm1: pwm@110b0010 { 346 compatible = "rockchip,rk3288-pwm"; 347 reg = <0x110b0010 0x10>; 348 #pwm-cells = <3>; 349 clocks = <&cru PCLK_PWM>; 350 clock-names = "pwm"; 351 pinctrl-names = "active"; 352 pinctrl-0 = <&pwm1_pin>; 353 status = "disabled"; 354 }; 355 356 pwm2: pwm@110b0020 { 357 compatible = "rockchip,rk3288-pwm"; 358 reg = <0x110b0020 0x10>; 359 #pwm-cells = <3>; 360 clocks = <&cru PCLK_PWM>; 361 clock-names = "pwm"; 362 pinctrl-names = "active"; 363 pinctrl-0 = <&pwm2_pin>; 364 status = "disabled"; 365 }; 366 367 pwm3: pwm@110b0030 { 368 compatible = "rockchip,rk3288-pwm"; 369 reg = <0x110b0030 0x10>; 370 #pwm-cells = <2>; 371 clocks = <&cru PCLK_PWM>; 372 clock-names = "pwm"; 373 pinctrl-names = "active"; 374 pinctrl-0 = <&pwm3_pin>; 375 status = "disabled"; 376 }; 377 378 timer: timer@110c0000 { 379 compatible = "rockchip,rk3288-timer"; 380 reg = <0x110c0000 0x20>; 381 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&xin24m>, <&cru PCLK_TIMER>; 383 clock-names = "timer", "pclk"; 384 }; 385 386 cru: clock-controller@110e0000 { 387 compatible = "rockchip,rk3228-cru"; 388 reg = <0x110e0000 0x1000>; 389 rockchip,grf = <&grf>; 390 #clock-cells = <1>; 391 #reset-cells = <1>; 392 assigned-clocks = <&cru PLL_GPLL>; 393 assigned-clock-rates = <594000000>; 394 }; 395 396 thermal-zones { 397 cpu_thermal: cpu-thermal { 398 polling-delay-passive = <100>; /* milliseconds */ 399 polling-delay = <5000>; /* milliseconds */ 400 401 thermal-sensors = <&tsadc 0>; 402 403 trips { 404 cpu_alert0: cpu_alert0 { 405 temperature = <70000>; /* millicelsius */ 406 hysteresis = <2000>; /* millicelsius */ 407 type = "passive"; 408 }; 409 cpu_alert1: cpu_alert1 { 410 temperature = <75000>; /* millicelsius */ 411 hysteresis = <2000>; /* millicelsius */ 412 type = "passive"; 413 }; 414 cpu_crit: cpu_crit { 415 temperature = <90000>; /* millicelsius */ 416 hysteresis = <2000>; /* millicelsius */ 417 type = "critical"; 418 }; 419 }; 420 421 cooling-maps { 422 map0 { 423 trip = <&cpu_alert0>; 424 cooling-device = 425 <&cpu0 THERMAL_NO_LIMIT 6>; 426 }; 427 map1 { 428 trip = <&cpu_alert1>; 429 cooling-device = 430 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 431 }; 432 }; 433 }; 434 }; 435 436 tsadc: tsadc@11150000 { 437 compatible = "rockchip,rk3228-tsadc"; 438 reg = <0x11150000 0x100>; 439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 441 clock-names = "tsadc", "apb_pclk"; 442 resets = <&cru SRST_TSADC>; 443 reset-names = "tsadc-apb"; 444 pinctrl-names = "init", "default", "sleep"; 445 pinctrl-0 = <&otp_gpio>; 446 pinctrl-1 = <&otp_out>; 447 pinctrl-2 = <&otp_gpio>; 448 #thermal-sensor-cells = <0>; 449 rockchip,hw-tshut-temp = <95000>; 450 status = "disabled"; 451 }; 452 453 sdmmc: dwmmc@30000000 { 454 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 455 reg = <0x30000000 0x4000>; 456 max-frequency = <150000000>; 457 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 459 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 460 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 461 fifo-depth = <0x100>; 462 cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 465 status = "disabled"; 466 }; 467 468 sdio: dwmmc@30010000 { 469 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 470 reg = <0x30010000 0x4000>; 471 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 473 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 474 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 475 fifo-depth = <0x100>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 478 status = "disabled"; 479 }; 480 481 emmc: dwmmc@30020000 { 482 compatible = "rockchip,rk3288-dw-mshc"; 483 reg = <0x30020000 0x4000>; 484 max-frequency = <150000000>; 485 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 487 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 488 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 489 bus-width = <8>; 490 default-sample-phase = <158>; 491 num-slots = <1>; 492 fifo-depth = <0x100>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 495 resets = <&cru SRST_EMMC>; 496 reset-names = "reset"; 497 status = "disabled"; 498 }; 499 500 usb20_otg: usb@30040000 { 501 compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", 502 "snps,dwc2"; 503 reg = <0x30040000 0x40000>; 504 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 505 hnp-srp-disable; 506 dr_mode = "otg"; 507 phys = <&u2phy0_otg>; 508 phy-names = "usb2-phy"; 509 status = "disabled"; 510 }; 511 512 gmac: ethernet@30200000 { 513 compatible = "rockchip,rk3228-gmac"; 514 reg = <0x30200000 0x10000>; 515 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-names = "macirq"; 517 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 518 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 519 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 520 <&cru PCLK_GMAC>; 521 clock-names = "stmmaceth", "mac_clk_rx", 522 "mac_clk_tx", "clk_mac_ref", 523 "clk_mac_refout", "aclk_mac", 524 "pclk_mac"; 525 resets = <&cru SRST_GMAC>; 526 reset-names = "stmmaceth"; 527 rockchip,grf = <&grf>; 528 status = "disabled"; 529 }; 530 531 gic: interrupt-controller@32010000 { 532 compatible = "arm,gic-400"; 533 interrupt-controller; 534 #interrupt-cells = <3>; 535 #address-cells = <0>; 536 537 reg = <0x32011000 0x1000>, 538 <0x32012000 0x2000>, 539 <0x32014000 0x2000>, 540 <0x32016000 0x2000>; 541 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 542 }; 543 544 pinctrl: pinctrl { 545 compatible = "rockchip,rk3228-pinctrl"; 546 rockchip,grf = <&grf>; 547 #address-cells = <1>; 548 #size-cells = <1>; 549 ranges; 550 551 gpio0: gpio0@11110000 { 552 compatible = "rockchip,gpio-bank"; 553 reg = <0x11110000 0x100>; 554 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cru PCLK_GPIO0>; 556 557 gpio-controller; 558 #gpio-cells = <2>; 559 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 }; 563 564 gpio1: gpio1@11120000 { 565 compatible = "rockchip,gpio-bank"; 566 reg = <0x11120000 0x100>; 567 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&cru PCLK_GPIO1>; 569 570 gpio-controller; 571 #gpio-cells = <2>; 572 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 }; 576 577 gpio2: gpio2@11130000 { 578 compatible = "rockchip,gpio-bank"; 579 reg = <0x11130000 0x100>; 580 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cru PCLK_GPIO2>; 582 583 gpio-controller; 584 #gpio-cells = <2>; 585 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 }; 589 590 gpio3: gpio3@11140000 { 591 compatible = "rockchip,gpio-bank"; 592 reg = <0x11140000 0x100>; 593 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cru PCLK_GPIO3>; 595 596 gpio-controller; 597 #gpio-cells = <2>; 598 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 }; 602 603 pcfg_pull_up: pcfg-pull-up { 604 bias-pull-up; 605 }; 606 607 pcfg_pull_down: pcfg-pull-down { 608 bias-pull-down; 609 }; 610 611 pcfg_pull_none: pcfg-pull-none { 612 bias-disable; 613 }; 614 615 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 616 drive-strength = <12>; 617 }; 618 619 sdmmc { 620 sdmmc_clk: sdmmc-clk { 621 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 622 }; 623 624 sdmmc_cmd: sdmmc-cmd { 625 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 626 }; 627 628 sdmmc_bus4: sdmmc-bus4 { 629 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 630 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 631 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 632 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 633 }; 634 }; 635 636 sdio { 637 sdio_clk: sdio-clk { 638 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 639 }; 640 641 sdio_cmd: sdio-cmd { 642 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 643 }; 644 645 sdio_bus4: sdio-bus4 { 646 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 647 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 648 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 649 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 650 }; 651 }; 652 653 emmc { 654 emmc_clk: emmc-clk { 655 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 656 }; 657 658 emmc_cmd: emmc-cmd { 659 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 660 }; 661 662 emmc_bus8: emmc-bus8 { 663 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, 664 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, 665 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, 666 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, 667 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, 668 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 669 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, 670 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 671 }; 672 }; 673 674 gmac { 675 rgmii_pins: rgmii-pins { 676 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 677 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 678 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 679 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 680 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 681 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 682 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 683 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 684 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 685 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 686 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 687 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 688 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 689 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 690 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 691 }; 692 693 rmii_pins: rmii-pins { 694 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 695 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 696 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 697 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 698 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 699 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 700 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 701 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 702 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 703 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 704 }; 705 706 phy_pins: phy-pins { 707 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, 708 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 709 }; 710 }; 711 712 i2c0 { 713 i2c0_xfer: i2c0-xfer { 714 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 715 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 716 }; 717 }; 718 719 i2c1 { 720 i2c1_xfer: i2c1-xfer { 721 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 722 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 723 }; 724 }; 725 726 i2c2 { 727 i2c2_xfer: i2c2-xfer { 728 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 729 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 730 }; 731 }; 732 733 i2c3 { 734 i2c3_xfer: i2c3-xfer { 735 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 736 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 737 }; 738 }; 739 740 i2s1 { 741 i2s1_bus: i2s1-bus { 742 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 743 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 744 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 745 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 746 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 747 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 748 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 749 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 750 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 751 }; 752 }; 753 754 pwm0 { 755 pwm0_pin: pwm0-pin { 756 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 757 }; 758 }; 759 760 pwm1 { 761 pwm1_pin: pwm1-pin { 762 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 763 }; 764 }; 765 766 pwm2 { 767 pwm2_pin: pwm2-pin { 768 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 769 }; 770 }; 771 772 pwm3 { 773 pwm3_pin: pwm3-pin { 774 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 775 }; 776 }; 777 778 tsadc { 779 otp_gpio: otp-gpio { 780 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 781 }; 782 783 otp_out: otp-out { 784 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 785 }; 786 }; 787 788 uart0 { 789 uart0_xfer: uart0-xfer { 790 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 791 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; 792 }; 793 794 uart0_cts: uart0-cts { 795 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 796 }; 797 798 uart0_rts: uart0-rts { 799 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 800 }; 801 }; 802 803 uart1 { 804 uart1_xfer: uart1-xfer { 805 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 806 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 807 }; 808 809 uart1_cts: uart1-cts { 810 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 811 }; 812 813 uart1_rts: uart1-rts { 814 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 815 }; 816 }; 817 818 uart2 { 819 uart2_xfer: uart2-xfer { 820 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, 821 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 822 }; 823 824 uart2_cts: uart2-cts { 825 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 826 }; 827 828 uart2_rts: uart2-rts { 829 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 830 }; 831 }; 832 833 uart2-1 { 834 uart21_xfer: uart21-xfer { 835 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, 836 <1 9 RK_FUNC_2 &pcfg_pull_none>; 837 }; 838 }; 839 }; 840 841 dmc: dmc@11200000 { 842 compatible = "rockchip,rk3228-dmc", "syscon"; 843 rockchip,cru = <&cru>; 844 rockchip,grf = <&grf>; 845 rockchip,msch = <&service_msch>; 846 reg = <0x11200000 0x3fc 847 0x12000000 0x400>; 848 rockchip,sram = <&ddr_sram>; 849 }; 850 851 service_msch: syscon@31090000 { 852 compatible = "rockchip,rk3228-msch", "syscon"; 853 reg = <0x31090000 0x2000>; 854 }; 855 856 nandc: nandc@30030000 { 857 compatible = "rockchip,rk-nandc"; 858 reg = <0x30030000 0x4000>; 859 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 860 nandc_id = <0>; 861 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 862 clock-names = "clk_nandc", "hclk_nandc"; 863 status = "disabled"; 864 }; 865}; 866