1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3228-cru.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 mmc0 = &emmc; 25 mmc1 = &sdmmc; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 resets = <&cru SRST_CORE0>; 37 operating-points = < 38 /* KHz uV */ 39 816000 1000000 40 >; 41 #cooling-cells = <2>; /* min followed by max */ 42 clock-latency = <40000>; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu1: cpu@f01 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf01>; 50 resets = <&cru SRST_CORE1>; 51 }; 52 53 cpu2: cpu@f02 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf02>; 57 resets = <&cru SRST_CORE2>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 }; 66 }; 67 68 amba { 69 compatible = "simple-bus"; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges; 73 74 pdma: pdma@110f0000 { 75 compatible = "arm,pl330", "arm,primecell"; 76 reg = <0x110f0000 0x4000>; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 79 #dma-cells = <1>; 80 clocks = <&cru ACLK_DMAC>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 arm-pmu { 86 compatible = "arm,cortex-a7-pmu"; 87 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 92 }; 93 94 timer { 95 compatible = "arm,armv7-timer"; 96 arm,cpu-registers-not-fw-configured; 97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 101 clock-frequency = <24000000>; 102 }; 103 104 xin24m: oscillator { 105 compatible = "fixed-clock"; 106 clock-frequency = <24000000>; 107 clock-output-names = "xin24m"; 108 #clock-cells = <0>; 109 }; 110 111 bus_intmem@10080000 { 112 compatible = "mmio-sram"; 113 reg = <0x10080000 0x9000>; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges = <0 0x10080000 0x9000>; 117 smp-sram@0 { 118 compatible = "rockchip,rk322x-smp-sram"; 119 reg = <0x00 0x10>; 120 }; 121 ddr_sram: ddr-sram@1000 { 122 compatible = "rockchip,rk322x-ddr-sram"; 123 reg = <0x1000 0x8000>; 124 }; 125 }; 126 127 i2s1: i2s1@100b0000 { 128 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 129 reg = <0x100b0000 0x4000>; 130 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 clock-names = "i2s_clk", "i2s_hclk"; 134 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 135 dmas = <&pdma 14>, <&pdma 15>; 136 dma-names = "tx", "rx"; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&i2s1_bus>; 139 status = "disabled"; 140 }; 141 142 i2s0: i2s0@100c0000 { 143 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 144 reg = <0x100c0000 0x4000>; 145 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 150 dmas = <&pdma 11>, <&pdma 12>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s2@100e0000 { 156 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x100e0000 0x4000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 clock-names = "i2s_clk", "i2s_hclk"; 162 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 163 dmas = <&pdma 0>, <&pdma 1>; 164 dma-names = "tx", "rx"; 165 status = "disabled"; 166 }; 167 168 grf: syscon@11000000 { 169 u-boot,dm-pre-reloc; 170 compatible = "rockchip,rk3228-grf", "syscon"; 171 reg = <0x11000000 0x1000>; 172 }; 173 174 uart0: serial@11010000 { 175 compatible = "snps,dw-apb-uart"; 176 reg = <0x11010000 0x100>; 177 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 178 clock-frequency = <24000000>; 179 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 180 clock-names = "baudclk", "apb_pclk"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 183 reg-shift = <2>; 184 reg-io-width = <4>; 185 status = "disabled"; 186 }; 187 188 uart1: serial@11020000 { 189 compatible = "snps,dw-apb-uart"; 190 reg = <0x11020000 0x100>; 191 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 192 clock-frequency = <24000000>; 193 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 194 clock-names = "baudclk", "apb_pclk"; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&uart1_xfer>; 197 reg-shift = <2>; 198 reg-io-width = <4>; 199 status = "disabled"; 200 }; 201 202 uart2: serial@11030000 { 203 compatible = "snps,dw-apb-uart"; 204 reg = <0x11030000 0x100>; 205 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 206 clock-frequency = <24000000>; 207 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 208 clock-names = "baudclk", "apb_pclk"; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&uart2_xfer>; 211 reg-shift = <2>; 212 reg-io-width = <4>; 213 status = "disabled"; 214 }; 215 216 efuse: efuse@11040000 { 217 compatible = "rockchip,rk322x-efuse"; 218 reg = <0x11040000 0x20>; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 clocks = <&cru PCLK_EFUSE_256>; 222 clock-names = "pclk_efuse"; 223 224 /* Data cells */ 225 efuse_id: id@7 { 226 reg = <0x7 0x10>; 227 }; 228 cpu_leakage: cpu_leakage@17 { 229 reg = <0x17 0x1>; 230 }; 231 }; 232 233 i2c0: i2c@11050000 { 234 compatible = "rockchip,rk3228-i2c"; 235 reg = <0x11050000 0x1000>; 236 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 clock-names = "i2c"; 240 clocks = <&cru PCLK_I2C0>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&i2c0_xfer>; 243 status = "disabled"; 244 }; 245 246 i2c1: i2c@11060000 { 247 compatible = "rockchip,rk3228-i2c"; 248 reg = <0x11060000 0x1000>; 249 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 clock-names = "i2c"; 253 clocks = <&cru PCLK_I2C1>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&i2c1_xfer>; 256 status = "disabled"; 257 }; 258 259 i2c2: i2c@11070000 { 260 compatible = "rockchip,rk3228-i2c"; 261 reg = <0x11070000 0x1000>; 262 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 clock-names = "i2c"; 266 clocks = <&cru PCLK_I2C2>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&i2c2_xfer>; 269 status = "disabled"; 270 }; 271 272 i2c3: i2c@11080000 { 273 compatible = "rockchip,rk3228-i2c"; 274 reg = <0x11080000 0x1000>; 275 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 clock-names = "i2c"; 279 clocks = <&cru PCLK_I2C3>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&i2c3_xfer>; 282 status = "disabled"; 283 }; 284 285 pwm0: pwm@110b0000 { 286 compatible = "rockchip,rk3288-pwm"; 287 reg = <0x110b0000 0x10>; 288 #pwm-cells = <3>; 289 clocks = <&cru PCLK_PWM>; 290 clock-names = "pwm"; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pwm0_pin>; 293 status = "disabled"; 294 }; 295 296 pwm1: pwm@110b0010 { 297 compatible = "rockchip,rk3288-pwm"; 298 reg = <0x110b0010 0x10>; 299 #pwm-cells = <3>; 300 clocks = <&cru PCLK_PWM>; 301 clock-names = "pwm"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pwm1_pin>; 304 status = "disabled"; 305 }; 306 307 pwm2: pwm@110b0020 { 308 compatible = "rockchip,rk3288-pwm"; 309 reg = <0x110b0020 0x10>; 310 #pwm-cells = <3>; 311 clocks = <&cru PCLK_PWM>; 312 clock-names = "pwm"; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pwm2_pin>; 315 status = "disabled"; 316 }; 317 318 pwm3: pwm@110b0030 { 319 compatible = "rockchip,rk3288-pwm"; 320 reg = <0x110b0030 0x10>; 321 #pwm-cells = <2>; 322 clocks = <&cru PCLK_PWM>; 323 clock-names = "pwm"; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pwm3_pin>; 326 status = "disabled"; 327 }; 328 329 timer: timer@110c0000 { 330 compatible = "rockchip,rk3288-timer"; 331 reg = <0x110c0000 0x20>; 332 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&xin24m>, <&cru PCLK_TIMER>; 334 clock-names = "timer", "pclk"; 335 }; 336 337 cru: clock-controller@110e0000 { 338 u-boot,dm-pre-reloc; 339 compatible = "rockchip,rk3228-cru"; 340 reg = <0x110e0000 0x1000>; 341 rockchip,grf = <&grf>; 342 #clock-cells = <1>; 343 #reset-cells = <1>; 344 assigned-clocks = <&cru PLL_GPLL>; 345 assigned-clock-rates = <594000000>; 346 }; 347 348 thermal-zones { 349 cpu_thermal: cpu-thermal { 350 polling-delay-passive = <100>; /* milliseconds */ 351 polling-delay = <5000>; /* milliseconds */ 352 353 thermal-sensors = <&tsadc 0>; 354 355 trips { 356 cpu_alert0: cpu_alert0 { 357 temperature = <70000>; /* millicelsius */ 358 hysteresis = <2000>; /* millicelsius */ 359 type = "passive"; 360 }; 361 cpu_alert1: cpu_alert1 { 362 temperature = <75000>; /* millicelsius */ 363 hysteresis = <2000>; /* millicelsius */ 364 type = "passive"; 365 }; 366 cpu_crit: cpu_crit { 367 temperature = <90000>; /* millicelsius */ 368 hysteresis = <2000>; /* millicelsius */ 369 type = "critical"; 370 }; 371 }; 372 373 cooling-maps { 374 map0 { 375 trip = <&cpu_alert0>; 376 cooling-device = 377 <&cpu0 THERMAL_NO_LIMIT 6>; 378 }; 379 map1 { 380 trip = <&cpu_alert1>; 381 cooling-device = 382 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 383 }; 384 }; 385 }; 386 }; 387 388 tsadc: tsadc@11150000 { 389 compatible = "rockchip,rk3228-tsadc"; 390 reg = <0x11150000 0x100>; 391 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 393 clock-names = "tsadc", "apb_pclk"; 394 resets = <&cru SRST_TSADC>; 395 reset-names = "tsadc-apb"; 396 pinctrl-names = "init", "default", "sleep"; 397 pinctrl-0 = <&otp_gpio>; 398 pinctrl-1 = <&otp_out>; 399 pinctrl-2 = <&otp_gpio>; 400 #thermal-sensor-cells = <0>; 401 rockchip,hw-tshut-temp = <95000>; 402 status = "disabled"; 403 }; 404 405 sdmmc: dwmmc@30000000 { 406 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 407 reg = <0x30000000 0x4000>; 408 max-frequency = <150000000>; 409 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 411 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 412 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 413 fifo-depth = <0x100>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 416 status = "disabled"; 417 }; 418 419 sdio: dwmmc@30010000 { 420 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 421 reg = <0x30010000 0x4000>; 422 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 424 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 425 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 426 fifo-depth = <0x100>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 429 status = "disabled"; 430 }; 431 432 emmc: dwmmc@30020000 { 433 compatible = "rockchip,rk3288-dw-mshc"; 434 reg = <0x30020000 0x4000>; 435 max-frequency = <150000000>; 436 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 438 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 439 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 440 bus-width = <8>; 441 default-sample-phase = <158>; 442 num-slots = <1>; 443 fifo-depth = <0x100>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 446 resets = <&cru SRST_EMMC>; 447 reset-names = "reset"; 448 status = "disabled"; 449 }; 450 451 usb20_otg: usb@30040000 { 452 compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", 453 "snps,dwc2"; 454 reg = <0x30040000 0x40000>; 455 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 456 hnp-srp-disable; 457 dr_mode = "otg"; 458 status = "disabled"; 459 }; 460 461 gmac: ethernet@30200000 { 462 compatible = "rockchip,rk3228-gmac"; 463 reg = <0x30200000 0x10000>; 464 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "macirq"; 466 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 467 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 468 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 469 <&cru PCLK_GMAC>; 470 clock-names = "stmmaceth", "mac_clk_rx", 471 "mac_clk_tx", "clk_mac_ref", 472 "clk_mac_refout", "aclk_mac", 473 "pclk_mac"; 474 resets = <&cru SRST_GMAC>; 475 reset-names = "stmmaceth"; 476 rockchip,grf = <&grf>; 477 status = "disabled"; 478 }; 479 480 gic: interrupt-controller@32010000 { 481 compatible = "arm,gic-400"; 482 interrupt-controller; 483 #interrupt-cells = <3>; 484 #address-cells = <0>; 485 486 reg = <0x32011000 0x1000>, 487 <0x32012000 0x2000>, 488 <0x32014000 0x2000>, 489 <0x32016000 0x2000>; 490 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 491 }; 492 493 pinctrl: pinctrl { 494 compatible = "rockchip,rk3228-pinctrl"; 495 rockchip,grf = <&grf>; 496 #address-cells = <1>; 497 #size-cells = <1>; 498 ranges; 499 500 gpio0: gpio0@11110000 { 501 compatible = "rockchip,gpio-bank"; 502 reg = <0x11110000 0x100>; 503 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cru PCLK_GPIO0>; 505 506 gpio-controller; 507 #gpio-cells = <2>; 508 509 interrupt-controller; 510 #interrupt-cells = <2>; 511 }; 512 513 gpio1: gpio1@11120000 { 514 compatible = "rockchip,gpio-bank"; 515 reg = <0x11120000 0x100>; 516 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cru PCLK_GPIO1>; 518 519 gpio-controller; 520 #gpio-cells = <2>; 521 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 }; 525 526 gpio2: gpio2@11130000 { 527 compatible = "rockchip,gpio-bank"; 528 reg = <0x11130000 0x100>; 529 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cru PCLK_GPIO2>; 531 532 gpio-controller; 533 #gpio-cells = <2>; 534 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 }; 538 539 gpio3: gpio3@11140000 { 540 compatible = "rockchip,gpio-bank"; 541 reg = <0x11140000 0x100>; 542 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cru PCLK_GPIO3>; 544 545 gpio-controller; 546 #gpio-cells = <2>; 547 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 }; 551 552 pcfg_pull_up: pcfg-pull-up { 553 bias-pull-up; 554 }; 555 556 pcfg_pull_down: pcfg-pull-down { 557 bias-pull-down; 558 }; 559 560 pcfg_pull_none: pcfg-pull-none { 561 bias-disable; 562 }; 563 564 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 565 drive-strength = <12>; 566 }; 567 568 sdmmc { 569 sdmmc_clk: sdmmc-clk { 570 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 571 }; 572 573 sdmmc_cmd: sdmmc-cmd { 574 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 575 }; 576 577 sdmmc_bus4: sdmmc-bus4 { 578 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 579 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 580 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 581 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 582 }; 583 }; 584 585 sdio { 586 sdio_clk: sdio-clk { 587 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 588 }; 589 590 sdio_cmd: sdio-cmd { 591 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 592 }; 593 594 sdio_bus4: sdio-bus4 { 595 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 596 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 597 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 598 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 599 }; 600 }; 601 602 emmc { 603 emmc_clk: emmc-clk { 604 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 605 }; 606 607 emmc_cmd: emmc-cmd { 608 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 609 }; 610 611 emmc_bus8: emmc-bus8 { 612 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, 613 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, 614 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, 615 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, 616 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, 617 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 618 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, 619 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 620 }; 621 }; 622 623 gmac { 624 rgmii_pins: rgmii-pins { 625 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 626 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 627 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 628 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 629 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 630 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 631 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 632 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 633 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 634 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 635 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 636 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 637 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 638 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 639 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 640 }; 641 642 rmii_pins: rmii-pins { 643 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 644 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 645 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 646 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 647 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 648 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 649 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 650 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 651 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 652 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 653 }; 654 655 phy_pins: phy-pins { 656 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, 657 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 658 }; 659 }; 660 661 i2c0 { 662 i2c0_xfer: i2c0-xfer { 663 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 664 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 665 }; 666 }; 667 668 i2c1 { 669 i2c1_xfer: i2c1-xfer { 670 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 671 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 672 }; 673 }; 674 675 i2c2 { 676 i2c2_xfer: i2c2-xfer { 677 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 678 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 679 }; 680 }; 681 682 i2c3 { 683 i2c3_xfer: i2c3-xfer { 684 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 685 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 686 }; 687 }; 688 689 i2s1 { 690 i2s1_bus: i2s1-bus { 691 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 692 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 693 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 694 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 695 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 696 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 697 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 698 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 699 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 700 }; 701 }; 702 703 pwm0 { 704 pwm0_pin: pwm0-pin { 705 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 706 }; 707 }; 708 709 pwm1 { 710 pwm1_pin: pwm1-pin { 711 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 712 }; 713 }; 714 715 pwm2 { 716 pwm2_pin: pwm2-pin { 717 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 718 }; 719 }; 720 721 pwm3 { 722 pwm3_pin: pwm3-pin { 723 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 724 }; 725 }; 726 727 tsadc { 728 otp_gpio: otp-gpio { 729 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 730 }; 731 732 otp_out: otp-out { 733 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 734 }; 735 }; 736 737 uart0 { 738 uart0_xfer: uart0-xfer { 739 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 740 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; 741 }; 742 743 uart0_cts: uart0-cts { 744 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 745 }; 746 747 uart0_rts: uart0-rts { 748 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 749 }; 750 }; 751 752 uart1 { 753 uart1_xfer: uart1-xfer { 754 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 755 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 756 }; 757 758 uart1_cts: uart1-cts { 759 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 760 }; 761 762 uart1_rts: uart1-rts { 763 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 764 }; 765 }; 766 767 uart2 { 768 uart2_xfer: uart2-xfer { 769 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 770 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 771 }; 772 773 uart2_cts: uart2-cts { 774 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 775 }; 776 777 uart2_rts: uart2-rts { 778 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 779 }; 780 }; 781 }; 782 783 dmc: dmc@11200000 { 784 u-boot,dm-pre-reloc; 785 compatible = "rockchip,rk3228-dmc", "syscon"; 786 rockchip,cru = <&cru>; 787 rockchip,grf = <&grf>; 788 rockchip,msch = <&service_msch>; 789 reg = <0x11200000 0x3fc 790 0x12000000 0x400>; 791 rockchip,sram = <&ddr_sram>; 792 }; 793 794 service_msch: syscon@31090000 { 795 u-boot,dm-pre-reloc; 796 compatible = "rockchip,rk3228-msch", "syscon"; 797 reg = <0x31090000 0x2000>; 798 }; 799}; 800