xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3188.dtsi (revision 5ce558eee1d84a2b85f2bbc4c4547c8ea1c1dae4) 
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * SPDX-License-Identifier:     GPL-2.0+ or X11
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rockchip.h>
10#include <dt-bindings/clock/rk3188-cru.h>
11#include "rk3xxx.dtsi"
12
13/ {
14	compatible = "rockchip,rk3188";
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		enable-method = "rockchip,rk3066-smp";
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a9";
24			next-level-cache = <&L2>;
25			reg = <0x0>;
26			operating-points = <
27				/* kHz    uV */
28				1608000 1350000
29				1416000 1250000
30				1200000 1150000
31				1008000 1075000
32				 816000  975000
33				 600000  950000
34				 504000  925000
35				 312000  875000
36			>;
37			clock-latency = <40000>;
38			clocks = <&cru ARMCLK>;
39		};
40		cpu@1 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a9";
43			next-level-cache = <&L2>;
44			reg = <0x1>;
45		};
46		cpu@2 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a9";
49			next-level-cache = <&L2>;
50			reg = <0x2>;
51		};
52		cpu@3 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a9";
55			next-level-cache = <&L2>;
56			reg = <0x3>;
57		};
58	};
59
60	sram: sram@10080000 {
61		compatible = "mmio-sram";
62		reg = <0x10080000 0x8000>;
63		#address-cells = <1>;
64		#size-cells = <1>;
65		ranges = <0 0x10080000 0x8000>;
66
67		smp-sram@0 {
68			compatible = "rockchip,rk3066-smp-sram";
69			reg = <0x0 0x50>;
70		};
71	};
72
73	i2s0: i2s@1011a000 {
74		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
75		reg = <0x1011a000 0x2000>;
76		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
77		#address-cells = <1>;
78		#size-cells = <0>;
79		pinctrl-names = "default";
80		pinctrl-0 = <&i2s0_bus>;
81		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
82		dma-names = "tx", "rx";
83		clock-names = "i2s_hclk", "i2s_clk";
84		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
85		rockchip,playback-channels = <2>;
86		rockchip,capture-channels = <2>;
87		status = "disabled";
88	};
89
90	spdif: sound@1011e000 {
91		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
92		reg = <0x1011e000 0x2000>;
93		#sound-dai-cells = <0>;
94		clock-names = "hclk", "mclk";
95		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
96		dmas = <&dmac1_s 8>;
97		dma-names = "tx";
98		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
99		pinctrl-names = "default";
100		pinctrl-0 = <&spdif_tx>;
101		status = "disabled";
102	};
103
104	cru: clock-controller@20000000 {
105		compatible = "rockchip,rk3188-cru";
106		reg = <0x20000000 0x1000>;
107		rockchip,grf = <&grf>;
108		u-boot,dm-spl;
109
110		#clock-cells = <1>;
111		#reset-cells = <1>;
112	};
113
114	efuse: efuse@20010000 {
115		compatible = "rockchip,rockchip-efuse";
116		reg = <0x20010000 0x4000>;
117		#address-cells = <1>;
118		#size-cells = <1>;
119		clocks = <&cru PCLK_EFUSE>;
120		clock-names = "pclk_efuse";
121
122		cpu_leakage: cpu_leakage@17 {
123			reg = <0x17 0x1>;
124		};
125	};
126
127	saradc: saradc@2006c000 {
128		compatible = "rockchip,saradc";
129		reg = <0x2006c000 0x100>;
130		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
131		#io-channel-cells = <1>;
132		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
133		clock-names = "saradc", "pclk_saradc";
134		status = "disabled";
135	};
136
137	usbphy: phy {
138		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
139		rockchip,grf = <&grf>;
140		#address-cells = <1>;
141		#size-cells = <0>;
142		status = "disabled";
143
144		usbphy0: usb-phy@10c {
145			#phy-cells = <0>;
146			reg = <0x10c>;
147			clocks = <&cru SCLK_OTGPHY0>;
148			clock-names = "phyclk";
149			#clock-cells = <0>;
150		};
151
152		usbphy1: usb-phy@11c {
153			#phy-cells = <0>;
154			reg = <0x11c>;
155			clocks = <&cru SCLK_OTGPHY1>;
156			clock-names = "phyclk";
157			#clock-cells = <0>;
158		};
159	};
160
161	pinctrl: pinctrl {
162		compatible = "rockchip,rk3188-pinctrl";
163		rockchip,grf = <&grf>;
164		rockchip,pmu = <&pmu>;
165
166		#address-cells = <1>;
167		#size-cells = <1>;
168		ranges;
169		u-boot,dm-spl;
170
171		gpio0: gpio0@2000a000 {
172			compatible = "rockchip,gpio-bank";
173			reg = <0x2000a000 0x100>;
174			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
175			clocks = <&cru PCLK_GPIO0>;
176
177			gpio-controller;
178			#gpio-cells = <2>;
179
180			interrupt-controller;
181			#interrupt-cells = <2>;
182		};
183
184		gpio1: gpio1@2003c000 {
185			compatible = "rockchip,gpio-bank";
186			reg = <0x2003c000 0x100>;
187			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
188			clocks = <&cru PCLK_GPIO1>;
189
190			gpio-controller;
191			#gpio-cells = <2>;
192
193			interrupt-controller;
194			#interrupt-cells = <2>;
195		};
196
197		gpio2: gpio2@2003e000 {
198			compatible = "rockchip,gpio-bank";
199			reg = <0x2003e000 0x100>;
200			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
201			clocks = <&cru PCLK_GPIO2>;
202
203			gpio-controller;
204			#gpio-cells = <2>;
205
206			interrupt-controller;
207			#interrupt-cells = <2>;
208		};
209
210		gpio3: gpio3@20080000 {
211			compatible = "rockchip,gpio-bank";
212			reg = <0x20080000 0x100>;
213			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
214			clocks = <&cru PCLK_GPIO3>;
215
216			gpio-controller;
217			#gpio-cells = <2>;
218
219			interrupt-controller;
220			#interrupt-cells = <2>;
221		};
222
223		pcfg_pull_up: pcfg_pull_up {
224			bias-pull-up;
225		};
226
227		pcfg_pull_down: pcfg_pull_down {
228			bias-pull-down;
229		};
230
231		pcfg_pull_none: pcfg_pull_none {
232			bias-disable;
233		};
234
235		emmc {
236			emmc_clk: emmc-clk {
237				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
238			};
239
240			emmc_cmd: emmc-cmd {
241				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
242			};
243
244			emmc_rst: emmc-rst {
245				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
246			};
247
248			/*
249			 * The data pins are shared between nandc and emmc and
250			 * not accessible through pinctrl. Also they should've
251			 * been already set correctly by firmware, as
252			 * flash/emmc is the boot-device.
253			 */
254		};
255
256		emac {
257			emac_xfer: emac-xfer {
258				rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
259						<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
260						<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
261						<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
262						<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
263						<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
264						<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
265						<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
266			};
267
268			emac_mdio: emac-mdio {
269				rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
270						<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
271			};
272		};
273
274		i2c0 {
275			i2c0_xfer: i2c0-xfer {
276				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
277						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
278			};
279		};
280
281		i2c1 {
282			i2c1_xfer: i2c1-xfer {
283				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
284						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
285			};
286		};
287
288		i2c2 {
289			i2c2_xfer: i2c2-xfer {
290				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
291						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
292			};
293		};
294
295		i2c3 {
296			i2c3_xfer: i2c3-xfer {
297				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
298						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
299			};
300		};
301
302		i2c4 {
303			i2c4_xfer: i2c4-xfer {
304				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
305						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
306			};
307		};
308
309		pwm0 {
310			pwm0_out: pwm0-out {
311				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
312			};
313		};
314
315		pwm1 {
316			pwm1_out: pwm1-out {
317				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
318			};
319		};
320
321		pwm2 {
322			pwm2_out: pwm2-out {
323				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
324			};
325		};
326
327		pwm3 {
328			pwm3_out: pwm3-out {
329				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
330			};
331		};
332
333		spi0 {
334			spi0_clk: spi0-clk {
335				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
336			};
337			spi0_cs0: spi0-cs0 {
338				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
339			};
340			spi0_tx: spi0-tx {
341				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
342			};
343			spi0_rx: spi0-rx {
344				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
345			};
346			spi0_cs1: spi0-cs1 {
347				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
348			};
349		};
350
351		spi1 {
352			spi1_clk: spi1-clk {
353				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
354			};
355			spi1_cs0: spi1-cs0 {
356				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
357			};
358			spi1_rx: spi1-rx {
359				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
360			};
361			spi1_tx: spi1-tx {
362				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
363			};
364			spi1_cs1: spi1-cs1 {
365				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
366			};
367		};
368
369		uart0 {
370			uart0_xfer: uart0-xfer {
371				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
372						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
373			};
374
375			uart0_cts: uart0-cts {
376				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
377			};
378
379			uart0_rts: uart0-rts {
380				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
381			};
382		};
383
384		uart1 {
385			uart1_xfer: uart1-xfer {
386				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
387						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
388			};
389
390			uart1_cts: uart1-cts {
391				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
392			};
393
394			uart1_rts: uart1-rts {
395				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
396			};
397		};
398
399		uart2 {
400			uart2_xfer: uart2-xfer {
401				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
402						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
403			};
404			/* no rts / cts for uart2 */
405		};
406
407		uart3 {
408			uart3_xfer: uart3-xfer {
409				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
410						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
411			};
412
413			uart3_cts: uart3-cts {
414				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
415			};
416
417			uart3_rts: uart3-rts {
418				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
419			};
420		};
421
422		sd0 {
423			sd0_clk: sd0-clk {
424				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
425			};
426
427			sd0_cmd: sd0-cmd {
428				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
429			};
430
431			sd0_cd: sd0-cd {
432				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
433			};
434
435			sd0_wp: sd0-wp {
436				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
437			};
438
439			sd0_pwr: sd0-pwr {
440				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
441			};
442
443			sd0_bus1: sd0-bus-width1 {
444				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
445			};
446
447			sd0_bus4: sd0-bus-width4 {
448				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
449						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
450						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
451						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
452			};
453		};
454
455		sd1 {
456			sd1_clk: sd1-clk {
457				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
458			};
459
460			sd1_cmd: sd1-cmd {
461				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
462			};
463
464			sd1_cd: sd1-cd {
465				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
466			};
467
468			sd1_wp: sd1-wp {
469				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
470			};
471
472			sd1_bus1: sd1-bus-width1 {
473				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
474			};
475
476			sd1_bus4: sd1-bus-width4 {
477				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
478						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
479						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
480						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
481			};
482		};
483
484		i2s0 {
485			i2s0_bus: i2s0-bus {
486				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
487						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
488						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
489						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
490						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
491						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
492			};
493		};
494
495		spdif {
496			spdif_tx: spdif-tx {
497				rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
498			};
499		};
500	};
501};
502
503&emac {
504	compatible = "rockchip,rk3188-emac";
505};
506
507&global_timer {
508	interrupts = <GIC_PPI 11 0xf04>;
509};
510
511&grf {
512	compatible = "rockchip,rk3188-grf", "syscon";
513};
514
515&local_timer {
516	interrupts = <GIC_PPI 13 0xf04>;
517};
518
519&i2c0 {
520	compatible = "rockchip,rk3188-i2c";
521	pinctrl-names = "default";
522	pinctrl-0 = <&i2c0_xfer>;
523};
524
525&i2c1 {
526	compatible = "rockchip,rk3188-i2c";
527	pinctrl-names = "default";
528	pinctrl-0 = <&i2c1_xfer>;
529};
530
531&i2c2 {
532	compatible = "rockchip,rk3188-i2c";
533	pinctrl-names = "default";
534	pinctrl-0 = <&i2c2_xfer>;
535};
536
537&i2c3 {
538	compatible = "rockchip,rk3188-i2c";
539	pinctrl-names = "default";
540	pinctrl-0 = <&i2c3_xfer>;
541};
542
543&i2c4 {
544	compatible = "rockchip,rk3188-i2c";
545	pinctrl-names = "default";
546	pinctrl-0 = <&i2c4_xfer>;
547};
548
549&pmu {
550	compatible = "rockchip,rk3188-pmu", "syscon";
551};
552
553&pwm0 {
554	pinctrl-names = "default";
555	pinctrl-0 = <&pwm0_out>;
556};
557
558&pwm1 {
559	pinctrl-names = "default";
560	pinctrl-0 = <&pwm1_out>;
561};
562
563&pwm2 {
564	pinctrl-names = "default";
565	pinctrl-0 = <&pwm2_out>;
566};
567
568&pwm3 {
569	pinctrl-names = "default";
570	pinctrl-0 = <&pwm3_out>;
571};
572
573&spi0 {
574	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
575	pinctrl-names = "default";
576	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
577};
578
579&spi1 {
580	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
581	pinctrl-names = "default";
582	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
583};
584
585&uart0 {
586	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
587	pinctrl-names = "default";
588	pinctrl-0 = <&uart0_xfer>;
589};
590
591&uart1 {
592	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
593	pinctrl-names = "default";
594	pinctrl-0 = <&uart1_xfer>;
595};
596
597&uart2 {
598	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
599	pinctrl-names = "default";
600	pinctrl-0 = <&uart2_xfer>;
601};
602
603&uart3 {
604	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
605	pinctrl-names = "default";
606	pinctrl-0 = <&uart3_xfer>;
607};
608
609&wdt {
610	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
611};
612