1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include "skeleton.dtsi" 13 14/ { 15 compatible = "rockchip,rk3128"; 16 rockchip,sram = <&sram>; 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 spi0 = &spi0; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 mmc0 = &emmc; 35 mmc1 = &sdmmc; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x60000000 0x40000000>; 41 }; 42 43 arm-pmu { 44 compatible = "arm,cortex-a7-pmu"; 45 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "rockchip,rk3128-smp"; 55 56 cpu0:cpu@0x000 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a7"; 59 reg = <0x000>; 60 operating-points = < 61 /* KHz uV */ 62 816000 1000000 63 >; 64 #cooling-cells = <2>; /* min followed by max */ 65 clock-latency = <40000>; 66 clocks = <&cru ARMCLK>; 67 }; 68 69 cpu1:cpu@0x001 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a7"; 72 reg = <0x001>; 73 }; 74 75 cpu2:cpu@0x002 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a7"; 78 reg = <0x002>; 79 }; 80 81 cpu3:cpu@0x003 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a7"; 84 reg = <0x003>; 85 }; 86 }; 87 88 cpu_axi_bus: cpu_axi_bus { 89 compatible = "rockchip,cpu_axi_bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges; 93 94 qos { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 crypto { 100 reg = <0x10128080 0x20>; 101 }; 102 103 core { 104 reg = <0x1012a000 0x20>; 105 }; 106 107 peri { 108 reg = <0x1012c000 0x20>; 109 }; 110 111 gpu { 112 reg = <0x1012d000 0x20>; 113 }; 114 115 vpu { 116 reg = <0x1012e000 0x20>; 117 }; 118 119 rga { 120 reg = <0x1012f000 0x20>; 121 }; 122 ebc { 123 reg = <0x1012f080 0x20>; 124 }; 125 126 iep { 127 reg = <0x1012f100 0x20>; 128 }; 129 130 lcdc { 131 reg = <0x1012f180 0x20>; 132 rockchip,priority = <3 3>; 133 }; 134 135 vip { 136 reg = <0x1012f200 0x20>; 137 rockchip,priority = <3 3>; 138 }; 139 }; 140 141 msch { 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges; 145 146 msch@10128000 { 147 reg = <0x10128000 0x20>; 148 rockchip,read-latency = <0x3f>; 149 }; 150 }; 151 }; 152 153 psci { 154 compatible = "arm,psci"; 155 method = "smc"; 156 cpu_suspend = <0x84000001>; 157 cpu_off = <0x84000002>; 158 cpu_on = <0x84000003>; 159 migrate = <0x84000005>; 160 }; 161 162 amba { 163 compatible = "arm,amba-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 interrupt-parent = <&gic>; 167 ranges; 168 169 pdma: pdma@20078000 { 170 compatible = "arm,pl330", "arm,primecell"; 171 reg = <0x20078000 0x4000>; 172 arm,pl330-broken-no-flushp;//2 173 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 175 #dma-cells = <1>; 176 clocks = <&cru ACLK_DMAC2>; 177 clock-names = "apb_pclk"; 178 }; 179 }; 180 181 xin24m: xin24m { 182 compatible = "fixed-clock"; 183 clock-frequency = <24000000>; 184 clock-output-names = "xin24m"; 185 #clock-cells = <0>; 186 }; 187 188 xin12m: xin12m { 189 compatible = "fixed-clock"; 190 clocks = <&xin24m>; 191 clock-frequency = <12000000>; 192 clock-output-names = "xin12m"; 193 #clock-cells = <0>; 194 }; 195 196 197 timer { 198 compatible = "arm,armv7-timer"; 199 arm,cpu-registers-not-fw-configured; 200 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 201 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 202 clock-frequency = <24000000>; 203 }; 204 205 timer@20044000 { 206 compatible = "arm,armv7-timer"; 207 reg = <0x20044000 0xb8>; 208 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 209 rockchip,broadcast = <1>; 210 }; 211 212 watchdog: wdt@2004c000 { 213 compatible = "rockchip,watch dog"; 214 reg = <0x2004c000 0x100>; 215 clock-names = "pclk_wdt"; 216 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 217 rockchip,irq = <1>; 218 rockchip,timeout = <60>; 219 rockchip,atboot = <1>; 220 rockchip,debug = <0>; 221 }; 222 223 reset: reset@20000110 { 224 compatible = "rockchip,reset"; 225 reg = <0x20000110 0x24>; 226 #reset-cells = <1>; 227 }; 228 229 nandc: nandc@10500000 { 230 compatible = "rockchip,rk-nandc"; 231 reg = <0x10500000 0x4000>; 232 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; 235 nandc_id = <0>; 236 clocks = <&cru SCLK_NANDC>, 237 <&cru HCLK_NANDC>, 238 <&cru SRST_NANDC>; 239 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; 240 }; 241 242 dmc: dmc@20004000 { 243 u-boot,dm-pre-reloc; 244 compatible = "rockchip,rk3128-dmc", "syscon"; 245 reg = <0x0 0x20004000 0x0 0x1000>; 246 }; 247 248 cru: clock-controller@20000000 { 249 u-boot,dm-pre-reloc; 250 compatible = "rockchip,rk3128-cru"; 251 reg = <0x20000000 0x1000>; 252 rockchip,grf = <&grf>; 253 #clock-cells = <1>; 254 #reset-cells = <1>; 255 assigned-clocks = <&cru PLL_GPLL>; 256 assigned-clock-rates = <594000000>; 257 }; 258 259 uart0: serial0@20060000 { 260 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 261 reg = <0x20060000 0x100>; 262 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 263 reg-shift = <2>; 264 reg-io-width = <4>; 265 clock-frequency = <24000000>; 266 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 267 clock-names = "baudclk", "apb_pclk"; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 270 dmas = <&pdma 2>, <&pdma 3>; 271 #dma-cells = <2>; 272 }; 273 274 uart1: serial1@20064000 { 275 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 276 reg = <0x20064000 0x100>; 277 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 278 reg-shift = <2>; 279 reg-io-width = <4>; 280 clock-frequency = <24000000>; 281 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 282 clock-names = "baudclk", "apb_pclk"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&uart1_xfer>; 285 dmas = <&pdma 4>, <&pdma 5>; 286 #dma-cells = <2>; 287 }; 288 289 uart2: serial2@20068000 { 290 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 291 reg = <0x20068000 0x100>; 292 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 293 reg-shift = <2>; 294 reg-io-width = <4>; 295 clock-frequency = <24000000>; 296 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 297 clock-names = "baudclk", "apb_pclk"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&uart2_xfer>; 300 dmas = <&pdma 6>, <&pdma 7>; 301 #dma-cells = <2>; 302 }; 303 304 saradc: saradc@2006c000 { 305 compatible = "rockchip,saradc"; 306 reg = <0x2006c000 0x100>; 307 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 308 #io-channel-cells = <1>; 309 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 310 clock-names = "saradc", "apb_pclk"; 311 resets = <&cru SRST_SARADC>; 312 reset-names = "saradc-apb"; 313 status = "disabled"; 314 }; 315 316 pwm0: pwm0@20050000 { 317 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 318 reg = <0x20050000 0x10>; 319 #pwm-cells = <2>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pwm0_pin>; 322 clocks = <&cru PCLK_PWM>; 323 clock-names = "pwm"; 324 }; 325 326 pwm1: pwm1@20050010 { 327 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 328 reg = <0x20050010 0x10>; 329 #pwm-cells = <2>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pwm1_pin>; 332 clocks = <&cru PCLK_PWM>; 333 clock-names = "pwm"; 334 }; 335 336 pwm2: pwm2@20050020 { 337 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 338 reg = <0x20050020 0x10>; 339 #pwm-cells = <2>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pwm2_pin>; 342 clocks = <&cru PCLK_PWM>; 343 clock-names = "pwm"; 344 }; 345 346 pwm3: pwm3@20050030 { 347 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 348 reg = <0x20050030 0x10>; 349 #pwm-cells = <2>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pwm3_pin>; 352 clocks = <&cru PCLK_PWM>; 353 clock-names = "pwm"; 354 }; 355 356 sram: sram@10080400 { 357 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 358 reg = <0x10080400 0x1C00>; 359 map-exec; 360 map-cacheable; 361 }; 362 363 pmu: syscon@100a0000 { 364 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 365 reg = <0x100a0000 0x1000>; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 }; 369 370 gic: interrupt-controller@10139000 { 371 compatible = "arm,gic-400"; 372 interrupt-controller; 373 #interrupt-cells = <3>; 374 #address-cells = <0>; 375 reg = <0x10139000 0x1000>, 376 <0x1013a000 0x1000>, 377 <0x1013c000 0x2000>, 378 <0x1013e000 0x2000>; 379 interrupts = <GIC_PPI 9 0xf04>; 380 }; 381 382 usb_otg: usb@10180000 { 383 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2"; 384 reg = <0x10180000 0x40000>; 385 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&cru HCLK_OTG0>; 387 clock-names = "otg"; 388 dr_mode = "otg"; 389 g-np-tx-fifo-size = <16>; 390 g-rx-fifo-size = <275>; 391 g-tx-fifo-size = <256 128 128 64 64 32>; 392 g-use-dma; 393 }; 394 395 usb_host: usb@101c0000 { 396 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 397 "snps,dwc2"; 398 reg = <0x101c0000 0x40000>; 399 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&cru HCLK_OTG1>; 401 clock-names = "otg"; 402 dr_mode = "host"; 403 }; 404 405 sdmmc: dwmmc@10214000 { 406 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 407 reg = <0x10214000 0x4000>; 408 max-frequency = <150000000>; 409 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 411 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 412 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 413 fifo-depth = <0x100>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 416 bus-width = <4>; 417 status = "disabled"; 418 }; 419 420 emmc: dwmmc@1021c000 { 421 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 422 reg = <0x1021c000 0x4000>; 423 max-frequency = <150000000>; 424 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 426 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 427 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 428 bus-width = <8>; 429 default-sample-phase = <158>; 430 num-slots = <1>; 431 fifo-depth = <0x100>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 434 resets = <&cru SRST_EMMC>; 435 reset-names = "reset"; 436 status = "disabled"; 437 }; 438 439 i2c0: i2c0@20072000 { 440 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 441 reg = <20072000 0x1000>; 442 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clock-names = "i2c"; 446 clocks = <&cru PCLK_I2C0>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&i2c0_xfer>; 449 }; 450 451 i2c1: i2c1@20056000 { 452 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 453 reg = <0x20056000 0x1000>; 454 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clock-names = "i2c"; 458 clocks = <&cru PCLK_I2C1>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&i2c1_xfer>; 461 }; 462 463 i2c2: i2c2@2005a000 { 464 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 465 reg = <0x2005a000 0x1000>; 466 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 clock-names = "i2c"; 470 clocks = <&cru PCLK_I2C2>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&i2c2_xfer>; 473 }; 474 475 i2c3: i2c3@2005e000 { 476 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 477 reg = <0x2005e000 0x1000>; 478 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 clock-names = "i2c"; 482 clocks = <&cru PCLK_I2C3>; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&i2c3_xfer>; 485 }; 486 487 spi0: spi@20074000 { 488 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 489 reg = <0x20074000 0x1000>; 490 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; 495 rockchip,spi-src-clk = <0>; 496 num-cs = <2>; 497 clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; 498 clock-names = "spi","pclk_spi0"; 499 dmas = <&pdma 8>, <&pdma 9>; 500 #dma-cells = <2>; 501 dma-names = "tx", "rx"; 502 }; 503 504 grf: syscon@20008000 { 505 u-boot,dm-pre-reloc; 506 compatible = "rockchip,rk3128-grf", "syscon"; 507 reg = <0x20008000 0x1000>; 508 }; 509 510 pinctrl: pinctrl@20008000 { 511 compatible = "rockchip,rk3128-pinctrl"; 512 reg = <0x20008000 0xA8>, 513 <0x200080A8 0x4C>, 514 <0x20008118 0x20>, 515 <0x20008100 0x04>; 516 reg-names = "base", "mux", "pull", "drv"; 517 rockchip,grf = <&grf>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges; 521 522 gpio0: gpio0@2007c000 { 523 compatible = "rockchip,gpio-bank"; 524 reg = <0x2007c000 0x100>; 525 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&cru PCLK_GPIO0>; 527 gpio-controller; 528 #gpio-cells = <2>; 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 }; 532 533 gpio1: gpio1@20080000 { 534 compatible = "rockchip,gpio-bank"; 535 reg = <0x20080000 0x100>; 536 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&cru PCLK_GPIO1>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 }; 543 544 gpio2: gpio2@20084000 { 545 compatible = "rockchip,gpio-bank"; 546 reg = <0x20084000 0x100>; 547 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cru PCLK_GPIO2>; 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 }; 554 555 gpio3: gpio2@20088000 { 556 compatible = "rockchip,gpio-bank"; 557 reg = <0x20088000 0x100>; 558 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cru PCLK_GPIO3>; 560 gpio-controller; 561 #gpio-cells = <2>; 562 interrupt-controller; 563 #interrupt-cells = <2>; 564 }; 565 566 pcfg_pull_up: pcfg-pull-up { 567 bias-pull-up; 568 }; 569 570 pcfg_pull_down: pcfg-pull-down { 571 bias-pull-down; 572 }; 573 574 pcfg_pull_none: pcfg-pull-none { 575 bias-disable; 576 }; 577 578 emmc { 579 /* 580 * We run eMMC at max speed; bump up drive strength. 581 * We also have external pulls, so disable the internal ones. 582 */ 583 584 emmc_clk: emmc-clk { 585 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; 586 }; 587 588 emmc_cmd: emmc-cmd { 589 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 590 }; 591 592 emmc_pwren: emmc-pwren { 593 rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; 594 }; 595 596 emmc_bus8: emmc-bus8 { 597 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 598 <1 25 RK_FUNC_2 &pcfg_pull_none>, 599 <1 26 RK_FUNC_2 &pcfg_pull_none>, 600 <1 27 RK_FUNC_2 &pcfg_pull_none>, 601 <1 28 RK_FUNC_2 &pcfg_pull_none>, 602 <1 29 RK_FUNC_2 &pcfg_pull_none>, 603 <1 30 RK_FUNC_2 &pcfg_pull_none>, 604 <1 31 RK_FUNC_2 &pcfg_pull_none>; 605 }; 606 }; 607 608 nandc{ 609 nandc_ale:nandc-ale { 610 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 611 }; 612 613 nandc_cle:nandc-cle { 614 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 615 }; 616 617 nandc_wrn:nandc-wrn { 618 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 619 }; 620 621 nandc_rdn:nandc-rdn { 622 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 623 }; 624 625 nandc_rdy:nandc-rdy { 626 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 627 }; 628 629 nandc_cs0:nandc-cs0 { 630 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 631 }; 632 633 nandc_data: nandc-data { 634 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 635 }; 636 }; 637 638 639 uart0 { 640 uart0_xfer: uart0-xfer { 641 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, 642 <0 17 RK_FUNC_1 &pcfg_pull_none>; 643 }; 644 645 uart0_cts: uart0-cts { 646 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 647 }; 648 649 uart0_rts: uart0-rts { 650 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; 651 }; 652 }; 653 654 uart1 { 655 uart1_xfer: uart1-xfer { 656 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, 657 <2 23 RK_FUNC_1 &pcfg_pull_none>; 658 }; 659 }; 660 661 uart2 { 662 uart2_xfer: uart2-xfer { 663 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, 664 <1 19 RK_FUNC_2 &pcfg_pull_none>; 665 }; 666 }; 667 668 sdmmc { 669 sdmmc_clk: sdmmc-clk { 670 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 671 }; 672 673 sdmmc_cmd: sdmmc-cmd { 674 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; 675 }; 676 677 sdmmc_wp: sdmmc-wp { 678 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; 679 }; 680 681 sdmmc_pwren: sdmmc-pwren { 682 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; 683 }; 684 685 sdmmc_bus4: sdmmc-bus4 { 686 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, 687 <1 RK_PC3 1 &pcfg_pull_up>, 688 <1 RK_PC4 1 &pcfg_pull_up>, 689 <1 RK_PC5 1 &pcfg_pull_up>; 690 }; 691 }; 692 693 pwm0 { 694 pwm0_pin: pwm0-pin { 695 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 696 }; 697 }; 698 699 pwm1 { 700 pwm1_pin: pwm1-pin { 701 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; 702 }; 703 }; 704 705 pwm2 { 706 pwm2_pin: pwm2-pin { 707 rockchip,pins = <0 1 2 &pcfg_pull_none>; 708 }; 709 }; 710 711 pwm3 { 712 pwm3_pin: pwm3-pin { 713 rockchip,pins = <0 27 1 &pcfg_pull_none>; 714 }; 715 }; 716 717 i2c0 { 718 i2c0_xfer: i2c0-xfer { 719 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, 720 <0 1 RK_FUNC_1 &pcfg_pull_none>; 721 }; 722 }; 723 724 i2c1 { 725 i2c1_xfer: i2c1-xfer { 726 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 727 <0 3 RK_FUNC_1 &pcfg_pull_none>; 728 }; 729 }; 730 731 i2c2 { 732 i2c2_xfer: i2c2-xfer { 733 rockchip,pins = <2 20 3 &pcfg_pull_none>, 734 <2 21 3 &pcfg_pull_none>; 735 }; 736 }; 737 738 i2c3 { 739 i2c3_xfer: i2c3-xfer { 740 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 741 <0 7 RK_FUNC_1 &pcfg_pull_none>; 742 }; 743 }; 744 745 spi0 { 746 spi0_txd_mux0:spi0-txd-mux0 { 747 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 748 }; 749 750 spi0_rxd_mux0:spi0-rxd-mux0 { 751 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 752 }; 753 754 spi0_clk_mux0:spi0-clk-mux0 { 755 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 756 }; 757 758 spi0_cs0_mux0:spi0-cs0-mux0 { 759 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 760 }; 761 762 spi0_cs1_mux0:spi0-cs1-mux0 { 763 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 764 }; 765 }; 766 767 }; 768}; 769