1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include <dt-bindings/media/rockchip_mipi_dsi.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3128"; 17 rockchip,sram = <&sram>; 18 interrupt-parent = <&gic>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 spi0 = &spi0; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 }; 38 39 memory { 40 device_type = "memory"; 41 reg = <0x60000000 0x40000000>; 42 }; 43 44 arm-pmu { 45 compatible = "arm,cortex-a7-pmu"; 46 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 enable-method = "rockchip,rk3128-smp"; 56 57 cpu0:cpu@0x000 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0x000>; 61 operating-points = < 62 /* KHz uV */ 63 816000 1000000 64 >; 65 #cooling-cells = <2>; /* min followed by max */ 66 clock-latency = <40000>; 67 clocks = <&cru ARMCLK>; 68 }; 69 70 cpu1:cpu@0x001 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a7"; 73 reg = <0x001>; 74 }; 75 76 cpu2:cpu@0x002 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <0x002>; 80 }; 81 82 cpu3:cpu@0x003 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a7"; 85 reg = <0x003>; 86 }; 87 }; 88 89 cpu_axi_bus: cpu_axi_bus { 90 compatible = "rockchip,cpu_axi_bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges; 94 95 qos { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 100 crypto { 101 reg = <0x10128080 0x20>; 102 }; 103 104 core { 105 reg = <0x1012a000 0x20>; 106 }; 107 108 peri { 109 reg = <0x1012c000 0x20>; 110 }; 111 112 gpu { 113 reg = <0x1012d000 0x20>; 114 }; 115 116 vpu { 117 reg = <0x1012e000 0x20>; 118 }; 119 120 rga { 121 reg = <0x1012f000 0x20>; 122 }; 123 ebc { 124 reg = <0x1012f080 0x20>; 125 }; 126 127 iep { 128 reg = <0x1012f100 0x20>; 129 }; 130 131 lcdc { 132 reg = <0x1012f180 0x20>; 133 rockchip,priority = <3 3>; 134 }; 135 136 vip { 137 reg = <0x1012f200 0x20>; 138 rockchip,priority = <3 3>; 139 }; 140 }; 141 142 msch { 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges; 146 147 msch@10128000 { 148 reg = <0x10128000 0x20>; 149 rockchip,read-latency = <0x3f>; 150 }; 151 }; 152 }; 153 154 psci { 155 compatible = "arm,psci"; 156 method = "smc"; 157 cpu_suspend = <0x84000001>; 158 cpu_off = <0x84000002>; 159 cpu_on = <0x84000003>; 160 migrate = <0x84000005>; 161 }; 162 163 amba { 164 compatible = "arm,amba-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 interrupt-parent = <&gic>; 168 ranges; 169 170 pdma: pdma@20078000 { 171 compatible = "arm,pl330", "arm,primecell"; 172 reg = <0x20078000 0x4000>; 173 arm,pl330-broken-no-flushp;//2 174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 clocks = <&cru ACLK_DMAC2>; 178 clock-names = "apb_pclk"; 179 }; 180 }; 181 182 xin24m: xin24m { 183 compatible = "fixed-clock"; 184 clock-frequency = <24000000>; 185 clock-output-names = "xin24m"; 186 #clock-cells = <0>; 187 }; 188 189 xin12m: xin12m { 190 compatible = "fixed-clock"; 191 clocks = <&xin24m>; 192 clock-frequency = <12000000>; 193 clock-output-names = "xin12m"; 194 #clock-cells = <0>; 195 }; 196 197 198 timer { 199 compatible = "arm,armv7-timer"; 200 arm,cpu-registers-not-fw-configured; 201 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 202 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 203 clock-frequency = <24000000>; 204 }; 205 206 timer@20044000 { 207 compatible = "arm,armv7-timer"; 208 reg = <0x20044000 0xb8>; 209 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 210 rockchip,broadcast = <1>; 211 }; 212 213 watchdog: wdt@2004c000 { 214 compatible = "rockchip,watch dog"; 215 reg = <0x2004c000 0x100>; 216 clock-names = "pclk_wdt"; 217 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 218 rockchip,irq = <1>; 219 rockchip,timeout = <60>; 220 rockchip,atboot = <1>; 221 rockchip,debug = <0>; 222 }; 223 224 reset: reset@20000110 { 225 compatible = "rockchip,reset"; 226 reg = <0x20000110 0x24>; 227 #reset-cells = <1>; 228 }; 229 230 nandc: nandc@10500000 { 231 compatible = "rockchip,rk-nandc"; 232 reg = <0x10500000 0x4000>; 233 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; 236 nandc_id = <0>; 237 clocks = <&cru SCLK_NANDC>, 238 <&cru HCLK_NANDC>, 239 <&cru SRST_NANDC>; 240 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; 241 }; 242 243 dmc: dmc@20004000 { 244 compatible = "rockchip,rk3128-dmc", "syscon"; 245 reg = <0x0 0x20004000 0x0 0x1000>; 246 }; 247 248 cru: clock-controller@20000000 { 249 compatible = "rockchip,rk3128-cru"; 250 reg = <0x20000000 0x1000>; 251 rockchip,grf = <&grf>; 252 #clock-cells = <1>; 253 #reset-cells = <1>; 254 assigned-clocks = <&cru PLL_GPLL>; 255 assigned-clock-rates = <594000000>; 256 }; 257 258 uart0: serial0@20060000 { 259 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 260 reg = <0x20060000 0x100>; 261 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 clock-frequency = <24000000>; 265 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 266 clock-names = "baudclk", "apb_pclk"; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 269 dmas = <&pdma 2>, <&pdma 3>; 270 #dma-cells = <2>; 271 }; 272 273 uart1: serial1@20064000 { 274 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 275 reg = <0x20064000 0x100>; 276 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 277 reg-shift = <2>; 278 reg-io-width = <4>; 279 clock-frequency = <24000000>; 280 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 281 clock-names = "baudclk", "apb_pclk"; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&uart1_xfer>; 284 dmas = <&pdma 4>, <&pdma 5>; 285 #dma-cells = <2>; 286 }; 287 288 uart2: serial2@20068000 { 289 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 290 reg = <0x20068000 0x100>; 291 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 292 reg-shift = <2>; 293 reg-io-width = <4>; 294 clock-frequency = <24000000>; 295 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 296 clock-names = "baudclk", "apb_pclk"; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&uart2_xfer>; 299 dmas = <&pdma 6>, <&pdma 7>; 300 #dma-cells = <2>; 301 }; 302 303 saradc: saradc@2006c000 { 304 compatible = "rockchip,saradc"; 305 reg = <0x2006c000 0x100>; 306 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 307 #io-channel-cells = <1>; 308 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 309 clock-names = "saradc", "apb_pclk"; 310 resets = <&cru SRST_SARADC>; 311 reset-names = "saradc-apb"; 312 status = "disabled"; 313 }; 314 315 pwm0: pwm0@20050000 { 316 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 317 reg = <0x20050000 0x10>; 318 #pwm-cells = <3>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pwm0_pin>; 321 clocks = <&cru PCLK_PWM>; 322 clock-names = "pwm"; 323 }; 324 325 pwm1: pwm1@20050010 { 326 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 327 reg = <0x20050010 0x10>; 328 #pwm-cells = <2>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pwm1_pin>; 331 clocks = <&cru PCLK_PWM>; 332 clock-names = "pwm"; 333 }; 334 335 pwm2: pwm2@20050020 { 336 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 337 reg = <0x20050020 0x10>; 338 #pwm-cells = <2>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pwm2_pin>; 341 clocks = <&cru PCLK_PWM>; 342 clock-names = "pwm"; 343 }; 344 345 pwm3: pwm3@20050030 { 346 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 347 reg = <0x20050030 0x10>; 348 #pwm-cells = <2>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pwm3_pin>; 351 clocks = <&cru PCLK_PWM>; 352 clock-names = "pwm"; 353 }; 354 355 sram: sram@10080400 { 356 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 357 reg = <0x10080400 0x1C00>; 358 map-exec; 359 map-cacheable; 360 }; 361 362 pmu: syscon@100a0000 { 363 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 364 reg = <0x100a0000 0x1000>; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 }; 368 369 vop: vop@1010e000 { 370 compatible = "rockchip,rk3126-vop"; 371 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>; 372 reg-names = "regs", "gamma_lut"; 373 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cru ACLK_VIO0>, <&cru DCLK_LCDC>, <&cru HCLK_LCDC>; 375 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 376 status = "disabled"; 377 378 vop_out: port { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 382 vop_out_lvds: endpoint@1 { 383 reg = <1>; 384 remote-endpoint = <&lvds_in_vop>; 385 }; 386 387 vop_out_dsi: endpoint@2 { 388 reg = <1>; 389 remote-endpoint = <&dsi_in_vop>; 390 }; 391 }; 392 }; 393 394 dsi: dsi@10110000 { 395 compatible = "rockchip,rk312x-mipi-dsi"; 396 reg = <0x10110000 0x4000>; 397 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&mipi_dphy>; 399 clock-names = "pclk", "h2p", "hs_clk"; 400 resets = <&cru SRST_VIO_MIPI_DSI>; 401 reset-names = "apb"; 402 phys = <&mipi_dphy>; 403 phy-names = "mipi_dphy"; 404 rockchip,grf = <&grf>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 409 ports { 410 port { 411 dsi_in_vop: endpoint { 412 remote-endpoint = <&vop_out_dsi>; 413 }; 414 }; 415 }; 416 }; 417 418 display_subsystem: display-subsystem { 419 compatible = "rockchip,display-subsystem"; 420 ports = <&vop_out>; 421 422 route { 423 route_lvds: route-lvds { 424 logo,uboot = "logo.bmp"; 425 logo,kernel = "logo_kernel.bmp"; 426 logo,mode = "fullscreen"; 427 charge_logo,mode = "center"; 428 connect = <&vop_out_lvds>; 429 }; 430 431 route_dsi: route-dsi { 432 logo,uboot = "logo.bmp"; 433 logo,kernel = "logo_kernel.bmp"; 434 logo,mode = "fullscreen"; 435 charge_logo,mode = "center"; 436 connect = <&vop_out_dsi>; 437 }; 438 }; 439 }; 440 441 gic: interrupt-controller@10139000 { 442 compatible = "arm,gic-400"; 443 interrupt-controller; 444 #interrupt-cells = <3>; 445 #address-cells = <0>; 446 reg = <0x10139000 0x1000>, 447 <0x1013a000 0x1000>, 448 <0x1013c000 0x2000>, 449 <0x1013e000 0x2000>; 450 interrupts = <GIC_PPI 9 0xf04>; 451 }; 452 453 u2phy: usb2-phy { 454 compatible = "rockchip,rk3128-usb2phy"; 455 reg = <0x017c 0x0c>; 456 rockchip,grf = <&grf>; 457 clocks = <&cru SCLK_OTGPHY0>; 458 clock-names = "phyclk"; 459 #clock-cells = <0>; 460 clock-output-names = "usb480m_phy"; 461 #phy-cells = <1>; 462 status = "disabled"; 463 464 u2phy_otg: otg-port { 465 #phy-cells = <0>; 466 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-names = "otg-bvalid", "otg-id", 470 "linestate"; 471 status = "disabled"; 472 }; 473 474 u2phy_host: host-port { 475 #phy-cells = <0>; 476 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-names = "linestate"; 478 status = "disabled"; 479 }; 480 }; 481 482 usb_otg: usb@10180000 { 483 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", 484 "snps,dwc2"; 485 reg = <0x10180000 0x40000>; 486 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 487 dr_mode = "otg"; 488 g-use-dma; 489 hnp-srp-disable; 490 phys = <&u2phy 0>; 491 phy-names = "usb"; 492 status = "disabled"; 493 }; 494 495 usb_host_ehci: usb@101c0000 { 496 compatible = "generic-ehci"; 497 reg = <0x101c0000 0x20000>; 498 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 499 phys = <&u2phy 1>; 500 phy-names = "usb"; 501 status = "disabled"; 502 }; 503 504 usb_host_ohci: usb@101e0000 { 505 compatible = "generic-ohci"; 506 reg = <0x101e0000 0x20000>; 507 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 508 phys = <&u2phy 1>; 509 phy-names = "usb"; 510 status = "disabled"; 511 }; 512 513 sdmmc: dwmmc@10214000 { 514 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 515 reg = <0x10214000 0x4000>; 516 max-frequency = <150000000>; 517 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 519 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 520 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 521 fifo-depth = <0x100>; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 524 bus-width = <4>; 525 status = "disabled"; 526 }; 527 528 emmc: dwmmc@1021c000 { 529 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 530 reg = <0x1021c000 0x4000>; 531 max-frequency = <150000000>; 532 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 534 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 535 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 536 bus-width = <8>; 537 default-sample-phase = <158>; 538 num-slots = <1>; 539 fifo-depth = <0x100>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 542 resets = <&cru SRST_EMMC>; 543 reset-names = "reset"; 544 status = "disabled"; 545 }; 546 547 mipi_dphy: mipi-dphy@20038000 { 548 compatible = "rockchip,rk312x-mipi-dphy"; 549 reg = <0x20038000 0x4000>; 550 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, <&cru HCLK_VIO_H2P>; 551 clock-names = "ref", "pclk", "h2p"; 552 clock-output-names = "mipi_dphy_pll"; 553 #clock-cells = <0>; 554 resets = <&cru SRST_MIPIPHY_P>; 555 reset-names = "apb"; 556 #phy-cells = <0>; 557 status = "disabled"; 558 }; 559 560 lvds: lvds@20038000 { 561 compatible = "rockchip,rk3126-lvds"; 562 reg = <0x20038000 0x4000>, <0x10110000 0x100>; 563 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 564 rockchip,grf = <&grf>; 565 status = "disabled"; 566 567 ports { 568 #address-cells = <1>; 569 #size-cells = <0>; 570 571 lvds_in: port@0 { 572 reg = <0>; 573 lvds_in_vop: endpoint { 574 remote-endpoint = <&vop_out_lvds>; 575 }; 576 }; 577 }; 578 }; 579 580 i2c0: i2c0@20072000 { 581 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 582 reg = <0x20072000 0x1000>; 583 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 clock-names = "i2c"; 587 clocks = <&cru PCLK_I2C0>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&i2c0_xfer>; 590 }; 591 592 i2c1: i2c1@20056000 { 593 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 594 reg = <0x20056000 0x1000>; 595 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 clock-names = "i2c"; 599 clocks = <&cru PCLK_I2C1>; 600 pinctrl-names = "default"; 601 pinctrl-0 = <&i2c1_xfer>; 602 }; 603 604 i2c2: i2c2@2005a000 { 605 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 606 reg = <0x2005a000 0x1000>; 607 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 clock-names = "i2c"; 611 clocks = <&cru PCLK_I2C2>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&i2c2_xfer>; 614 }; 615 616 i2c3: i2c3@2005e000 { 617 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 618 reg = <0x2005e000 0x1000>; 619 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 clock-names = "i2c"; 623 clocks = <&cru PCLK_I2C3>; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&i2c3_xfer>; 626 }; 627 628 spi0: spi@20074000 { 629 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 630 reg = <0x20074000 0x1000>; 631 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; 636 rockchip,spi-src-clk = <0>; 637 num-cs = <2>; 638 clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; 639 clock-names = "spi","pclk_spi0"; 640 dmas = <&pdma 8>, <&pdma 9>; 641 #dma-cells = <2>; 642 dma-names = "tx", "rx"; 643 }; 644 645 grf: syscon@20008000 { 646 compatible = "rockchip,rk3128-grf", "syscon"; 647 reg = <0x20008000 0x1000>; 648 }; 649 650 pinctrl: pinctrl@20008000 { 651 compatible = "rockchip,rk3128-pinctrl"; 652 reg = <0x20008000 0xA8>, 653 <0x200080A8 0x4C>, 654 <0x20008118 0x20>, 655 <0x20008100 0x04>; 656 reg-names = "base", "mux", "pull", "drv"; 657 rockchip,grf = <&grf>; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 ranges; 661 662 gpio0: gpio0@2007c000 { 663 compatible = "rockchip,gpio-bank"; 664 reg = <0x2007c000 0x100>; 665 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cru PCLK_GPIO0>; 667 gpio-controller; 668 #gpio-cells = <2>; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 673 gpio1: gpio1@20080000 { 674 compatible = "rockchip,gpio-bank"; 675 reg = <0x20080000 0x100>; 676 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cru PCLK_GPIO1>; 678 gpio-controller; 679 #gpio-cells = <2>; 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 684 gpio2: gpio2@20084000 { 685 compatible = "rockchip,gpio-bank"; 686 reg = <0x20084000 0x100>; 687 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cru PCLK_GPIO2>; 689 gpio-controller; 690 #gpio-cells = <2>; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 695 gpio3: gpio2@20088000 { 696 compatible = "rockchip,gpio-bank"; 697 reg = <0x20088000 0x100>; 698 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru PCLK_GPIO3>; 700 gpio-controller; 701 #gpio-cells = <2>; 702 interrupt-controller; 703 #interrupt-cells = <2>; 704 }; 705 706 pcfg_pull_up: pcfg-pull-up { 707 bias-pull-up; 708 }; 709 710 pcfg_pull_down: pcfg-pull-down { 711 bias-pull-down; 712 }; 713 714 pcfg_pull_none: pcfg-pull-none { 715 bias-disable; 716 }; 717 718 emmc { 719 /* 720 * We run eMMC at max speed; bump up drive strength. 721 * We also have external pulls, so disable the internal ones. 722 */ 723 724 emmc_clk: emmc-clk { 725 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; 726 }; 727 728 emmc_cmd: emmc-cmd { 729 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 730 }; 731 732 emmc_pwren: emmc-pwren { 733 rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; 734 }; 735 736 emmc_bus8: emmc-bus8 { 737 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 738 <1 25 RK_FUNC_2 &pcfg_pull_none>, 739 <1 26 RK_FUNC_2 &pcfg_pull_none>, 740 <1 27 RK_FUNC_2 &pcfg_pull_none>, 741 <1 28 RK_FUNC_2 &pcfg_pull_none>, 742 <1 29 RK_FUNC_2 &pcfg_pull_none>, 743 <1 30 RK_FUNC_2 &pcfg_pull_none>, 744 <1 31 RK_FUNC_2 &pcfg_pull_none>; 745 }; 746 }; 747 748 nandc{ 749 nandc_ale:nandc-ale { 750 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 751 }; 752 753 nandc_cle:nandc-cle { 754 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 755 }; 756 757 nandc_wrn:nandc-wrn { 758 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 759 }; 760 761 nandc_rdn:nandc-rdn { 762 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 763 }; 764 765 nandc_rdy:nandc-rdy { 766 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 767 }; 768 769 nandc_cs0:nandc-cs0 { 770 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 771 }; 772 773 nandc_data: nandc-data { 774 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 775 }; 776 }; 777 778 779 uart0 { 780 uart0_xfer: uart0-xfer { 781 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, 782 <0 17 RK_FUNC_1 &pcfg_pull_none>; 783 }; 784 785 uart0_cts: uart0-cts { 786 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 787 }; 788 789 uart0_rts: uart0-rts { 790 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; 791 }; 792 }; 793 794 uart1 { 795 uart1_xfer: uart1-xfer { 796 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, 797 <2 23 RK_FUNC_1 &pcfg_pull_none>; 798 }; 799 }; 800 801 uart2 { 802 uart2_xfer: uart2-xfer { 803 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, 804 <1 19 RK_FUNC_2 &pcfg_pull_none>; 805 }; 806 }; 807 808 sdmmc { 809 sdmmc_clk: sdmmc-clk { 810 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 811 }; 812 813 sdmmc_cmd: sdmmc-cmd { 814 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; 815 }; 816 817 sdmmc_wp: sdmmc-wp { 818 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; 819 }; 820 821 sdmmc_pwren: sdmmc-pwren { 822 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; 823 }; 824 825 sdmmc_bus4: sdmmc-bus4 { 826 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, 827 <1 RK_PC3 1 &pcfg_pull_up>, 828 <1 RK_PC4 1 &pcfg_pull_up>, 829 <1 RK_PC5 1 &pcfg_pull_up>; 830 }; 831 }; 832 833 pwm0 { 834 pwm0_pin: pwm0-pin { 835 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 836 }; 837 }; 838 839 pwm1 { 840 pwm1_pin: pwm1-pin { 841 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; 842 }; 843 }; 844 845 pwm2 { 846 pwm2_pin: pwm2-pin { 847 rockchip,pins = <0 1 2 &pcfg_pull_none>; 848 }; 849 }; 850 851 pwm3 { 852 pwm3_pin: pwm3-pin { 853 rockchip,pins = <0 27 1 &pcfg_pull_none>; 854 }; 855 }; 856 857 i2c0 { 858 i2c0_xfer: i2c0-xfer { 859 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, 860 <0 1 RK_FUNC_1 &pcfg_pull_none>; 861 }; 862 }; 863 864 i2c1 { 865 i2c1_xfer: i2c1-xfer { 866 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 867 <0 3 RK_FUNC_1 &pcfg_pull_none>; 868 }; 869 }; 870 871 i2c2 { 872 i2c2_xfer: i2c2-xfer { 873 rockchip,pins = <2 20 3 &pcfg_pull_none>, 874 <2 21 3 &pcfg_pull_none>; 875 }; 876 }; 877 878 i2c3 { 879 i2c3_xfer: i2c3-xfer { 880 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 881 <0 7 RK_FUNC_1 &pcfg_pull_none>; 882 }; 883 }; 884 885 spi0 { 886 spi0_txd_mux0:spi0-txd-mux0 { 887 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 888 }; 889 890 spi0_rxd_mux0:spi0-rxd-mux0 { 891 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 892 }; 893 894 spi0_clk_mux0:spi0-clk-mux0 { 895 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 896 }; 897 898 spi0_cs0_mux0:spi0-cs0-mux0 { 899 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 900 }; 901 902 spi0_cs1_mux0:spi0-cs1-mux0 { 903 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 904 }; 905 }; 906 907 }; 908}; 909
