1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include <dt-bindings/media/rockchip_mipi_dsi.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3128"; 17 rockchip,sram = <&sram>; 18 interrupt-parent = <&gic>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 spi0 = &spi0; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 }; 38 39 memory { 40 device_type = "memory"; 41 reg = <0x60000000 0x40000000>; 42 }; 43 44 arm-pmu { 45 compatible = "arm,cortex-a7-pmu"; 46 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 enable-method = "rockchip,rk3128-smp"; 56 57 cpu0:cpu@0x000 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0x000>; 61 operating-points = < 62 /* KHz uV */ 63 816000 1000000 64 >; 65 #cooling-cells = <2>; /* min followed by max */ 66 clock-latency = <40000>; 67 clocks = <&cru ARMCLK>; 68 }; 69 70 cpu1:cpu@0x001 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a7"; 73 reg = <0x001>; 74 }; 75 76 cpu2:cpu@0x002 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <0x002>; 80 }; 81 82 cpu3:cpu@0x003 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a7"; 85 reg = <0x003>; 86 }; 87 }; 88 89 cpu_axi_bus: cpu_axi_bus { 90 compatible = "rockchip,cpu_axi_bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges; 94 95 qos { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 100 crypto { 101 reg = <0x10128080 0x20>; 102 }; 103 104 core { 105 reg = <0x1012a000 0x20>; 106 }; 107 108 peri { 109 reg = <0x1012c000 0x20>; 110 }; 111 112 gpu { 113 reg = <0x1012d000 0x20>; 114 }; 115 116 vpu { 117 reg = <0x1012e000 0x20>; 118 }; 119 120 rga { 121 reg = <0x1012f000 0x20>; 122 }; 123 ebc { 124 reg = <0x1012f080 0x20>; 125 }; 126 127 iep { 128 reg = <0x1012f100 0x20>; 129 }; 130 131 lcdc { 132 reg = <0x1012f180 0x20>; 133 rockchip,priority = <3 3>; 134 }; 135 136 vip { 137 reg = <0x1012f200 0x20>; 138 rockchip,priority = <3 3>; 139 }; 140 }; 141 142 msch { 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges; 146 147 msch@10128000 { 148 reg = <0x10128000 0x20>; 149 rockchip,read-latency = <0x3f>; 150 }; 151 }; 152 }; 153 154 psci { 155 compatible = "arm,psci"; 156 method = "smc"; 157 cpu_suspend = <0x84000001>; 158 cpu_off = <0x84000002>; 159 cpu_on = <0x84000003>; 160 migrate = <0x84000005>; 161 }; 162 163 amba { 164 compatible = "arm,amba-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 interrupt-parent = <&gic>; 168 ranges; 169 170 pdma: pdma@20078000 { 171 compatible = "arm,pl330", "arm,primecell"; 172 reg = <0x20078000 0x4000>; 173 arm,pl330-broken-no-flushp;//2 174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 clocks = <&cru ACLK_DMAC2>; 178 clock-names = "apb_pclk"; 179 }; 180 }; 181 182 xin24m: xin24m { 183 compatible = "fixed-clock"; 184 clock-frequency = <24000000>; 185 clock-output-names = "xin24m"; 186 #clock-cells = <0>; 187 }; 188 189 xin12m: xin12m { 190 compatible = "fixed-clock"; 191 clocks = <&xin24m>; 192 clock-frequency = <12000000>; 193 clock-output-names = "xin12m"; 194 #clock-cells = <0>; 195 }; 196 197 198 timer { 199 compatible = "arm,armv7-timer"; 200 arm,cpu-registers-not-fw-configured; 201 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 202 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 203 clock-frequency = <24000000>; 204 }; 205 206 timer@20044000 { 207 compatible = "arm,armv7-timer"; 208 reg = <0x20044000 0xb8>; 209 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 210 rockchip,broadcast = <1>; 211 }; 212 213 watchdog: wdt@2004c000 { 214 compatible = "rockchip,watch dog"; 215 reg = <0x2004c000 0x100>; 216 clock-names = "pclk_wdt"; 217 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 218 rockchip,irq = <1>; 219 rockchip,timeout = <60>; 220 rockchip,atboot = <1>; 221 rockchip,debug = <0>; 222 }; 223 224 reset: reset@20000110 { 225 compatible = "rockchip,reset"; 226 reg = <0x20000110 0x24>; 227 #reset-cells = <1>; 228 }; 229 nandc: nandc@10500000 { 230 compatible = "rockchip,rk-nandc"; 231 reg = <0x10500000 0x4000>; 232 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 233 nandc_id = <0>; 234 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 235 clock-names = "clk_nandc", "hclk_nandc"; 236 status = "disabled"; 237 }; 238 239 dmc: dmc@20004000 { 240 compatible = "rockchip,rk3128-dmc", "syscon"; 241 reg = <0x0 0x20004000 0x0 0x1000>; 242 }; 243 244 cru: clock-controller@20000000 { 245 compatible = "rockchip,rk3128-cru"; 246 reg = <0x20000000 0x1000>; 247 rockchip,grf = <&grf>; 248 #clock-cells = <1>; 249 #reset-cells = <1>; 250 assigned-clocks = <&cru PLL_GPLL>; 251 assigned-clock-rates = <594000000>; 252 }; 253 254 uart0: serial0@20060000 { 255 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 256 reg = <0x20060000 0x100>; 257 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 258 reg-shift = <2>; 259 reg-io-width = <4>; 260 clock-frequency = <24000000>; 261 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 262 clock-names = "baudclk", "apb_pclk"; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 265 dmas = <&pdma 2>, <&pdma 3>; 266 #dma-cells = <2>; 267 }; 268 269 uart1: serial1@20064000 { 270 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 271 reg = <0x20064000 0x100>; 272 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 273 reg-shift = <2>; 274 reg-io-width = <4>; 275 clock-frequency = <24000000>; 276 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 277 clock-names = "baudclk", "apb_pclk"; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&uart1_xfer>; 280 dmas = <&pdma 4>, <&pdma 5>; 281 #dma-cells = <2>; 282 }; 283 284 uart2: serial2@20068000 { 285 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 286 reg = <0x20068000 0x100>; 287 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 288 reg-shift = <2>; 289 reg-io-width = <4>; 290 clock-frequency = <24000000>; 291 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 292 clock-names = "baudclk", "apb_pclk"; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&uart2_xfer>; 295 dmas = <&pdma 6>, <&pdma 7>; 296 #dma-cells = <2>; 297 }; 298 299 saradc: saradc@2006c000 { 300 compatible = "rockchip,saradc"; 301 reg = <0x2006c000 0x100>; 302 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 303 #io-channel-cells = <1>; 304 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 305 clock-names = "saradc", "apb_pclk"; 306 resets = <&cru SRST_SARADC>; 307 reset-names = "saradc-apb"; 308 status = "disabled"; 309 }; 310 311 pwm0: pwm0@20050000 { 312 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 313 reg = <0x20050000 0x10>; 314 #pwm-cells = <3>; 315 pinctrl-names = "active"; 316 pinctrl-0 = <&pwm0_pin>; 317 clocks = <&cru PCLK_PWM>; 318 clock-names = "pwm"; 319 }; 320 321 pwm1: pwm1@20050010 { 322 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 323 reg = <0x20050010 0x10>; 324 #pwm-cells = <2>; 325 pinctrl-names = "active"; 326 pinctrl-0 = <&pwm1_pin>; 327 clocks = <&cru PCLK_PWM>; 328 clock-names = "pwm"; 329 }; 330 331 pwm2: pwm2@20050020 { 332 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 333 reg = <0x20050020 0x10>; 334 #pwm-cells = <2>; 335 pinctrl-names = "active"; 336 pinctrl-0 = <&pwm2_pin>; 337 clocks = <&cru PCLK_PWM>; 338 clock-names = "pwm"; 339 }; 340 341 pwm3: pwm3@20050030 { 342 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 343 reg = <0x20050030 0x10>; 344 #pwm-cells = <2>; 345 pinctrl-names = "active"; 346 pinctrl-0 = <&pwm3_pin>; 347 clocks = <&cru PCLK_PWM>; 348 clock-names = "pwm"; 349 }; 350 351 sram: sram@10080400 { 352 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 353 reg = <0x10080400 0x1C00>; 354 map-exec; 355 map-cacheable; 356 }; 357 358 pmu: syscon@100a0000 { 359 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 360 reg = <0x100a0000 0x1000>; 361 #address-cells = <1>; 362 #size-cells = <1>; 363 }; 364 365 vop: vop@1010e000 { 366 compatible = "rockchip,rk3126-vop"; 367 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>; 368 reg-names = "regs", "gamma_lut"; 369 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cru ACLK_VIO0>, <&cru DCLK_LCDC>, <&cru HCLK_LCDC>; 371 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 372 status = "disabled"; 373 374 vop_out: port { 375 #address-cells = <1>; 376 #size-cells = <0>; 377 378 vop_out_lvds: endpoint@1 { 379 reg = <1>; 380 remote-endpoint = <&lvds_in_vop>; 381 }; 382 383 vop_out_dsi: endpoint@2 { 384 reg = <1>; 385 remote-endpoint = <&dsi_in_vop>; 386 }; 387 }; 388 }; 389 390 dsi: dsi@10110000 { 391 compatible = "rockchip,rk3128-mipi-dsi"; 392 reg = <0x10110000 0x4000>; 393 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&mipi_dphy>; 395 clock-names = "pclk", "h2p", "hs_clk"; 396 resets = <&cru SRST_VIO_MIPI_DSI>; 397 reset-names = "apb"; 398 phys = <&mipi_dphy>; 399 phy-names = "mipi_dphy"; 400 rockchip,grf = <&grf>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 status = "disabled"; 404 405 ports { 406 port { 407 dsi_in_vop: endpoint { 408 remote-endpoint = <&vop_out_dsi>; 409 }; 410 }; 411 }; 412 }; 413 414 display_subsystem: display-subsystem { 415 compatible = "rockchip,display-subsystem"; 416 ports = <&vop_out>; 417 418 route { 419 route_lvds: route-lvds { 420 logo,uboot = "logo.bmp"; 421 logo,kernel = "logo_kernel.bmp"; 422 logo,mode = "fullscreen"; 423 charge_logo,mode = "center"; 424 connect = <&vop_out_lvds>; 425 }; 426 427 route_dsi: route-dsi { 428 logo,uboot = "logo.bmp"; 429 logo,kernel = "logo_kernel.bmp"; 430 logo,mode = "fullscreen"; 431 charge_logo,mode = "center"; 432 connect = <&vop_out_dsi>; 433 }; 434 }; 435 }; 436 437 gic: interrupt-controller@10139000 { 438 compatible = "arm,gic-400"; 439 interrupt-controller; 440 #interrupt-cells = <3>; 441 #address-cells = <0>; 442 reg = <0x10139000 0x1000>, 443 <0x1013a000 0x1000>, 444 <0x1013c000 0x2000>, 445 <0x1013e000 0x2000>; 446 interrupts = <GIC_PPI 9 0xf04>; 447 }; 448 449 u2phy: usb2-phy { 450 compatible = "rockchip,rk3128-usb2phy"; 451 reg = <0x017c 0x0c>; 452 rockchip,grf = <&grf>; 453 clocks = <&cru SCLK_OTGPHY0>; 454 clock-names = "phyclk"; 455 #clock-cells = <0>; 456 clock-output-names = "usb480m_phy"; 457 #phy-cells = <1>; 458 status = "disabled"; 459 460 u2phy_otg: otg-port { 461 #phy-cells = <0>; 462 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "otg-bvalid", "otg-id", 466 "linestate"; 467 status = "disabled"; 468 }; 469 470 u2phy_host: host-port { 471 #phy-cells = <0>; 472 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 473 interrupt-names = "linestate"; 474 status = "disabled"; 475 }; 476 }; 477 478 usb_otg: usb@10180000 { 479 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", 480 "snps,dwc2"; 481 reg = <0x10180000 0x40000>; 482 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 483 dr_mode = "otg"; 484 g-use-dma; 485 hnp-srp-disable; 486 phys = <&u2phy 0>; 487 phy-names = "usb"; 488 status = "disabled"; 489 }; 490 491 usb_host_ehci: usb@101c0000 { 492 compatible = "generic-ehci"; 493 reg = <0x101c0000 0x20000>; 494 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 495 phys = <&u2phy 1>; 496 phy-names = "usb"; 497 status = "disabled"; 498 }; 499 500 usb_host_ohci: usb@101e0000 { 501 compatible = "generic-ohci"; 502 reg = <0x101e0000 0x20000>; 503 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 504 phys = <&u2phy 1>; 505 phy-names = "usb"; 506 status = "disabled"; 507 }; 508 509 sdmmc: dwmmc@10214000 { 510 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 511 reg = <0x10214000 0x4000>; 512 max-frequency = <150000000>; 513 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 515 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 516 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 517 fifo-depth = <0x100>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 520 bus-width = <4>; 521 status = "disabled"; 522 }; 523 524 emmc: dwmmc@1021c000 { 525 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 526 reg = <0x1021c000 0x4000>; 527 max-frequency = <150000000>; 528 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 530 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 531 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 532 bus-width = <8>; 533 default-sample-phase = <158>; 534 num-slots = <1>; 535 fifo-depth = <0x100>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 538 resets = <&cru SRST_EMMC>; 539 reset-names = "reset"; 540 status = "disabled"; 541 }; 542 543 mipi_dphy: mipi-dphy@20038000 { 544 compatible = "rockchip,rk3128-mipi-dphy"; 545 reg = <0x20038000 0x4000>; 546 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, <&cru HCLK_VIO_H2P>; 547 clock-names = "ref", "pclk", "h2p"; 548 clock-output-names = "mipi_dphy_pll"; 549 #clock-cells = <0>; 550 resets = <&cru SRST_MIPIPHY_P>; 551 reset-names = "apb"; 552 #phy-cells = <0>; 553 status = "disabled"; 554 }; 555 556 lvds: lvds@20038000 { 557 compatible = "rockchip,rk3126-lvds"; 558 reg = <0x20038000 0x4000>, <0x10110000 0x100>; 559 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 560 rockchip,grf = <&grf>; 561 status = "disabled"; 562 563 ports { 564 #address-cells = <1>; 565 #size-cells = <0>; 566 567 lvds_in: port@0 { 568 reg = <0>; 569 lvds_in_vop: endpoint { 570 remote-endpoint = <&vop_out_lvds>; 571 }; 572 }; 573 }; 574 }; 575 576 i2c0: i2c0@20072000 { 577 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 578 reg = <0x20072000 0x1000>; 579 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 clock-names = "i2c"; 583 clocks = <&cru PCLK_I2C0>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2c0_xfer>; 586 }; 587 588 i2c1: i2c1@20056000 { 589 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 590 reg = <0x20056000 0x1000>; 591 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 clock-names = "i2c"; 595 clocks = <&cru PCLK_I2C1>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&i2c1_xfer>; 598 }; 599 600 i2c2: i2c2@2005a000 { 601 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 602 reg = <0x2005a000 0x1000>; 603 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 clock-names = "i2c"; 607 clocks = <&cru PCLK_I2C2>; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&i2c2_xfer>; 610 }; 611 612 i2c3: i2c3@2005e000 { 613 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 614 reg = <0x2005e000 0x1000>; 615 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 clock-names = "i2c"; 619 clocks = <&cru PCLK_I2C3>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&i2c3_xfer>; 622 }; 623 624 spi0: spi@20074000 { 625 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 626 reg = <0x20074000 0x1000>; 627 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 630 clock-names = "spiclk", "apb_pclk"; 631 dmas = <&pdma 8>, <&pdma 9>; 632 dma-names = "tx", "rx"; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 status = "disabled"; 636 }; 637 638 grf: syscon@20008000 { 639 compatible = "rockchip,rk3128-grf", "syscon"; 640 reg = <0x20008000 0x1000>; 641 }; 642 643 pinctrl: pinctrl@20008000 { 644 compatible = "rockchip,rk3128-pinctrl"; 645 reg = <0x20008000 0xA8>, 646 <0x200080A8 0x4C>, 647 <0x20008118 0x20>, 648 <0x20008100 0x04>; 649 reg-names = "base", "mux", "pull", "drv"; 650 rockchip,grf = <&grf>; 651 #address-cells = <1>; 652 #size-cells = <1>; 653 ranges; 654 655 gpio0: gpio0@2007c000 { 656 compatible = "rockchip,gpio-bank"; 657 reg = <0x2007c000 0x100>; 658 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&cru PCLK_GPIO0>; 660 gpio-controller; 661 #gpio-cells = <2>; 662 interrupt-controller; 663 #interrupt-cells = <2>; 664 }; 665 666 gpio1: gpio1@20080000 { 667 compatible = "rockchip,gpio-bank"; 668 reg = <0x20080000 0x100>; 669 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&cru PCLK_GPIO1>; 671 gpio-controller; 672 #gpio-cells = <2>; 673 interrupt-controller; 674 #interrupt-cells = <2>; 675 }; 676 677 gpio2: gpio2@20084000 { 678 compatible = "rockchip,gpio-bank"; 679 reg = <0x20084000 0x100>; 680 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&cru PCLK_GPIO2>; 682 gpio-controller; 683 #gpio-cells = <2>; 684 interrupt-controller; 685 #interrupt-cells = <2>; 686 }; 687 688 gpio3: gpio2@20088000 { 689 compatible = "rockchip,gpio-bank"; 690 reg = <0x20088000 0x100>; 691 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&cru PCLK_GPIO3>; 693 gpio-controller; 694 #gpio-cells = <2>; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 699 pcfg_pull_default: pcfg_pull_default { 700 bias-pull-pin-default; 701 }; 702 703 pcfg_pull_none: pcfg-pull-none { 704 bias-disable; 705 }; 706 707 emmc { 708 emmc_clk: emmc-clk { 709 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 710 }; 711 712 emmc_cmd: emmc-cmd { 713 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 714 }; 715 716 emmc_cmd1: emmc-cmd1 { 717 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 718 }; 719 720 emmc_pwr: emmc-pwr { 721 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 722 }; 723 724 emmc_bus1: emmc-bus1 { 725 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 726 }; 727 728 emmc_bus4: emmc-bus4 { 729 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 730 <1 RK_PD1 2 &pcfg_pull_default>, 731 <1 RK_PD2 2 &pcfg_pull_default>, 732 <1 RK_PD3 2 &pcfg_pull_default>; 733 }; 734 735 emmc_bus8: emmc-bus8 { 736 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 737 <1 RK_PD1 2 &pcfg_pull_default>, 738 <1 RK_PD2 2 &pcfg_pull_default>, 739 <1 RK_PD3 2 &pcfg_pull_default>, 740 <1 RK_PD4 2 &pcfg_pull_default>, 741 <1 RK_PD5 2 &pcfg_pull_default>, 742 <1 RK_PD6 2 &pcfg_pull_default>, 743 <1 RK_PD7 2 &pcfg_pull_default>; 744 }; 745 }; 746 747 i2c0 { 748 i2c0_xfer: i2c0-xfer { 749 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 750 <0 RK_PA1 1 &pcfg_pull_none>; 751 }; 752 }; 753 754 i2c1 { 755 i2c1_xfer: i2c1-xfer { 756 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 757 <0 RK_PA3 1 &pcfg_pull_none>; 758 }; 759 }; 760 761 i2c2 { 762 i2c2_xfer: i2c2-xfer { 763 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 764 <2 RK_PC5 3 &pcfg_pull_none>; 765 }; 766 }; 767 768 i2c3 { 769 i2c3_xfer: i2c3-xfer { 770 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 771 <0 RK_PA7 1 &pcfg_pull_none>; 772 }; 773 }; 774 775 uart0 { 776 uart0_xfer: uart0-xfer { 777 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 778 <2 RK_PD3 2 &pcfg_pull_none>; 779 }; 780 781 uart0_cts: uart0-cts { 782 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 783 }; 784 785 uart0_rts: uart0-rts { 786 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 787 }; 788 }; 789 790 uart1 { 791 uart1_xfer: uart1-xfer { 792 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 793 <1 RK_PB2 2 &pcfg_pull_default>; 794 }; 795 796 uart1_cts: uart1-cts { 797 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 798 }; 799 800 uart1_rts: uart1-rts { 801 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 802 }; 803 }; 804 805 uart2 { 806 uart2_xfer: uart2-xfer { 807 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 808 <1 RK_PC3 2 &pcfg_pull_none>; 809 }; 810 811 uart2_cts: uart2-cts { 812 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 813 }; 814 815 uart2_rts: uart2-rts { 816 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 817 }; 818 }; 819 820 sdmmc { 821 sdmmc_clk: sdmmc-clk { 822 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 823 }; 824 825 sdmmc_cmd: sdmmc-cmd { 826 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 827 }; 828 829 sdmmc_wp: sdmmc-wp { 830 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 831 }; 832 833 sdmmc_pwren: sdmmc-pwren { 834 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 835 }; 836 837 sdmmc_bus4: sdmmc-bus4 { 838 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 839 <1 RK_PC3 1 &pcfg_pull_default>, 840 <1 RK_PC4 1 &pcfg_pull_default>, 841 <1 RK_PC5 1 &pcfg_pull_default>; 842 }; 843 }; 844 845 sdio { 846 sdio_clk: sdio-clk { 847 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 848 }; 849 850 sdio_cmd: sdio-cmd { 851 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 852 }; 853 854 sdio_pwren: sdio-pwren { 855 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 856 }; 857 858 sdio_bus4: sdio-bus4 { 859 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 860 <1 RK_PA2 2 &pcfg_pull_default>, 861 <1 RK_PA4 2 &pcfg_pull_default>, 862 <1 RK_PA5 2 &pcfg_pull_default>; 863 }; 864 }; 865 866 hdmi { 867 hdmii2c_xfer: hdmii2c-xfer { 868 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 869 <0 RK_PA7 2 &pcfg_pull_none>; 870 }; 871 }; 872 873 i2s { 874 i2s_bus: i2s-bus { 875 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 876 <0 RK_PB1 1 &pcfg_pull_none>, 877 <0 RK_PB3 1 &pcfg_pull_none>, 878 <0 RK_PB4 1 &pcfg_pull_none>, 879 <0 RK_PB5 1 &pcfg_pull_none>, 880 <0 RK_PB6 1 &pcfg_pull_none>; 881 }; 882 883 i2s1_bus: i2s1-bus { 884 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 885 <1 RK_PA1 1 &pcfg_pull_none>, 886 <1 RK_PA2 1 &pcfg_pull_none>, 887 <1 RK_PA3 1 &pcfg_pull_none>, 888 <1 RK_PA4 1 &pcfg_pull_none>, 889 <1 RK_PA5 1 &pcfg_pull_none>; 890 }; 891 }; 892 893 pwm0 { 894 pwm0_pin: pwm0-pin { 895 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 896 }; 897 }; 898 899 pwm1 { 900 pwm1_pin: pwm1-pin { 901 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 902 }; 903 }; 904 905 pwm2 { 906 pwm2_pin: pwm2-pin { 907 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; 908 }; 909 }; 910 911 pwm3 { 912 pwm3_pin: pwm3-pin { 913 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 914 }; 915 }; 916 917 gmac { 918 rgmii_pins: rgmii-pins { 919 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 920 <2 RK_PB1 3 &pcfg_pull_default>, 921 <2 RK_PB3 3 &pcfg_pull_default>, 922 <2 RK_PB4 3 &pcfg_pull_default>, 923 <2 RK_PB5 3 &pcfg_pull_default>, 924 <2 RK_PB6 3 &pcfg_pull_default>, 925 <2 RK_PC0 3 &pcfg_pull_default>, 926 <2 RK_PC1 3 &pcfg_pull_default>, 927 <2 RK_PC2 3 &pcfg_pull_default>, 928 <2 RK_PC3 3 &pcfg_pull_default>, 929 <2 RK_PD1 3 &pcfg_pull_default>, 930 <2 RK_PC4 4 &pcfg_pull_default>, 931 <2 RK_PC5 4 &pcfg_pull_default>, 932 <2 RK_PC6 4 &pcfg_pull_default>, 933 <2 RK_PC7 4 &pcfg_pull_default>; 934 }; 935 936 rmii_pins: rmii-pins { 937 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 938 <2 RK_PB4 3 &pcfg_pull_default>, 939 <2 RK_PB5 3 &pcfg_pull_default>, 940 <2 RK_PB6 3 &pcfg_pull_default>, 941 <2 RK_PB7 3 &pcfg_pull_default>, 942 <2 RK_PC0 3 &pcfg_pull_default>, 943 <2 RK_PC1 3 &pcfg_pull_default>, 944 <2 RK_PC3 3 &pcfg_pull_default>, 945 <2 RK_PC4 3 &pcfg_pull_default>, 946 <2 RK_PD1 3 &pcfg_pull_default>; 947 }; 948 }; 949 950 spdif { 951 spdif_tx: spdif-tx { 952 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 953 }; 954 }; 955 956 spi { 957 spi0_clk: spi0-clk { 958 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 959 }; 960 961 spi0_cs0: spi0-cs0 { 962 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 963 }; 964 965 spi0_tx: spi0-tx { 966 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 967 }; 968 969 spi0_rx: spi0-rx { 970 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 971 }; 972 973 spi0_cs1: spi0-cs1 { 974 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 975 }; 976 977 spi1_clk: spi1-clk { 978 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 979 }; 980 981 spi1_cs0: spi1-cs0 { 982 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 983 }; 984 985 spi1_tx: spi1-tx { 986 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 987 }; 988 989 spi1_rx: spi1-rx { 990 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 991 }; 992 993 spi1_cs1: spi1-cs1 { 994 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 995 }; 996 997 spi2_clk: spi2-clk { 998 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 999 }; 1000 1001 spi2_cs0: spi2-cs0 { 1002 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1003 }; 1004 1005 spi2_tx: spi2-tx { 1006 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1007 }; 1008 1009 spi2_rx: spi2-rx { 1010 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1011 }; 1012 }; 1013 }; 1014}; 1015
