1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include <dt-bindings/media/rockchip_mipi_dsi.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3128"; 17 rockchip,sram = <&sram>; 18 interrupt-parent = <&gic>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 spi0 = &spi0; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 }; 38 39 memory { 40 device_type = "memory"; 41 reg = <0x60000000 0x40000000>; 42 }; 43 44 arm-pmu { 45 compatible = "arm,cortex-a7-pmu"; 46 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 enable-method = "rockchip,rk3128-smp"; 56 57 cpu0:cpu@0x000 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0x000>; 61 operating-points = < 62 /* KHz uV */ 63 816000 1000000 64 >; 65 #cooling-cells = <2>; /* min followed by max */ 66 clock-latency = <40000>; 67 clocks = <&cru ARMCLK>; 68 }; 69 70 cpu1:cpu@0x001 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a7"; 73 reg = <0x001>; 74 }; 75 76 cpu2:cpu@0x002 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <0x002>; 80 }; 81 82 cpu3:cpu@0x003 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a7"; 85 reg = <0x003>; 86 }; 87 }; 88 89 cpu_axi_bus: cpu_axi_bus { 90 compatible = "rockchip,cpu_axi_bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges; 94 95 qos { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 100 crypto { 101 reg = <0x10128080 0x20>; 102 }; 103 104 core { 105 reg = <0x1012a000 0x20>; 106 }; 107 108 peri { 109 reg = <0x1012c000 0x20>; 110 }; 111 112 gpu { 113 reg = <0x1012d000 0x20>; 114 }; 115 116 vpu { 117 reg = <0x1012e000 0x20>; 118 }; 119 120 rga { 121 reg = <0x1012f000 0x20>; 122 }; 123 ebc { 124 reg = <0x1012f080 0x20>; 125 }; 126 127 iep { 128 reg = <0x1012f100 0x20>; 129 }; 130 131 lcdc { 132 reg = <0x1012f180 0x20>; 133 rockchip,priority = <3 3>; 134 }; 135 136 vip { 137 reg = <0x1012f200 0x20>; 138 rockchip,priority = <3 3>; 139 }; 140 }; 141 142 msch { 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges; 146 147 msch@10128000 { 148 reg = <0x10128000 0x20>; 149 rockchip,read-latency = <0x3f>; 150 }; 151 }; 152 }; 153 154 psci { 155 compatible = "arm,psci"; 156 method = "smc"; 157 cpu_suspend = <0x84000001>; 158 cpu_off = <0x84000002>; 159 cpu_on = <0x84000003>; 160 migrate = <0x84000005>; 161 }; 162 163 amba { 164 compatible = "arm,amba-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 interrupt-parent = <&gic>; 168 ranges; 169 170 pdma: pdma@20078000 { 171 compatible = "arm,pl330", "arm,primecell"; 172 reg = <0x20078000 0x4000>; 173 arm,pl330-broken-no-flushp;//2 174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 clocks = <&cru ACLK_DMAC2>; 178 clock-names = "apb_pclk"; 179 }; 180 }; 181 182 xin24m: xin24m { 183 compatible = "fixed-clock"; 184 clock-frequency = <24000000>; 185 clock-output-names = "xin24m"; 186 #clock-cells = <0>; 187 }; 188 189 xin12m: xin12m { 190 compatible = "fixed-clock"; 191 clocks = <&xin24m>; 192 clock-frequency = <12000000>; 193 clock-output-names = "xin12m"; 194 #clock-cells = <0>; 195 }; 196 197 198 timer { 199 compatible = "arm,armv7-timer"; 200 arm,cpu-registers-not-fw-configured; 201 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 202 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 203 clock-frequency = <24000000>; 204 }; 205 206 timer@20044000 { 207 compatible = "arm,armv7-timer"; 208 reg = <0x20044000 0xb8>; 209 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 210 rockchip,broadcast = <1>; 211 }; 212 213 watchdog: wdt@2004c000 { 214 compatible = "rockchip,watch dog"; 215 reg = <0x2004c000 0x100>; 216 clock-names = "pclk_wdt"; 217 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 218 rockchip,irq = <1>; 219 rockchip,timeout = <60>; 220 rockchip,atboot = <1>; 221 rockchip,debug = <0>; 222 }; 223 224 reset: reset@20000110 { 225 compatible = "rockchip,reset"; 226 reg = <0x20000110 0x24>; 227 #reset-cells = <1>; 228 }; 229 230 nandc: nandc@10500000 { 231 compatible = "rockchip,rk-nandc"; 232 reg = <0x10500000 0x4000>; 233 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; 236 nandc_id = <0>; 237 clocks = <&cru SCLK_NANDC>, 238 <&cru HCLK_NANDC>, 239 <&cru SRST_NANDC>; 240 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; 241 }; 242 243 dmc: dmc@20004000 { 244 u-boot,dm-pre-reloc; 245 compatible = "rockchip,rk3128-dmc", "syscon"; 246 reg = <0x0 0x20004000 0x0 0x1000>; 247 }; 248 249 cru: clock-controller@20000000 { 250 u-boot,dm-pre-reloc; 251 compatible = "rockchip,rk3128-cru"; 252 reg = <0x20000000 0x1000>; 253 rockchip,grf = <&grf>; 254 #clock-cells = <1>; 255 #reset-cells = <1>; 256 assigned-clocks = <&cru PLL_GPLL>; 257 assigned-clock-rates = <594000000>; 258 }; 259 260 uart0: serial0@20060000 { 261 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 262 reg = <0x20060000 0x100>; 263 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 264 reg-shift = <2>; 265 reg-io-width = <4>; 266 clock-frequency = <24000000>; 267 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 268 clock-names = "baudclk", "apb_pclk"; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 271 dmas = <&pdma 2>, <&pdma 3>; 272 #dma-cells = <2>; 273 }; 274 275 uart1: serial1@20064000 { 276 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 277 reg = <0x20064000 0x100>; 278 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 279 reg-shift = <2>; 280 reg-io-width = <4>; 281 clock-frequency = <24000000>; 282 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 283 clock-names = "baudclk", "apb_pclk"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&uart1_xfer>; 286 dmas = <&pdma 4>, <&pdma 5>; 287 #dma-cells = <2>; 288 }; 289 290 uart2: serial2@20068000 { 291 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 292 reg = <0x20068000 0x100>; 293 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 294 reg-shift = <2>; 295 reg-io-width = <4>; 296 clock-frequency = <24000000>; 297 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 298 clock-names = "baudclk", "apb_pclk"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&uart2_xfer>; 301 dmas = <&pdma 6>, <&pdma 7>; 302 #dma-cells = <2>; 303 }; 304 305 saradc: saradc@2006c000 { 306 compatible = "rockchip,saradc"; 307 reg = <0x2006c000 0x100>; 308 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 309 #io-channel-cells = <1>; 310 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 311 clock-names = "saradc", "apb_pclk"; 312 resets = <&cru SRST_SARADC>; 313 reset-names = "saradc-apb"; 314 status = "disabled"; 315 }; 316 317 pwm0: pwm0@20050000 { 318 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 319 reg = <0x20050000 0x10>; 320 #pwm-cells = <2>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&pwm0_pin>; 323 clocks = <&cru PCLK_PWM>; 324 clock-names = "pwm"; 325 }; 326 327 pwm1: pwm1@20050010 { 328 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 329 reg = <0x20050010 0x10>; 330 #pwm-cells = <2>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pwm1_pin>; 333 clocks = <&cru PCLK_PWM>; 334 clock-names = "pwm"; 335 }; 336 337 pwm2: pwm2@20050020 { 338 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 339 reg = <0x20050020 0x10>; 340 #pwm-cells = <2>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pwm2_pin>; 343 clocks = <&cru PCLK_PWM>; 344 clock-names = "pwm"; 345 }; 346 347 pwm3: pwm3@20050030 { 348 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 349 reg = <0x20050030 0x10>; 350 #pwm-cells = <2>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pwm3_pin>; 353 clocks = <&cru PCLK_PWM>; 354 clock-names = "pwm"; 355 }; 356 357 sram: sram@10080400 { 358 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 359 reg = <0x10080400 0x1C00>; 360 map-exec; 361 map-cacheable; 362 }; 363 364 pmu: syscon@100a0000 { 365 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 366 reg = <0x100a0000 0x1000>; 367 #address-cells = <1>; 368 #size-cells = <1>; 369 }; 370 371 vop: vop@1010e000 { 372 u-boot,dm-pre-reloc; 373 compatible = "rockchip,rk3126-vop"; 374 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>; 375 reg-names = "regs", "gamma_lut"; 376 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cru ACLK_VIO0>, <&cru DCLK_LCDC>, <&cru HCLK_LCDC>; 378 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 379 status = "disabled"; 380 381 vop_out: port { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 385 vop_out_lvds: endpoint@1 { 386 reg = <1>; 387 remote-endpoint = <&lvds_in_vop>; 388 }; 389 390 vop_out_dsi: endpoint@2 { 391 reg = <1>; 392 remote-endpoint = <&dsi_in_vop>; 393 }; 394 }; 395 }; 396 397 dsi: dsi@10110000 { 398 compatible = "rockchip,rk312x-mipi-dsi"; 399 reg = <0x10110000 0x4000>; 400 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&mipi_dphy>; 402 clock-names = "pclk", "h2p", "hs_clk"; 403 resets = <&cru SRST_VIO_MIPI_DSI>; 404 reset-names = "apb"; 405 phys = <&mipi_dphy>; 406 phy-names = "mipi_dphy"; 407 rockchip,grf = <&grf>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 412 ports { 413 port { 414 dsi_in_vop: endpoint { 415 remote-endpoint = <&vop_out_dsi>; 416 }; 417 }; 418 }; 419 }; 420 421 display_subsystem: display-subsystem { 422 u-boot,dm-pre-reloc; 423 compatible = "rockchip,display-subsystem"; 424 ports = <&vop_out>; 425 426 route { 427 route_lvds: route-lvds { 428 logo,uboot = "logo.bmp"; 429 logo,kernel = "logo_kernel.bmp"; 430 logo,mode = "fullscreen"; 431 charge_logo,mode = "center"; 432 connect = <&vop_out_lvds>; 433 }; 434 435 route_dsi: route-dsi { 436 logo,uboot = "logo.bmp"; 437 logo,kernel = "logo_kernel.bmp"; 438 logo,mode = "fullscreen"; 439 charge_logo,mode = "center"; 440 connect = <&vop_out_dsi>; 441 }; 442 }; 443 }; 444 445 gic: interrupt-controller@10139000 { 446 compatible = "arm,gic-400"; 447 interrupt-controller; 448 #interrupt-cells = <3>; 449 #address-cells = <0>; 450 reg = <0x10139000 0x1000>, 451 <0x1013a000 0x1000>, 452 <0x1013c000 0x2000>, 453 <0x1013e000 0x2000>; 454 interrupts = <GIC_PPI 9 0xf04>; 455 }; 456 457 u2phy: usb2-phy { 458 compatible = "rockchip,rk3128-usb2phy"; 459 reg = <0x017c 0x0c>; 460 rockchip,grf = <&grf>; 461 clocks = <&cru SCLK_OTGPHY0>; 462 clock-names = "phyclk"; 463 #clock-cells = <0>; 464 clock-output-names = "usb480m_phy"; 465 #phy-cells = <1>; 466 status = "disabled"; 467 468 u2phy_otg: otg-port { 469 #phy-cells = <0>; 470 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 473 interrupt-names = "otg-bvalid", "otg-id", 474 "linestate"; 475 status = "disabled"; 476 }; 477 478 u2phy_host: host-port { 479 #phy-cells = <0>; 480 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "linestate"; 482 status = "disabled"; 483 }; 484 }; 485 486 usb_otg: usb@10180000 { 487 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", 488 "snps,dwc2"; 489 reg = <0x10180000 0x40000>; 490 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 491 dr_mode = "otg"; 492 g-use-dma; 493 hnp-srp-disable; 494 phys = <&u2phy 0>; 495 phy-names = "usb"; 496 status = "disabled"; 497 }; 498 499 usb_host_ehci: usb@101c0000 { 500 compatible = "generic-ehci"; 501 reg = <0x101c0000 0x20000>; 502 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 503 phys = <&u2phy 1>; 504 phy-names = "usb"; 505 status = "disabled"; 506 }; 507 508 usb_host_ohci: usb@101e0000 { 509 compatible = "generic-ohci"; 510 reg = <0x101e0000 0x20000>; 511 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 512 phys = <&u2phy 1>; 513 phy-names = "usb"; 514 status = "disabled"; 515 }; 516 517 sdmmc: dwmmc@10214000 { 518 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 519 reg = <0x10214000 0x4000>; 520 max-frequency = <150000000>; 521 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 523 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 524 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 525 fifo-depth = <0x100>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 528 bus-width = <4>; 529 status = "disabled"; 530 }; 531 532 emmc: dwmmc@1021c000 { 533 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 534 reg = <0x1021c000 0x4000>; 535 max-frequency = <150000000>; 536 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 538 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 539 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 540 bus-width = <8>; 541 default-sample-phase = <158>; 542 num-slots = <1>; 543 fifo-depth = <0x100>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 546 resets = <&cru SRST_EMMC>; 547 reset-names = "reset"; 548 status = "disabled"; 549 }; 550 551 mipi_dphy: mipi-dphy@20038000 { 552 compatible = "rockchip,rk312x-mipi-dphy"; 553 reg = <0x20038000 0x4000>; 554 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, <&cru HCLK_VIO_H2P>; 555 clock-names = "ref", "pclk", "h2p"; 556 clock-output-names = "mipi_dphy_pll"; 557 #clock-cells = <0>; 558 resets = <&cru SRST_MIPIPHY_P>; 559 reset-names = "apb"; 560 #phy-cells = <0>; 561 status = "disabled"; 562 }; 563 564 lvds: lvds@20038000 { 565 u-boot,dm-pre-reloc; 566 compatible = "rockchip,rk3126-lvds"; 567 reg = <0x20038000 0x4000>, <0x10110000 0x100>; 568 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 569 rockchip,grf = <&grf>; 570 status = "disabled"; 571 572 ports { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 576 lvds_in: port@0 { 577 reg = <0>; 578 lvds_in_vop: endpoint { 579 remote-endpoint = <&vop_out_lvds>; 580 }; 581 }; 582 }; 583 }; 584 585 i2c0: i2c0@20072000 { 586 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 587 reg = <0x20072000 0x1000>; 588 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 clock-names = "i2c"; 592 clocks = <&cru PCLK_I2C0>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&i2c0_xfer>; 595 }; 596 597 i2c1: i2c1@20056000 { 598 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 599 reg = <0x20056000 0x1000>; 600 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 clock-names = "i2c"; 604 clocks = <&cru PCLK_I2C1>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&i2c1_xfer>; 607 }; 608 609 i2c2: i2c2@2005a000 { 610 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 611 reg = <0x2005a000 0x1000>; 612 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 clock-names = "i2c"; 616 clocks = <&cru PCLK_I2C2>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&i2c2_xfer>; 619 }; 620 621 i2c3: i2c3@2005e000 { 622 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 623 reg = <0x2005e000 0x1000>; 624 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 clock-names = "i2c"; 628 clocks = <&cru PCLK_I2C3>; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&i2c3_xfer>; 631 }; 632 633 spi0: spi@20074000 { 634 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 635 reg = <0x20074000 0x1000>; 636 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; 641 rockchip,spi-src-clk = <0>; 642 num-cs = <2>; 643 clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; 644 clock-names = "spi","pclk_spi0"; 645 dmas = <&pdma 8>, <&pdma 9>; 646 #dma-cells = <2>; 647 dma-names = "tx", "rx"; 648 }; 649 650 grf: syscon@20008000 { 651 u-boot,dm-pre-reloc; 652 compatible = "rockchip,rk3128-grf", "syscon"; 653 reg = <0x20008000 0x1000>; 654 }; 655 656 pinctrl: pinctrl@20008000 { 657 compatible = "rockchip,rk3128-pinctrl"; 658 reg = <0x20008000 0xA8>, 659 <0x200080A8 0x4C>, 660 <0x20008118 0x20>, 661 <0x20008100 0x04>; 662 reg-names = "base", "mux", "pull", "drv"; 663 rockchip,grf = <&grf>; 664 #address-cells = <1>; 665 #size-cells = <1>; 666 ranges; 667 668 gpio0: gpio0@2007c000 { 669 compatible = "rockchip,gpio-bank"; 670 reg = <0x2007c000 0x100>; 671 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&cru PCLK_GPIO0>; 673 gpio-controller; 674 #gpio-cells = <2>; 675 interrupt-controller; 676 #interrupt-cells = <2>; 677 }; 678 679 gpio1: gpio1@20080000 { 680 compatible = "rockchip,gpio-bank"; 681 reg = <0x20080000 0x100>; 682 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cru PCLK_GPIO1>; 684 gpio-controller; 685 #gpio-cells = <2>; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 }; 689 690 gpio2: gpio2@20084000 { 691 compatible = "rockchip,gpio-bank"; 692 reg = <0x20084000 0x100>; 693 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&cru PCLK_GPIO2>; 695 gpio-controller; 696 #gpio-cells = <2>; 697 interrupt-controller; 698 #interrupt-cells = <2>; 699 }; 700 701 gpio3: gpio2@20088000 { 702 compatible = "rockchip,gpio-bank"; 703 reg = <0x20088000 0x100>; 704 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&cru PCLK_GPIO3>; 706 gpio-controller; 707 #gpio-cells = <2>; 708 interrupt-controller; 709 #interrupt-cells = <2>; 710 }; 711 712 pcfg_pull_up: pcfg-pull-up { 713 bias-pull-up; 714 }; 715 716 pcfg_pull_down: pcfg-pull-down { 717 bias-pull-down; 718 }; 719 720 pcfg_pull_none: pcfg-pull-none { 721 bias-disable; 722 }; 723 724 emmc { 725 /* 726 * We run eMMC at max speed; bump up drive strength. 727 * We also have external pulls, so disable the internal ones. 728 */ 729 730 emmc_clk: emmc-clk { 731 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; 732 }; 733 734 emmc_cmd: emmc-cmd { 735 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 736 }; 737 738 emmc_pwren: emmc-pwren { 739 rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; 740 }; 741 742 emmc_bus8: emmc-bus8 { 743 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 744 <1 25 RK_FUNC_2 &pcfg_pull_none>, 745 <1 26 RK_FUNC_2 &pcfg_pull_none>, 746 <1 27 RK_FUNC_2 &pcfg_pull_none>, 747 <1 28 RK_FUNC_2 &pcfg_pull_none>, 748 <1 29 RK_FUNC_2 &pcfg_pull_none>, 749 <1 30 RK_FUNC_2 &pcfg_pull_none>, 750 <1 31 RK_FUNC_2 &pcfg_pull_none>; 751 }; 752 }; 753 754 nandc{ 755 nandc_ale:nandc-ale { 756 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 757 }; 758 759 nandc_cle:nandc-cle { 760 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 761 }; 762 763 nandc_wrn:nandc-wrn { 764 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 765 }; 766 767 nandc_rdn:nandc-rdn { 768 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 769 }; 770 771 nandc_rdy:nandc-rdy { 772 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 773 }; 774 775 nandc_cs0:nandc-cs0 { 776 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 777 }; 778 779 nandc_data: nandc-data { 780 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 781 }; 782 }; 783 784 785 uart0 { 786 uart0_xfer: uart0-xfer { 787 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, 788 <0 17 RK_FUNC_1 &pcfg_pull_none>; 789 }; 790 791 uart0_cts: uart0-cts { 792 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 793 }; 794 795 uart0_rts: uart0-rts { 796 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; 797 }; 798 }; 799 800 uart1 { 801 uart1_xfer: uart1-xfer { 802 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, 803 <2 23 RK_FUNC_1 &pcfg_pull_none>; 804 }; 805 }; 806 807 uart2 { 808 uart2_xfer: uart2-xfer { 809 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, 810 <1 19 RK_FUNC_2 &pcfg_pull_none>; 811 }; 812 }; 813 814 sdmmc { 815 sdmmc_clk: sdmmc-clk { 816 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 817 }; 818 819 sdmmc_cmd: sdmmc-cmd { 820 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; 821 }; 822 823 sdmmc_wp: sdmmc-wp { 824 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; 825 }; 826 827 sdmmc_pwren: sdmmc-pwren { 828 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; 829 }; 830 831 sdmmc_bus4: sdmmc-bus4 { 832 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, 833 <1 RK_PC3 1 &pcfg_pull_up>, 834 <1 RK_PC4 1 &pcfg_pull_up>, 835 <1 RK_PC5 1 &pcfg_pull_up>; 836 }; 837 }; 838 839 pwm0 { 840 pwm0_pin: pwm0-pin { 841 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 842 }; 843 }; 844 845 pwm1 { 846 pwm1_pin: pwm1-pin { 847 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; 848 }; 849 }; 850 851 pwm2 { 852 pwm2_pin: pwm2-pin { 853 rockchip,pins = <0 1 2 &pcfg_pull_none>; 854 }; 855 }; 856 857 pwm3 { 858 pwm3_pin: pwm3-pin { 859 rockchip,pins = <0 27 1 &pcfg_pull_none>; 860 }; 861 }; 862 863 i2c0 { 864 i2c0_xfer: i2c0-xfer { 865 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, 866 <0 1 RK_FUNC_1 &pcfg_pull_none>; 867 }; 868 }; 869 870 i2c1 { 871 i2c1_xfer: i2c1-xfer { 872 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 873 <0 3 RK_FUNC_1 &pcfg_pull_none>; 874 }; 875 }; 876 877 i2c2 { 878 i2c2_xfer: i2c2-xfer { 879 rockchip,pins = <2 20 3 &pcfg_pull_none>, 880 <2 21 3 &pcfg_pull_none>; 881 }; 882 }; 883 884 i2c3 { 885 i2c3_xfer: i2c3-xfer { 886 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 887 <0 7 RK_FUNC_1 &pcfg_pull_none>; 888 }; 889 }; 890 891 spi0 { 892 spi0_txd_mux0:spi0-txd-mux0 { 893 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 894 }; 895 896 spi0_rxd_mux0:spi0-rxd-mux0 { 897 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 898 }; 899 900 spi0_clk_mux0:spi0-clk-mux0 { 901 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 902 }; 903 904 spi0_cs0_mux0:spi0-cs0-mux0 { 905 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 906 }; 907 908 spi0_cs1_mux0:spi0-cs1-mux0 { 909 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 910 }; 911 }; 912 913 }; 914}; 915
