1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include <dt-bindings/media/rockchip_mipi_dsi.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3128"; 17 rockchip,sram = <&sram>; 18 interrupt-parent = <&gic>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 spi0 = &spi0; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 }; 38 39 memory { 40 device_type = "memory"; 41 reg = <0x60000000 0x40000000>; 42 }; 43 44 arm-pmu { 45 compatible = "arm,cortex-a7-pmu"; 46 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 enable-method = "rockchip,rk3128-smp"; 56 57 cpu0:cpu@0x000 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a7"; 60 reg = <0x000>; 61 operating-points = < 62 /* KHz uV */ 63 816000 1000000 64 >; 65 #cooling-cells = <2>; /* min followed by max */ 66 clock-latency = <40000>; 67 clocks = <&cru ARMCLK>; 68 }; 69 70 cpu1:cpu@0x001 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a7"; 73 reg = <0x001>; 74 }; 75 76 cpu2:cpu@0x002 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <0x002>; 80 }; 81 82 cpu3:cpu@0x003 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a7"; 85 reg = <0x003>; 86 }; 87 }; 88 89 cpu_axi_bus: cpu_axi_bus { 90 compatible = "rockchip,cpu_axi_bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges; 94 95 qos { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 100 crypto { 101 reg = <0x10128080 0x20>; 102 }; 103 104 core { 105 reg = <0x1012a000 0x20>; 106 }; 107 108 peri { 109 reg = <0x1012c000 0x20>; 110 }; 111 112 gpu { 113 reg = <0x1012d000 0x20>; 114 }; 115 116 vpu { 117 reg = <0x1012e000 0x20>; 118 }; 119 120 rga { 121 reg = <0x1012f000 0x20>; 122 }; 123 ebc { 124 reg = <0x1012f080 0x20>; 125 }; 126 127 iep { 128 reg = <0x1012f100 0x20>; 129 }; 130 131 lcdc { 132 reg = <0x1012f180 0x20>; 133 rockchip,priority = <3 3>; 134 }; 135 136 vip { 137 reg = <0x1012f200 0x20>; 138 rockchip,priority = <3 3>; 139 }; 140 }; 141 142 msch { 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges; 146 147 msch@10128000 { 148 reg = <0x10128000 0x20>; 149 rockchip,read-latency = <0x3f>; 150 }; 151 }; 152 }; 153 154 psci { 155 compatible = "arm,psci"; 156 method = "smc"; 157 cpu_suspend = <0x84000001>; 158 cpu_off = <0x84000002>; 159 cpu_on = <0x84000003>; 160 migrate = <0x84000005>; 161 }; 162 163 amba { 164 compatible = "arm,amba-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 interrupt-parent = <&gic>; 168 ranges; 169 170 pdma: pdma@20078000 { 171 compatible = "arm,pl330", "arm,primecell"; 172 reg = <0x20078000 0x4000>; 173 arm,pl330-broken-no-flushp;//2 174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 clocks = <&cru ACLK_DMAC>; 178 clock-names = "apb_pclk"; 179 }; 180 }; 181 182 xin24m: xin24m { 183 compatible = "fixed-clock"; 184 clock-frequency = <24000000>; 185 clock-output-names = "xin24m"; 186 #clock-cells = <0>; 187 }; 188 189 xin12m: xin12m { 190 compatible = "fixed-clock"; 191 clocks = <&xin24m>; 192 clock-frequency = <12000000>; 193 clock-output-names = "xin12m"; 194 #clock-cells = <0>; 195 }; 196 197 198 timer { 199 compatible = "arm,armv7-timer"; 200 arm,cpu-registers-not-fw-configured; 201 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 202 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 203 clock-frequency = <24000000>; 204 }; 205 206 timer@20044000 { 207 compatible = "arm,armv7-timer"; 208 reg = <0x20044000 0xb8>; 209 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 210 rockchip,broadcast = <1>; 211 }; 212 213 watchdog: wdt@2004c000 { 214 compatible = "rockchip,watch dog"; 215 reg = <0x2004c000 0x100>; 216 clock-names = "pclk_wdt"; 217 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 218 rockchip,irq = <1>; 219 rockchip,timeout = <60>; 220 rockchip,atboot = <1>; 221 rockchip,debug = <0>; 222 }; 223 224 reset: reset@20000110 { 225 compatible = "rockchip,reset"; 226 reg = <0x20000110 0x24>; 227 #reset-cells = <1>; 228 }; 229 nandc: nandc@10500000 { 230 compatible = "rockchip,rk-nandc"; 231 reg = <0x10500000 0x4000>; 232 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 233 nandc_id = <0>; 234 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 235 clock-names = "clk_nandc", "hclk_nandc"; 236 status = "disabled"; 237 }; 238 239 dmc: dmc@20004000 { 240 compatible = "rockchip,rk3128-dmc", "syscon"; 241 reg = <0x0 0x20004000 0x0 0x1000>; 242 }; 243 244 cru: clock-controller@20000000 { 245 compatible = "rockchip,rk3128-cru"; 246 reg = <0x20000000 0x1000>; 247 rockchip,grf = <&grf>; 248 #clock-cells = <1>; 249 #reset-cells = <1>; 250 assigned-clocks = <&cru PLL_GPLL>; 251 assigned-clock-rates = <594000000>; 252 }; 253 254 uart0: serial0@20060000 { 255 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 256 reg = <0x20060000 0x100>; 257 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 258 reg-shift = <2>; 259 reg-io-width = <4>; 260 clock-frequency = <24000000>; 261 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 262 clock-names = "baudclk", "apb_pclk"; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 265 dmas = <&pdma 2>, <&pdma 3>; 266 #dma-cells = <2>; 267 }; 268 269 uart1: serial1@20064000 { 270 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 271 reg = <0x20064000 0x100>; 272 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 273 reg-shift = <2>; 274 reg-io-width = <4>; 275 clock-frequency = <24000000>; 276 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 277 clock-names = "baudclk", "apb_pclk"; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&uart1_xfer>; 280 dmas = <&pdma 4>, <&pdma 5>; 281 #dma-cells = <2>; 282 }; 283 284 uart2: serial2@20068000 { 285 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 286 reg = <0x20068000 0x100>; 287 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 288 reg-shift = <2>; 289 reg-io-width = <4>; 290 clock-frequency = <24000000>; 291 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 292 clock-names = "baudclk", "apb_pclk"; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&uart2_xfer>; 295 dmas = <&pdma 6>, <&pdma 7>; 296 #dma-cells = <2>; 297 }; 298 299 saradc: saradc@2006c000 { 300 compatible = "rockchip,saradc"; 301 reg = <0x2006c000 0x100>; 302 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 303 #io-channel-cells = <1>; 304 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 305 clock-names = "saradc", "apb_pclk"; 306 resets = <&cru SRST_SARADC>; 307 reset-names = "saradc-apb"; 308 status = "disabled"; 309 }; 310 311 pwm0: pwm0@20050000 { 312 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 313 reg = <0x20050000 0x10>; 314 #pwm-cells = <3>; 315 pinctrl-names = "active"; 316 pinctrl-0 = <&pwm0_pin>; 317 clocks = <&cru PCLK_PWM>; 318 clock-names = "pwm"; 319 }; 320 321 pwm1: pwm1@20050010 { 322 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 323 reg = <0x20050010 0x10>; 324 #pwm-cells = <2>; 325 pinctrl-names = "active"; 326 pinctrl-0 = <&pwm1_pin>; 327 clocks = <&cru PCLK_PWM>; 328 clock-names = "pwm"; 329 }; 330 331 pwm2: pwm2@20050020 { 332 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 333 reg = <0x20050020 0x10>; 334 #pwm-cells = <2>; 335 pinctrl-names = "active"; 336 pinctrl-0 = <&pwm2_pin>; 337 clocks = <&cru PCLK_PWM>; 338 clock-names = "pwm"; 339 }; 340 341 pwm3: pwm3@20050030 { 342 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 343 reg = <0x20050030 0x10>; 344 #pwm-cells = <2>; 345 pinctrl-names = "active"; 346 pinctrl-0 = <&pwm3_pin>; 347 clocks = <&cru PCLK_PWM>; 348 clock-names = "pwm"; 349 }; 350 351 sram: sram@10080400 { 352 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 353 reg = <0x10080400 0x1C00>; 354 map-exec; 355 map-cacheable; 356 }; 357 358 pmu: syscon@100a0000 { 359 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 360 reg = <0x100a0000 0x1000>; 361 #address-cells = <1>; 362 #size-cells = <1>; 363 }; 364 365 vop: vop@1010e000 { 366 compatible = "rockchip,rk3126-vop"; 367 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>; 368 reg-names = "regs", "gamma_lut"; 369 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, <&cru HCLK_LCDC0>; 371 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 372 status = "disabled"; 373 374 vop_out: port { 375 #address-cells = <1>; 376 #size-cells = <0>; 377 378 vop_out_lvds: endpoint@0 { 379 reg = <0>; 380 remote-endpoint = <&lvds_in_vop>; 381 }; 382 383 vop_out_dsi: endpoint@1 { 384 reg = <1>; 385 remote-endpoint = <&dsi_in_vop>; 386 }; 387 388 vop_out_rgb: endpoint@2 { 389 reg = <2>; 390 remote-endpoint = <&rgb_in_vop>; 391 }; 392 }; 393 }; 394 395 dsi: dsi@10110000 { 396 compatible = "rockchip,rk3128-mipi-dsi"; 397 reg = <0x10110000 0x4000>; 398 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>; 400 clock-names = "pclk", "h2p", "hs_clk"; 401 resets = <&cru SRST_VIO_MIPI_DSI>; 402 reset-names = "apb"; 403 phys = <&video_phy>; 404 phy-names = "mipi_dphy"; 405 rockchip,grf = <&grf>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 status = "disabled"; 409 410 ports { 411 port { 412 dsi_in_vop: endpoint { 413 remote-endpoint = <&vop_out_dsi>; 414 }; 415 }; 416 }; 417 }; 418 419 display_subsystem: display-subsystem { 420 compatible = "rockchip,display-subsystem"; 421 ports = <&vop_out>; 422 423 route { 424 route_lvds: route-lvds { 425 logo,uboot = "logo.bmp"; 426 logo,kernel = "logo_kernel.bmp"; 427 logo,mode = "fullscreen"; 428 charge_logo,mode = "center"; 429 connect = <&vop_out_lvds>; 430 }; 431 432 route_dsi: route-dsi { 433 logo,uboot = "logo.bmp"; 434 logo,kernel = "logo_kernel.bmp"; 435 logo,mode = "fullscreen"; 436 charge_logo,mode = "center"; 437 connect = <&vop_out_dsi>; 438 }; 439 }; 440 }; 441 442 gic: interrupt-controller@10139000 { 443 compatible = "arm,gic-400"; 444 interrupt-controller; 445 #interrupt-cells = <3>; 446 #address-cells = <0>; 447 reg = <0x10139000 0x1000>, 448 <0x1013a000 0x1000>, 449 <0x1013c000 0x2000>, 450 <0x1013e000 0x2000>; 451 interrupts = <GIC_PPI 9 0xf04>; 452 }; 453 454 u2phy: usb2-phy { 455 compatible = "rockchip,rk3128-usb2phy"; 456 reg = <0x017c 0x0c>; 457 rockchip,grf = <&grf>; 458 clocks = <&cru SCLK_OTGPHY0>; 459 clock-names = "phyclk"; 460 #clock-cells = <0>; 461 clock-output-names = "usb480m_phy"; 462 #phy-cells = <1>; 463 status = "disabled"; 464 465 u2phy_otg: otg-port { 466 #phy-cells = <0>; 467 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "otg-bvalid", "otg-id", 471 "linestate"; 472 status = "disabled"; 473 }; 474 475 u2phy_host: host-port { 476 #phy-cells = <0>; 477 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 478 interrupt-names = "linestate"; 479 status = "disabled"; 480 }; 481 }; 482 483 usb_otg: usb@10180000 { 484 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", 485 "snps,dwc2"; 486 reg = <0x10180000 0x40000>; 487 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 488 dr_mode = "otg"; 489 g-use-dma; 490 hnp-srp-disable; 491 phys = <&u2phy 0>; 492 phy-names = "usb"; 493 status = "disabled"; 494 }; 495 496 usb_host_ehci: usb@101c0000 { 497 compatible = "generic-ehci"; 498 reg = <0x101c0000 0x20000>; 499 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 500 phys = <&u2phy 1>; 501 phy-names = "usb"; 502 status = "disabled"; 503 }; 504 505 usb_host_ohci: usb@101e0000 { 506 compatible = "generic-ohci"; 507 reg = <0x101e0000 0x20000>; 508 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 509 phys = <&u2phy 1>; 510 phy-names = "usb"; 511 status = "disabled"; 512 }; 513 514 sdmmc: dwmmc@10214000 { 515 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 516 reg = <0x10214000 0x4000>; 517 max-frequency = <150000000>; 518 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 520 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 521 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 522 fifo-depth = <0x100>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 525 bus-width = <4>; 526 status = "disabled"; 527 }; 528 529 emmc: dwmmc@1021c000 { 530 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 531 reg = <0x1021c000 0x4000>; 532 max-frequency = <150000000>; 533 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 535 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 536 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 537 bus-width = <8>; 538 default-sample-phase = <158>; 539 num-slots = <1>; 540 fifo-depth = <0x100>; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 543 resets = <&cru SRST_EMMC>; 544 reset-names = "reset"; 545 status = "disabled"; 546 }; 547 548 video_phy: video-phy@20038000 { 549 compatible = "rockchip,rk3128-video-phy"; 550 reg = <0x20038000 0x4000>, <0x10110000 0x4000>; 551 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, 552 <&cru PCLK_MIPI>; 553 clock-names = "ref", "pclk_phy", "pclk_host"; 554 #clock-cells = <0>; 555 resets = <&cru SRST_MIPIPHY_P>; 556 reset-names = "rst"; 557 #phy-cells = <0>; 558 status = "disabled"; 559 }; 560 561 i2c0: i2c0@20072000 { 562 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 563 reg = <0x20072000 0x1000>; 564 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 clock-names = "i2c"; 568 clocks = <&cru PCLK_I2C0>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&i2c0_xfer>; 571 }; 572 573 i2c1: i2c1@20056000 { 574 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 575 reg = <0x20056000 0x1000>; 576 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 clock-names = "i2c"; 580 clocks = <&cru PCLK_I2C1>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&i2c1_xfer>; 583 }; 584 585 i2c2: i2c2@2005a000 { 586 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 587 reg = <0x2005a000 0x1000>; 588 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 clock-names = "i2c"; 592 clocks = <&cru PCLK_I2C2>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&i2c2_xfer>; 595 }; 596 597 i2c3: i2c3@2005e000 { 598 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 599 reg = <0x2005e000 0x1000>; 600 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 clock-names = "i2c"; 604 clocks = <&cru PCLK_I2C3>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&i2c3_xfer>; 607 }; 608 609 spi0: spi@20074000 { 610 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 611 reg = <0x20074000 0x1000>; 612 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 615 clock-names = "spiclk", "apb_pclk"; 616 dmas = <&pdma 8>, <&pdma 9>; 617 dma-names = "tx", "rx"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 grf: syscon@20008000 { 624 compatible = "rockchip,rk3128-grf", "syscon"; 625 reg = <0x20008000 0x1000>; 626 627 lvds: lvds { 628 compatible = "rockchip,rk3126-lvds"; 629 phys = <&video_phy>; 630 phy-names = "phy"; 631 status = "disabled"; 632 633 ports { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 637 port@0 { 638 reg = <0>; 639 640 lvds_in_vop: endpoint { 641 remote-endpoint = <&vop_out_lvds>; 642 }; 643 }; 644 }; 645 }; 646 647 rgb: rgb { 648 compatible = "rockchip,rk3128-rgb"; 649 phys = <&video_phy>; 650 phy-names = "phy"; 651 pinctrl-names = "default", "sleep"; 652 pinctrl-0 = <&lcdc_rgb_pins>; 653 pinctrl-1 = <&lcdc_sleep_pins>; 654 status = "disabled"; 655 656 ports { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 660 port@0 { 661 reg = <0>; 662 663 rgb_in_vop: endpoint { 664 remote-endpoint = <&vop_out_rgb>; 665 }; 666 }; 667 }; 668 }; 669 }; 670 671 pinctrl: pinctrl@20008000 { 672 compatible = "rockchip,rk3128-pinctrl"; 673 reg = <0x20008000 0xA8>, 674 <0x200080A8 0x4C>, 675 <0x20008118 0x20>, 676 <0x20008100 0x04>; 677 reg-names = "base", "mux", "pull", "drv"; 678 rockchip,grf = <&grf>; 679 #address-cells = <1>; 680 #size-cells = <1>; 681 ranges; 682 683 gpio0: gpio0@2007c000 { 684 compatible = "rockchip,gpio-bank"; 685 reg = <0x2007c000 0x100>; 686 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&cru PCLK_GPIO0>; 688 gpio-controller; 689 #gpio-cells = <2>; 690 interrupt-controller; 691 #interrupt-cells = <2>; 692 }; 693 694 gpio1: gpio1@20080000 { 695 compatible = "rockchip,gpio-bank"; 696 reg = <0x20080000 0x100>; 697 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&cru PCLK_GPIO1>; 699 gpio-controller; 700 #gpio-cells = <2>; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 705 gpio2: gpio2@20084000 { 706 compatible = "rockchip,gpio-bank"; 707 reg = <0x20084000 0x100>; 708 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cru PCLK_GPIO2>; 710 gpio-controller; 711 #gpio-cells = <2>; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 }; 715 716 gpio3: gpio2@20088000 { 717 compatible = "rockchip,gpio-bank"; 718 reg = <0x20088000 0x100>; 719 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&cru PCLK_GPIO3>; 721 gpio-controller; 722 #gpio-cells = <2>; 723 interrupt-controller; 724 #interrupt-cells = <2>; 725 }; 726 727 pcfg_pull_default: pcfg_pull_default { 728 bias-pull-pin-default; 729 }; 730 731 pcfg_pull_none: pcfg-pull-none { 732 bias-disable; 733 }; 734 735 emmc { 736 emmc_clk: emmc-clk { 737 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 738 }; 739 740 emmc_cmd: emmc-cmd { 741 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 742 }; 743 744 emmc_cmd1: emmc-cmd1 { 745 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 746 }; 747 748 emmc_pwr: emmc-pwr { 749 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 750 }; 751 752 emmc_bus1: emmc-bus1 { 753 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 754 }; 755 756 emmc_bus4: emmc-bus4 { 757 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 758 <1 RK_PD1 2 &pcfg_pull_default>, 759 <1 RK_PD2 2 &pcfg_pull_default>, 760 <1 RK_PD3 2 &pcfg_pull_default>; 761 }; 762 763 emmc_bus8: emmc-bus8 { 764 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 765 <1 RK_PD1 2 &pcfg_pull_default>, 766 <1 RK_PD2 2 &pcfg_pull_default>, 767 <1 RK_PD3 2 &pcfg_pull_default>, 768 <1 RK_PD4 2 &pcfg_pull_default>, 769 <1 RK_PD5 2 &pcfg_pull_default>, 770 <1 RK_PD6 2 &pcfg_pull_default>, 771 <1 RK_PD7 2 &pcfg_pull_default>; 772 }; 773 }; 774 775 i2c0 { 776 i2c0_xfer: i2c0-xfer { 777 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 778 <0 RK_PA1 1 &pcfg_pull_none>; 779 }; 780 }; 781 782 i2c1 { 783 i2c1_xfer: i2c1-xfer { 784 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 785 <0 RK_PA3 1 &pcfg_pull_none>; 786 }; 787 }; 788 789 i2c2 { 790 i2c2_xfer: i2c2-xfer { 791 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 792 <2 RK_PC5 3 &pcfg_pull_none>; 793 }; 794 }; 795 796 i2c3 { 797 i2c3_xfer: i2c3-xfer { 798 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 799 <0 RK_PA7 1 &pcfg_pull_none>; 800 }; 801 }; 802 803 lcdc { 804 lcdc_rgb_pins: lcdc-rgb-pins { 805 rockchip,pins = 806 <2 RK_PB0 1 &pcfg_pull_none>, /* LCDC_DCLK */ 807 <2 RK_PB1 1 &pcfg_pull_none>, /* LCDC_HSYNC */ 808 <2 RK_PB2 1 &pcfg_pull_none>, /* LCDC_VSYNC */ 809 <2 RK_PB3 1 &pcfg_pull_none>, /* LCDC_DEN */ 810 <2 RK_PB4 1 &pcfg_pull_none>, /* LCDC_DATA10 */ 811 <2 RK_PB5 1 &pcfg_pull_none>, /* LCDC_DATA11 */ 812 <2 RK_PB6 1 &pcfg_pull_none>, /* LCDC_DATA12 */ 813 <2 RK_PB7 1 &pcfg_pull_none>, /* LCDC_DATA13 */ 814 <2 RK_PC0 1 &pcfg_pull_none>, /* LCDC_DATA14 */ 815 <2 RK_PC1 1 &pcfg_pull_none>, /* LCDC_DATA15 */ 816 <2 RK_PC2 1 &pcfg_pull_none>, /* LCDC_DATA16 */ 817 <2 RK_PC3 1 &pcfg_pull_none>, /* LCDC_DATA17 */ 818 <2 RK_PC4 1 &pcfg_pull_none>, /* LCDC_DATA18 */ 819 <2 RK_PC5 1 &pcfg_pull_none>, /* LCDC_DATA19 */ 820 <2 RK_PC6 1 &pcfg_pull_none>, /* LCDC_DATA20 */ 821 <2 RK_PC7 1 &pcfg_pull_none>, /* LCDC_DATA21 */ 822 <2 RK_PD0 1 &pcfg_pull_none>, /* LCDC_DATA22 */ 823 <2 RK_PD1 1 &pcfg_pull_none>; /* LCDC_DATA23 */ 824 }; 825 826 lcdc_sleep_pins: lcdc-sleep-pins { 827 rockchip,pins = 828 <2 RK_PB0 0 &pcfg_pull_none>, /* LCDC_DCLK */ 829 <2 RK_PB1 0 &pcfg_pull_none>, /* LCDC_HSYNC */ 830 <2 RK_PB2 0 &pcfg_pull_none>, /* LCDC_VSYNC */ 831 <2 RK_PB3 0 &pcfg_pull_none>, /* LCDC_DEN */ 832 <2 RK_PB4 0 &pcfg_pull_none>, /* LCDC_DATA10 */ 833 <2 RK_PB5 0 &pcfg_pull_none>, /* LCDC_DATA11 */ 834 <2 RK_PB6 0 &pcfg_pull_none>, /* LCDC_DATA12 */ 835 <2 RK_PB7 0 &pcfg_pull_none>, /* LCDC_DATA13 */ 836 <2 RK_PC0 0 &pcfg_pull_none>, /* LCDC_DATA14 */ 837 <2 RK_PC1 0 &pcfg_pull_none>, /* LCDC_DATA15 */ 838 <2 RK_PC2 0 &pcfg_pull_none>, /* LCDC_DATA16 */ 839 <2 RK_PC3 0 &pcfg_pull_none>, /* LCDC_DATA17 */ 840 <2 RK_PC4 0 &pcfg_pull_none>, /* LCDC_DATA18 */ 841 <2 RK_PC5 0 &pcfg_pull_none>, /* LCDC_DATA19 */ 842 <2 RK_PC6 0 &pcfg_pull_none>, /* LCDC_DATA20 */ 843 <2 RK_PC7 0 &pcfg_pull_none>, /* LCDC_DATA21 */ 844 <2 RK_PD0 0 &pcfg_pull_none>, /* LCDC_DATA22 */ 845 <2 RK_PD1 0 &pcfg_pull_none>; /* LCDC_DATA23 */ 846 }; 847 }; 848 849 uart0 { 850 uart0_xfer: uart0-xfer { 851 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 852 <2 RK_PD3 2 &pcfg_pull_none>; 853 }; 854 855 uart0_cts: uart0-cts { 856 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 857 }; 858 859 uart0_rts: uart0-rts { 860 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 861 }; 862 }; 863 864 uart1 { 865 uart1_xfer: uart1-xfer { 866 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 867 <1 RK_PB2 2 &pcfg_pull_default>; 868 }; 869 870 uart1_cts: uart1-cts { 871 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 872 }; 873 874 uart1_rts: uart1-rts { 875 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 876 }; 877 }; 878 879 uart2 { 880 uart2_xfer: uart2-xfer { 881 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 882 <1 RK_PC3 2 &pcfg_pull_none>; 883 }; 884 885 uart2_cts: uart2-cts { 886 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 887 }; 888 889 uart2_rts: uart2-rts { 890 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 891 }; 892 }; 893 894 sdmmc { 895 sdmmc_clk: sdmmc-clk { 896 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 897 }; 898 899 sdmmc_cmd: sdmmc-cmd { 900 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 901 }; 902 903 sdmmc_wp: sdmmc-wp { 904 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 905 }; 906 907 sdmmc_pwren: sdmmc-pwren { 908 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 909 }; 910 911 sdmmc_bus4: sdmmc-bus4 { 912 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 913 <1 RK_PC3 1 &pcfg_pull_default>, 914 <1 RK_PC4 1 &pcfg_pull_default>, 915 <1 RK_PC5 1 &pcfg_pull_default>; 916 }; 917 }; 918 919 sdio { 920 sdio_clk: sdio-clk { 921 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 922 }; 923 924 sdio_cmd: sdio-cmd { 925 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 926 }; 927 928 sdio_pwren: sdio-pwren { 929 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 930 }; 931 932 sdio_bus4: sdio-bus4 { 933 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 934 <1 RK_PA2 2 &pcfg_pull_default>, 935 <1 RK_PA4 2 &pcfg_pull_default>, 936 <1 RK_PA5 2 &pcfg_pull_default>; 937 }; 938 }; 939 940 hdmi { 941 hdmii2c_xfer: hdmii2c-xfer { 942 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 943 <0 RK_PA7 2 &pcfg_pull_none>; 944 }; 945 }; 946 947 i2s { 948 i2s_bus: i2s-bus { 949 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 950 <0 RK_PB1 1 &pcfg_pull_none>, 951 <0 RK_PB3 1 &pcfg_pull_none>, 952 <0 RK_PB4 1 &pcfg_pull_none>, 953 <0 RK_PB5 1 &pcfg_pull_none>, 954 <0 RK_PB6 1 &pcfg_pull_none>; 955 }; 956 957 i2s1_bus: i2s1-bus { 958 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 959 <1 RK_PA1 1 &pcfg_pull_none>, 960 <1 RK_PA2 1 &pcfg_pull_none>, 961 <1 RK_PA3 1 &pcfg_pull_none>, 962 <1 RK_PA4 1 &pcfg_pull_none>, 963 <1 RK_PA5 1 &pcfg_pull_none>; 964 }; 965 }; 966 967 pwm0 { 968 pwm0_pin: pwm0-pin { 969 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 970 }; 971 }; 972 973 pwm1 { 974 pwm1_pin: pwm1-pin { 975 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 976 }; 977 }; 978 979 pwm2 { 980 pwm2_pin: pwm2-pin { 981 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 982 }; 983 }; 984 985 pwm3 { 986 pwm3_pin: pwm3-pin { 987 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 988 }; 989 }; 990 991 gmac { 992 rgmii_pins: rgmii-pins { 993 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 994 <2 RK_PB1 3 &pcfg_pull_default>, 995 <2 RK_PB3 3 &pcfg_pull_default>, 996 <2 RK_PB4 3 &pcfg_pull_default>, 997 <2 RK_PB5 3 &pcfg_pull_default>, 998 <2 RK_PB6 3 &pcfg_pull_default>, 999 <2 RK_PC0 3 &pcfg_pull_default>, 1000 <2 RK_PC1 3 &pcfg_pull_default>, 1001 <2 RK_PC2 3 &pcfg_pull_default>, 1002 <2 RK_PC3 3 &pcfg_pull_default>, 1003 <2 RK_PD1 3 &pcfg_pull_default>, 1004 <2 RK_PC4 4 &pcfg_pull_default>, 1005 <2 RK_PC5 4 &pcfg_pull_default>, 1006 <2 RK_PC6 4 &pcfg_pull_default>, 1007 <2 RK_PC7 4 &pcfg_pull_default>; 1008 }; 1009 1010 rmii_pins: rmii-pins { 1011 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 1012 <2 RK_PB4 3 &pcfg_pull_default>, 1013 <2 RK_PB5 3 &pcfg_pull_default>, 1014 <2 RK_PB6 3 &pcfg_pull_default>, 1015 <2 RK_PB7 3 &pcfg_pull_default>, 1016 <2 RK_PC0 3 &pcfg_pull_default>, 1017 <2 RK_PC1 3 &pcfg_pull_default>, 1018 <2 RK_PC3 3 &pcfg_pull_default>, 1019 <2 RK_PC4 3 &pcfg_pull_default>, 1020 <2 RK_PD1 3 &pcfg_pull_default>; 1021 }; 1022 }; 1023 1024 spdif { 1025 spdif_tx: spdif-tx { 1026 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1027 }; 1028 }; 1029 1030 spi { 1031 spi0_clk: spi0-clk { 1032 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1033 }; 1034 1035 spi0_cs0: spi0-cs0 { 1036 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1037 }; 1038 1039 spi0_tx: spi0-tx { 1040 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1041 }; 1042 1043 spi0_rx: spi0-rx { 1044 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1045 }; 1046 1047 spi0_cs1: spi0-cs1 { 1048 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1049 }; 1050 1051 spi1_clk: spi1-clk { 1052 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1053 }; 1054 1055 spi1_cs0: spi1-cs0 { 1056 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1057 }; 1058 1059 spi1_tx: spi1-tx { 1060 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1061 }; 1062 1063 spi1_rx: spi1-rx { 1064 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1065 }; 1066 1067 spi1_cs1: spi1-cs1 { 1068 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1069 }; 1070 1071 spi2_clk: spi2-clk { 1072 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1073 }; 1074 1075 spi2_cs0: spi2-cs0 { 1076 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1077 }; 1078 1079 spi2_tx: spi2-tx { 1080 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1081 }; 1082 1083 spi2_rx: spi2-rx { 1084 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1085 }; 1086 }; 1087 }; 1088}; 1089
