1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include "skeleton.dtsi" 13 14/ { 15 compatible = "rockchip,rk3128"; 16 rockchip,sram = <&sram>; 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 spi0 = &spi0; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 mmc0 = &emmc; 35 mmc1 = &sdmmc; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x60000000 0x40000000>; 41 }; 42 43 arm-pmu { 44 compatible = "arm,cortex-a7-pmu"; 45 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "rockchip,rk3128-smp"; 55 56 cpu0:cpu@0x000 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a7"; 59 reg = <0x000>; 60 operating-points = < 61 /* KHz uV */ 62 816000 1000000 63 >; 64 #cooling-cells = <2>; /* min followed by max */ 65 clock-latency = <40000>; 66 clocks = <&cru ARMCLK>; 67 }; 68 69 cpu1:cpu@0x001 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a7"; 72 reg = <0x001>; 73 }; 74 75 cpu2:cpu@0x002 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a7"; 78 reg = <0x002>; 79 }; 80 81 cpu3:cpu@0x003 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a7"; 84 reg = <0x003>; 85 }; 86 }; 87 88 cpu_axi_bus: cpu_axi_bus { 89 compatible = "rockchip,cpu_axi_bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges; 93 94 qos { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 crypto { 100 reg = <0x10128080 0x20>; 101 }; 102 103 core { 104 reg = <0x1012a000 0x20>; 105 }; 106 107 peri { 108 reg = <0x1012c000 0x20>; 109 }; 110 111 gpu { 112 reg = <0x1012d000 0x20>; 113 }; 114 115 vpu { 116 reg = <0x1012e000 0x20>; 117 }; 118 119 rga { 120 reg = <0x1012f000 0x20>; 121 }; 122 ebc { 123 reg = <0x1012f080 0x20>; 124 }; 125 126 iep { 127 reg = <0x1012f100 0x20>; 128 }; 129 130 lcdc { 131 reg = <0x1012f180 0x20>; 132 rockchip,priority = <3 3>; 133 }; 134 135 vip { 136 reg = <0x1012f200 0x20>; 137 rockchip,priority = <3 3>; 138 }; 139 }; 140 141 msch { 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges; 145 146 msch@10128000 { 147 reg = <0x10128000 0x20>; 148 rockchip,read-latency = <0x3f>; 149 }; 150 }; 151 }; 152 153 psci { 154 compatible = "arm,psci"; 155 method = "smc"; 156 cpu_suspend = <0x84000001>; 157 cpu_off = <0x84000002>; 158 cpu_on = <0x84000003>; 159 migrate = <0x84000005>; 160 }; 161 162 amba { 163 compatible = "arm,amba-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 interrupt-parent = <&gic>; 167 ranges; 168 169 pdma: pdma@20078000 { 170 compatible = "arm,pl330", "arm,primecell"; 171 reg = <0x20078000 0x4000>; 172 arm,pl330-broken-no-flushp;//2 173 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 175 #dma-cells = <1>; 176 clocks = <&cru ACLK_DMAC2>; 177 clock-names = "apb_pclk"; 178 }; 179 }; 180 181 xin24m: xin24m { 182 compatible = "fixed-clock"; 183 clock-frequency = <24000000>; 184 clock-output-names = "xin24m"; 185 #clock-cells = <0>; 186 }; 187 188 xin12m: xin12m { 189 compatible = "fixed-clock"; 190 clocks = <&xin24m>; 191 clock-frequency = <12000000>; 192 clock-output-names = "xin12m"; 193 #clock-cells = <0>; 194 }; 195 196 197 timer { 198 compatible = "arm,armv7-timer"; 199 arm,cpu-registers-not-fw-configured; 200 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 201 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 202 clock-frequency = <24000000>; 203 }; 204 205 timer@20044000 { 206 compatible = "arm,armv7-timer"; 207 reg = <0x20044000 0xb8>; 208 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 209 rockchip,broadcast = <1>; 210 }; 211 212 watchdog: wdt@2004c000 { 213 compatible = "rockchip,watch dog"; 214 reg = <0x2004c000 0x100>; 215 clock-names = "pclk_wdt"; 216 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 217 rockchip,irq = <1>; 218 rockchip,timeout = <60>; 219 rockchip,atboot = <1>; 220 rockchip,debug = <0>; 221 }; 222 223 reset: reset@20000110 { 224 compatible = "rockchip,reset"; 225 reg = <0x20000110 0x24>; 226 #reset-cells = <1>; 227 }; 228 229 nandc: nandc@10500000 { 230 compatible = "rockchip,rk-nandc"; 231 reg = <0x10500000 0x4000>; 232 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; 235 nandc_id = <0>; 236 clocks = <&cru SCLK_NANDC>, 237 <&cru HCLK_NANDC>, 238 <&cru SRST_NANDC>; 239 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; 240 }; 241 242 dmc: dmc@20004000 { 243 u-boot,dm-pre-reloc; 244 compatible = "rockchip,rk3128-dmc", "syscon"; 245 reg = <0x0 0x20004000 0x0 0x1000>; 246 }; 247 248 cru: clock-controller@20000000 { 249 u-boot,dm-pre-reloc; 250 compatible = "rockchip,rk3128-cru"; 251 reg = <0x20000000 0x1000>; 252 rockchip,grf = <&grf>; 253 #clock-cells = <1>; 254 #reset-cells = <1>; 255 assigned-clocks = <&cru PLL_GPLL>; 256 assigned-clock-rates = <594000000>; 257 }; 258 259 uart0: serial0@20060000 { 260 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 261 reg = <0x20060000 0x100>; 262 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 263 reg-shift = <2>; 264 reg-io-width = <4>; 265 clock-frequency = <24000000>; 266 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 267 clock-names = "baudclk", "apb_pclk"; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 270 dmas = <&pdma 2>, <&pdma 3>; 271 #dma-cells = <2>; 272 }; 273 274 uart1: serial1@20064000 { 275 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 276 reg = <0x20064000 0x100>; 277 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 278 reg-shift = <2>; 279 reg-io-width = <4>; 280 clock-frequency = <24000000>; 281 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 282 clock-names = "baudclk", "apb_pclk"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&uart1_xfer>; 285 dmas = <&pdma 4>, <&pdma 5>; 286 #dma-cells = <2>; 287 }; 288 289 uart2: serial2@20068000 { 290 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 291 reg = <0x20068000 0x100>; 292 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 293 reg-shift = <2>; 294 reg-io-width = <4>; 295 clock-frequency = <24000000>; 296 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 297 clock-names = "baudclk", "apb_pclk"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&uart2_xfer>; 300 dmas = <&pdma 6>, <&pdma 7>; 301 #dma-cells = <2>; 302 }; 303 304 saradc: saradc@2006c000 { 305 compatible = "rockchip,saradc"; 306 reg = <0x2006c000 0x100>; 307 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 308 #io-channel-cells = <1>; 309 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 310 clock-names = "saradc", "apb_pclk"; 311 resets = <&cru SRST_SARADC>; 312 reset-names = "saradc-apb"; 313 status = "disabled"; 314 }; 315 316 pwm0: pwm0@20050000 { 317 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 318 reg = <0x20050000 0x10>; 319 #pwm-cells = <2>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pwm0_pin>; 322 clocks = <&cru PCLK_PWM>; 323 clock-names = "pwm"; 324 }; 325 326 pwm1: pwm1@20050010 { 327 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 328 reg = <0x20050010 0x10>; 329 #pwm-cells = <2>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pwm1_pin>; 332 clocks = <&cru PCLK_PWM>; 333 clock-names = "pwm"; 334 }; 335 336 pwm2: pwm2@20050020 { 337 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 338 reg = <0x20050020 0x10>; 339 #pwm-cells = <2>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pwm2_pin>; 342 clocks = <&cru PCLK_PWM>; 343 clock-names = "pwm"; 344 }; 345 346 pwm3: pwm3@20050030 { 347 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 348 reg = <0x20050030 0x10>; 349 #pwm-cells = <2>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pwm3_pin>; 352 clocks = <&cru PCLK_PWM>; 353 clock-names = "pwm"; 354 }; 355 356 sram: sram@10080400 { 357 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 358 reg = <0x10080400 0x1C00>; 359 map-exec; 360 map-cacheable; 361 }; 362 363 pmu: syscon@100a0000 { 364 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 365 reg = <0x100a0000 0x1000>; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 }; 369 370 vop: vop@1010e000 { 371 u-boot,dm-pre-reloc; 372 compatible = "rockchip,rk3126-vop"; 373 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>; 374 reg-names = "regs", "gamma_lut"; 375 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cru ACLK_VIO0>, <&cru DCLK_LCDC>, <&cru HCLK_LCDC>; 377 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 378 status = "disabled"; 379 380 vop_out: port { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 384 vop_out_lvds: endpoint@1 { 385 reg = <1>; 386 remote-endpoint = <&lvds_in_vop>; 387 }; 388 }; 389 }; 390 391 display_subsystem: display-subsystem { 392 u-boot,dm-pre-reloc; 393 compatible = "rockchip,display-subsystem"; 394 ports = <&vop_out>; 395 396 route { 397 route_lvds: route-lvds { 398 logo,uboot = "logo.bmp"; 399 logo,kernel = "logo_kernel.bmp"; 400 logo,mode = "fullscreen"; 401 charge_logo,mode = "center"; 402 connect = <&vop_out_lvds>; 403 }; 404 }; 405 }; 406 407 gic: interrupt-controller@10139000 { 408 compatible = "arm,gic-400"; 409 interrupt-controller; 410 #interrupt-cells = <3>; 411 #address-cells = <0>; 412 reg = <0x10139000 0x1000>, 413 <0x1013a000 0x1000>, 414 <0x1013c000 0x2000>, 415 <0x1013e000 0x2000>; 416 interrupts = <GIC_PPI 9 0xf04>; 417 }; 418 419 u2phy: usb2-phy { 420 compatible = "rockchip,rk3128-usb2phy"; 421 reg = <0x017c 0x0c>; 422 rockchip,grf = <&grf>; 423 clocks = <&cru SCLK_OTGPHY0>; 424 clock-names = "phyclk"; 425 #clock-cells = <0>; 426 clock-output-names = "usb480m_phy"; 427 #phy-cells = <1>; 428 status = "disabled"; 429 430 u2phy_otg: otg-port { 431 #phy-cells = <0>; 432 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-names = "otg-bvalid", "otg-id", 436 "linestate"; 437 status = "disabled"; 438 }; 439 440 u2phy_host: host-port { 441 #phy-cells = <0>; 442 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 443 interrupt-names = "linestate"; 444 status = "disabled"; 445 }; 446 }; 447 448 usb_otg: usb@10180000 { 449 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", 450 "snps,dwc2"; 451 reg = <0x10180000 0x40000>; 452 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 453 dr_mode = "otg"; 454 g-use-dma; 455 hnp-srp-disable; 456 phys = <&u2phy 0>; 457 phy-names = "usb"; 458 status = "disabled"; 459 }; 460 461 usb_host_ehci: usb@101c0000 { 462 compatible = "generic-ehci"; 463 reg = <0x101c0000 0x20000>; 464 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 465 phys = <&u2phy 1>; 466 phy-names = "usb"; 467 status = "disabled"; 468 }; 469 470 usb_host_ohci: usb@101e0000 { 471 compatible = "generic-ohci"; 472 reg = <0x101e0000 0x20000>; 473 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 474 phys = <&u2phy 1>; 475 phy-names = "usb"; 476 status = "disabled"; 477 }; 478 479 sdmmc: dwmmc@10214000 { 480 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 481 reg = <0x10214000 0x4000>; 482 max-frequency = <150000000>; 483 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 485 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 486 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 487 fifo-depth = <0x100>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 490 bus-width = <4>; 491 status = "disabled"; 492 }; 493 494 emmc: dwmmc@1021c000 { 495 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 496 reg = <0x1021c000 0x4000>; 497 max-frequency = <150000000>; 498 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 500 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 501 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 502 bus-width = <8>; 503 default-sample-phase = <158>; 504 num-slots = <1>; 505 fifo-depth = <0x100>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 508 resets = <&cru SRST_EMMC>; 509 reset-names = "reset"; 510 status = "disabled"; 511 }; 512 513 lvds: lvds@20038000 { 514 u-boot,dm-pre-reloc; 515 compatible = "rockchip,rk3126-lvds"; 516 reg = <0x20038000 0x4000>, <0x10110000 0x100>; 517 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 518 rockchip,grf = <&grf>; 519 status = "disabled"; 520 521 ports { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 525 lvds_in: port@0 { 526 reg = <0>; 527 lvds_in_vop: endpoint { 528 remote-endpoint = <&vop_out_lvds>; 529 }; 530 }; 531 }; 532 }; 533 534 i2c0: i2c0@20072000 { 535 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 536 reg = <0x20072000 0x1000>; 537 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clock-names = "i2c"; 541 clocks = <&cru PCLK_I2C0>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&i2c0_xfer>; 544 }; 545 546 i2c1: i2c1@20056000 { 547 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 548 reg = <0x20056000 0x1000>; 549 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 clock-names = "i2c"; 553 clocks = <&cru PCLK_I2C1>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c1_xfer>; 556 }; 557 558 i2c2: i2c2@2005a000 { 559 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 560 reg = <0x2005a000 0x1000>; 561 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 clock-names = "i2c"; 565 clocks = <&cru PCLK_I2C2>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&i2c2_xfer>; 568 }; 569 570 i2c3: i2c3@2005e000 { 571 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 572 reg = <0x2005e000 0x1000>; 573 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 clock-names = "i2c"; 577 clocks = <&cru PCLK_I2C3>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&i2c3_xfer>; 580 }; 581 582 spi0: spi@20074000 { 583 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 584 reg = <0x20074000 0x1000>; 585 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; 590 rockchip,spi-src-clk = <0>; 591 num-cs = <2>; 592 clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; 593 clock-names = "spi","pclk_spi0"; 594 dmas = <&pdma 8>, <&pdma 9>; 595 #dma-cells = <2>; 596 dma-names = "tx", "rx"; 597 }; 598 599 grf: syscon@20008000 { 600 u-boot,dm-pre-reloc; 601 compatible = "rockchip,rk3128-grf", "syscon"; 602 reg = <0x20008000 0x1000>; 603 }; 604 605 pinctrl: pinctrl@20008000 { 606 compatible = "rockchip,rk3128-pinctrl"; 607 reg = <0x20008000 0xA8>, 608 <0x200080A8 0x4C>, 609 <0x20008118 0x20>, 610 <0x20008100 0x04>; 611 reg-names = "base", "mux", "pull", "drv"; 612 rockchip,grf = <&grf>; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 ranges; 616 617 gpio0: gpio0@2007c000 { 618 compatible = "rockchip,gpio-bank"; 619 reg = <0x2007c000 0x100>; 620 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cru PCLK_GPIO0>; 622 gpio-controller; 623 #gpio-cells = <2>; 624 interrupt-controller; 625 #interrupt-cells = <2>; 626 }; 627 628 gpio1: gpio1@20080000 { 629 compatible = "rockchip,gpio-bank"; 630 reg = <0x20080000 0x100>; 631 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cru PCLK_GPIO1>; 633 gpio-controller; 634 #gpio-cells = <2>; 635 interrupt-controller; 636 #interrupt-cells = <2>; 637 }; 638 639 gpio2: gpio2@20084000 { 640 compatible = "rockchip,gpio-bank"; 641 reg = <0x20084000 0x100>; 642 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cru PCLK_GPIO2>; 644 gpio-controller; 645 #gpio-cells = <2>; 646 interrupt-controller; 647 #interrupt-cells = <2>; 648 }; 649 650 gpio3: gpio2@20088000 { 651 compatible = "rockchip,gpio-bank"; 652 reg = <0x20088000 0x100>; 653 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&cru PCLK_GPIO3>; 655 gpio-controller; 656 #gpio-cells = <2>; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 }; 660 661 pcfg_pull_up: pcfg-pull-up { 662 bias-pull-up; 663 }; 664 665 pcfg_pull_down: pcfg-pull-down { 666 bias-pull-down; 667 }; 668 669 pcfg_pull_none: pcfg-pull-none { 670 bias-disable; 671 }; 672 673 emmc { 674 /* 675 * We run eMMC at max speed; bump up drive strength. 676 * We also have external pulls, so disable the internal ones. 677 */ 678 679 emmc_clk: emmc-clk { 680 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; 681 }; 682 683 emmc_cmd: emmc-cmd { 684 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 685 }; 686 687 emmc_pwren: emmc-pwren { 688 rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; 689 }; 690 691 emmc_bus8: emmc-bus8 { 692 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 693 <1 25 RK_FUNC_2 &pcfg_pull_none>, 694 <1 26 RK_FUNC_2 &pcfg_pull_none>, 695 <1 27 RK_FUNC_2 &pcfg_pull_none>, 696 <1 28 RK_FUNC_2 &pcfg_pull_none>, 697 <1 29 RK_FUNC_2 &pcfg_pull_none>, 698 <1 30 RK_FUNC_2 &pcfg_pull_none>, 699 <1 31 RK_FUNC_2 &pcfg_pull_none>; 700 }; 701 }; 702 703 nandc{ 704 nandc_ale:nandc-ale { 705 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 706 }; 707 708 nandc_cle:nandc-cle { 709 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 710 }; 711 712 nandc_wrn:nandc-wrn { 713 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 714 }; 715 716 nandc_rdn:nandc-rdn { 717 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 718 }; 719 720 nandc_rdy:nandc-rdy { 721 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 722 }; 723 724 nandc_cs0:nandc-cs0 { 725 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 726 }; 727 728 nandc_data: nandc-data { 729 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 730 }; 731 }; 732 733 734 uart0 { 735 uart0_xfer: uart0-xfer { 736 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, 737 <0 17 RK_FUNC_1 &pcfg_pull_none>; 738 }; 739 740 uart0_cts: uart0-cts { 741 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 742 }; 743 744 uart0_rts: uart0-rts { 745 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; 746 }; 747 }; 748 749 uart1 { 750 uart1_xfer: uart1-xfer { 751 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, 752 <2 23 RK_FUNC_1 &pcfg_pull_none>; 753 }; 754 }; 755 756 uart2 { 757 uart2_xfer: uart2-xfer { 758 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, 759 <1 19 RK_FUNC_2 &pcfg_pull_none>; 760 }; 761 }; 762 763 sdmmc { 764 sdmmc_clk: sdmmc-clk { 765 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 766 }; 767 768 sdmmc_cmd: sdmmc-cmd { 769 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; 770 }; 771 772 sdmmc_wp: sdmmc-wp { 773 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; 774 }; 775 776 sdmmc_pwren: sdmmc-pwren { 777 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; 778 }; 779 780 sdmmc_bus4: sdmmc-bus4 { 781 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, 782 <1 RK_PC3 1 &pcfg_pull_up>, 783 <1 RK_PC4 1 &pcfg_pull_up>, 784 <1 RK_PC5 1 &pcfg_pull_up>; 785 }; 786 }; 787 788 pwm0 { 789 pwm0_pin: pwm0-pin { 790 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 791 }; 792 }; 793 794 pwm1 { 795 pwm1_pin: pwm1-pin { 796 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; 797 }; 798 }; 799 800 pwm2 { 801 pwm2_pin: pwm2-pin { 802 rockchip,pins = <0 1 2 &pcfg_pull_none>; 803 }; 804 }; 805 806 pwm3 { 807 pwm3_pin: pwm3-pin { 808 rockchip,pins = <0 27 1 &pcfg_pull_none>; 809 }; 810 }; 811 812 i2c0 { 813 i2c0_xfer: i2c0-xfer { 814 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, 815 <0 1 RK_FUNC_1 &pcfg_pull_none>; 816 }; 817 }; 818 819 i2c1 { 820 i2c1_xfer: i2c1-xfer { 821 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 822 <0 3 RK_FUNC_1 &pcfg_pull_none>; 823 }; 824 }; 825 826 i2c2 { 827 i2c2_xfer: i2c2-xfer { 828 rockchip,pins = <2 20 3 &pcfg_pull_none>, 829 <2 21 3 &pcfg_pull_none>; 830 }; 831 }; 832 833 i2c3 { 834 i2c3_xfer: i2c3-xfer { 835 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 836 <0 7 RK_FUNC_1 &pcfg_pull_none>; 837 }; 838 }; 839 840 spi0 { 841 spi0_txd_mux0:spi0-txd-mux0 { 842 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 843 }; 844 845 spi0_rxd_mux0:spi0-rxd-mux0 { 846 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 847 }; 848 849 spi0_clk_mux0:spi0-clk-mux0 { 850 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 851 }; 852 853 spi0_cs0_mux0:spi0-cs0-mux0 { 854 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 855 }; 856 857 spi0_cs1_mux0:spi0-cs1-mux0 { 858 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 859 }; 860 }; 861 862 }; 863}; 864
