1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3036-cru.h> 10#include "skeleton.dtsi" 11 12/ { 13 compatible = "rockchip,rk3036"; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 gpio0 = &gpio0; 19 gpio1 = &gpio1; 20 gpio2 = &gpio2; 21 i2c1 = &i2c1; 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 mmc0 = &emmc; 26 mmc1 = &sdmmc; 27 }; 28 29 memory { 30 device_type = "memory"; 31 reg = <0x60000000 0x40000000>; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a7-pmu"; 36 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 38 interrupt-affinity = <&cpu0>, <&cpu1>; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 enable-method = "rockchip,rk3036-smp"; 45 46 cpu0: cpu@f00 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf00>; 50 operating-points = < 51 /* KHz uV */ 52 816000 1000000 53 >; 54 #cooling-cells = <2>; /* min followed by max */ 55 clock-latency = <40000>; 56 clocks = <&cru ARMCLK>; 57 resets = <&cru SRST_CORE0>; 58 }; 59 cpu1: cpu@f01 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf01>; 63 resets = <&cru SRST_CORE1>; 64 }; 65 }; 66 67 amba { 68 compatible = "arm,amba-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges; 72 73 pdma: pdma@20078000 { 74 compatible = "arm,pl330", "arm,primecell"; 75 reg = <0x20078000 0x4000>; 76 arm,pl330-broken-no-flushp; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 79 #dma-cells = <1>; 80 clocks = <&cru ACLK_DMAC2>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 xin24m: oscillator { 86 compatible = "fixed-clock"; 87 clock-frequency = <24000000>; 88 clock-output-names = "xin24m"; 89 #clock-cells = <0>; 90 }; 91 92 psci: psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 timer { 98 compatible = "arm,armv7-timer"; 99 arm,cpu-registers-not-fw-configured; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 104 clock-frequency = <24000000>; 105 }; 106 107 cru: clock-controller@20000000 { 108 compatible = "rockchip,rk3036-cru"; 109 reg = <0x20000000 0x1000>; 110 rockchip,grf = <&grf>; 111 #clock-cells = <1>; 112 #reset-cells = <1>; 113 assigned-clocks = <&cru PLL_GPLL>; 114 assigned-clock-rates = <594000000>; 115 }; 116 117 dmc: dmc@20004000 { 118 compatible = "rockchip,rk3036-dmc", "syscon"; 119 reg = <0x0 0x20004000 0x0 0x1000>; 120 }; 121 122 uart0: serial@20060000 { 123 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 124 reg = <0x20060000 0x100>; 125 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 126 reg-shift = <2>; 127 reg-io-width = <4>; 128 clock-frequency = <24000000>; 129 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 130 clock-names = "baudclk", "apb_pclk"; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 133 }; 134 135 uart1: serial@20064000 { 136 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 137 reg = <0x20064000 0x100>; 138 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 139 reg-shift = <2>; 140 reg-io-width = <4>; 141 clock-frequency = <24000000>; 142 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 143 clock-names = "baudclk", "apb_pclk"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&uart1_xfer>; 146 }; 147 148 uart2: serial@20068000 { 149 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 150 reg = <0x20068000 0x100>; 151 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 152 reg-shift = <2>; 153 reg-io-width = <4>; 154 clock-frequency = <24000000>; 155 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 156 clock-names = "baudclk", "apb_pclk"; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&uart2_xfer>; 159 }; 160 161 pwm0: pwm@20050000 { 162 compatible = "rockchip,rk2928-pwm"; 163 reg = <0x20050000 0x10>; 164 #pwm-cells = <3>; 165 pinctrl-names = "active"; 166 pinctrl-0 = <&pwm0_pin>; 167 clocks = <&cru PCLK_PWM>; 168 clock-names = "pwm"; 169 status = "disabled"; 170 }; 171 172 pwm1: pwm@20050010 { 173 compatible = "rockchip,rk2928-pwm"; 174 reg = <0x20050010 0x10>; 175 #pwm-cells = <3>; 176 pinctrl-names = "active"; 177 pinctrl-0 = <&pwm1_pin>; 178 clocks = <&cru PCLK_PWM>; 179 clock-names = "pwm"; 180 status = "disabled"; 181 }; 182 183 pwm2: pwm@20050020 { 184 compatible = "rockchip,rk2928-pwm"; 185 reg = <0x20050020 0x10>; 186 #pwm-cells = <3>; 187 pinctrl-names = "active"; 188 pinctrl-0 = <&pwm2_pin>; 189 clocks = <&cru PCLK_PWM>; 190 clock-names = "pwm"; 191 status = "disabled"; 192 }; 193 194 pwm3: pwm@20050030 { 195 compatible = "rockchip,rk2928-pwm"; 196 reg = <0x20050030 0x10>; 197 #pwm-cells = <2>; 198 pinctrl-names = "active"; 199 pinctrl-0 = <&pwm3_pin>; 200 clocks = <&cru PCLK_PWM>; 201 clock-names = "pwm"; 202 status = "disabled"; 203 }; 204 205 sram: sram@10080000 { 206 compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; 207 reg = <0x10080000 0x2000>; 208 }; 209 210 gic: interrupt-controller@10139000 { 211 compatible = "arm,gic-400"; 212 interrupt-controller; 213 #interrupt-cells = <3>; 214 #address-cells = <0>; 215 216 reg = <0x10139000 0x1000>, 217 <0x1013a000 0x1000>, 218 <0x1013c000 0x2000>, 219 <0x1013e000 0x2000>; 220 interrupts = <GIC_PPI 9 0xf04>; 221 }; 222 223 grf: syscon@20008000 { 224 compatible = "rockchip,rk3036-grf", "syscon"; 225 reg = <0x20008000 0x1000>; 226 }; 227 228 usb_otg: usb@10180000 { 229 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 230 "snps,dwc2"; 231 reg = <0x10180000 0x40000>; 232 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&cru HCLK_OTG0>; 234 clock-names = "otg"; 235 dr_mode = "otg"; 236 g-np-tx-fifo-size = <16>; 237 g-rx-fifo-size = <275>; 238 g-tx-fifo-size = <256 128 128 64 64 32>; 239 g-use-dma; 240 status = "disabled"; 241 }; 242 243 usb_host: usb@101c0000 { 244 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 245 "snps,dwc2"; 246 reg = <0x101c0000 0x40000>; 247 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&cru HCLK_OTG1>; 249 clock-names = "otg"; 250 dr_mode = "host"; 251 status = "disabled"; 252 }; 253 254 emmc: dwmmc@1021c000 { 255 compatible = "rockchip,rk3288-dw-mshc"; 256 clock-frequency = <37500000>; 257 max-frequency = <37500000>; 258 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 259 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 260 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 261 dmas = <&pdma 12>; 262 dma-names = "rx-tx"; 263 fifo-depth = <0x100>; 264 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 265 reg = <0x1021c000 0x4000>; 266 broken-cd; 267 bus-width = <8>; 268 cap-mmc-highspeed; 269 mmc-ddr-1_8v; 270 disable-wp; 271 fifo-mode; 272 non-removable; 273 num-slots = <1>; 274 default-sample-phase = <158>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 277 }; 278 279 sfc: sfc@102080000 { 280 compatible = "rockchip,rksfc"; 281 reg = <0x10208000 0x4000>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 286 clock-names = "clk_sfc", "hclk_sfc"; 287 status = "disabled"; 288 }; 289 290 sdmmc: dwmmc@10214000 { 291 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 292 reg = <0x10214000 0x4000>; 293 clock-frequency = <37500000>; 294 max-frequency = <37500000>; 295 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 296 clock-names = "biu", "ciu"; 297 fifo-depth = <0x100>; 298 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 299 status = "disabled"; 300 }; 301 302 nandc: nandc@10500000 { 303 compatible = "rockchip,rk-nandc"; 304 reg = <0x10500000 0x4000>; 305 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 306 nandc_id = <0>; 307 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 308 clock-names = "clk_nandc", "hclk_nandc"; 309 status = "disabled"; 310 }; 311 312 pinctrl: pinctrl { 313 compatible = "rockchip,rk3036-pinctrl"; 314 rockchip,grf = <&grf>; 315 #address-cells = <1>; 316 #size-cells = <1>; 317 ranges; 318 319 gpio0: gpio0@2007c000 { 320 compatible = "rockchip,gpio-bank"; 321 reg = <0x2007c000 0x100>; 322 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&cru PCLK_GPIO0>; 324 325 gpio-controller; 326 #gpio-cells = <2>; 327 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 }; 331 332 gpio1: gpio1@20080000 { 333 compatible = "rockchip,gpio-bank"; 334 reg = <0x20080000 0x100>; 335 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&cru PCLK_GPIO1>; 337 338 gpio-controller; 339 #gpio-cells = <2>; 340 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 }; 344 345 gpio2: gpio2@20084000 { 346 compatible = "rockchip,gpio-bank"; 347 reg = <0x20084000 0x100>; 348 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&cru PCLK_GPIO2>; 350 351 gpio-controller; 352 #gpio-cells = <2>; 353 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 }; 357 358 pcfg_pull_up: pcfg-pull-up { 359 bias-pull-up; 360 }; 361 362 pcfg_pull_down: pcfg-pull-down { 363 bias-pull-down; 364 }; 365 366 pcfg_pull_none: pcfg-pull-none { 367 bias-disable; 368 }; 369 370 emmc { 371 /* 372 * We run eMMC at max speed; bump up drive strength. 373 * We also have external pulls, so disable the internal ones. 374 */ 375 emmc_clk: emmc-clk { 376 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 377 }; 378 379 emmc_cmd: emmc-cmd { 380 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; 381 }; 382 383 emmc_bus8: emmc-bus8 { 384 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 385 <1 25 RK_FUNC_2 &pcfg_pull_none>, 386 <1 26 RK_FUNC_2 &pcfg_pull_none>, 387 <1 27 RK_FUNC_2 &pcfg_pull_none>; 388 /* 389 <1 28 RK_FUNC_2 &pcfg_pull_up>, 390 <1 29 RK_FUNC_2 &pcfg_pull_up>, 391 <1 30 RK_FUNC_2 &pcfg_pull_up>, 392 <1 31 RK_FUNC_2 &pcfg_pull_up>; 393 */ 394 }; 395 }; 396 397 uart0 { 398 uart0_xfer: uart0-xfer { 399 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, 400 <0 17 RK_FUNC_1 &pcfg_pull_none>; 401 }; 402 403 uart0_cts: uart0-cts { 404 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 405 }; 406 407 uart0_rts: uart0-rts { 408 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; 409 }; 410 }; 411 412 uart1 { 413 uart1_xfer: uart1-xfer { 414 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, 415 <2 23 RK_FUNC_1 &pcfg_pull_none>; 416 }; 417 /* no rts / cts for uart1 */ 418 }; 419 420 uart2 { 421 uart2_xfer: uart2-xfer { 422 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, 423 <1 19 RK_FUNC_2 &pcfg_pull_none>; 424 }; 425 /* no rts / cts for uart2 */ 426 }; 427 428 pwm0 { 429 pwm0_pin: pwm0-pin { 430 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 431 }; 432 }; 433 434 pwm1 { 435 pwm1_pin: pwm1-pin { 436 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; 437 }; 438 }; 439 440 pwm2 { 441 pwm2_pin: pwm2-pin { 442 rockchip,pins = <0 1 2 &pcfg_pull_none>; 443 }; 444 }; 445 446 pwm3 { 447 pwm3_pin: pwm3-pin { 448 rockchip,pins = <0 27 1 &pcfg_pull_none>; 449 }; 450 }; 451 452 i2c1 { 453 i2c1_xfer: i2c1-xfer { 454 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 455 <0 3 RK_FUNC_1 &pcfg_pull_none>; 456 }; 457 }; 458 }; 459 460 i2c1: i2c@20056000 { 461 compatible = "rockchip,rk3288-i2c"; 462 reg = <0x20056000 0x1000>; 463 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 clock-names = "i2c"; 467 clocks = <&cru PCLK_I2C1>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&i2c1_xfer>; 470 status = "disabled"; 471 }; 472}; 473