1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3036-cru.h> 10#include "skeleton.dtsi" 11 12/ { 13 compatible = "rockchip,rk3036"; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 gpio0 = &gpio0; 19 gpio1 = &gpio1; 20 gpio2 = &gpio2; 21 i2c1 = &i2c1; 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 mmc0 = &emmc; 26 mmc1 = &sdmmc; 27 }; 28 29 memory { 30 device_type = "memory"; 31 reg = <0x60000000 0x40000000>; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a7-pmu"; 36 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 38 interrupt-affinity = <&cpu0>, <&cpu1>; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 enable-method = "rockchip,rk3036-smp"; 45 46 cpu0: cpu@f00 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf00>; 50 operating-points = < 51 /* KHz uV */ 52 816000 1000000 53 >; 54 #cooling-cells = <2>; /* min followed by max */ 55 clock-latency = <40000>; 56 clocks = <&cru ARMCLK>; 57 resets = <&cru SRST_CORE0>; 58 }; 59 cpu1: cpu@f01 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 reg = <0xf01>; 63 resets = <&cru SRST_CORE1>; 64 }; 65 }; 66 67 amba { 68 compatible = "arm,amba-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges; 72 73 pdma: pdma@20078000 { 74 compatible = "arm,pl330", "arm,primecell"; 75 reg = <0x20078000 0x4000>; 76 arm,pl330-broken-no-flushp; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 79 #dma-cells = <1>; 80 clocks = <&cru ACLK_DMAC2>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 xin24m: oscillator { 86 compatible = "fixed-clock"; 87 clock-frequency = <24000000>; 88 clock-output-names = "xin24m"; 89 #clock-cells = <0>; 90 }; 91 92 timer { 93 compatible = "arm,armv7-timer"; 94 arm,cpu-registers-not-fw-configured; 95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 99 clock-frequency = <24000000>; 100 }; 101 102 cru: clock-controller@20000000 { 103 compatible = "rockchip,rk3036-cru"; 104 reg = <0x20000000 0x1000>; 105 rockchip,grf = <&grf>; 106 #clock-cells = <1>; 107 #reset-cells = <1>; 108 assigned-clocks = <&cru PLL_GPLL>; 109 assigned-clock-rates = <594000000>; 110 }; 111 112 dmc: dmc@20004000 { 113 compatible = "rockchip,rk3036-dmc", "syscon"; 114 reg = <0x0 0x20004000 0x0 0x1000>; 115 }; 116 117 uart0: serial@20060000 { 118 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 119 reg = <0x20060000 0x100>; 120 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 121 reg-shift = <2>; 122 reg-io-width = <4>; 123 clock-frequency = <24000000>; 124 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 125 clock-names = "baudclk", "apb_pclk"; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 128 }; 129 130 uart1: serial@20064000 { 131 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 132 reg = <0x20064000 0x100>; 133 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 134 reg-shift = <2>; 135 reg-io-width = <4>; 136 clock-frequency = <24000000>; 137 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 138 clock-names = "baudclk", "apb_pclk"; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&uart1_xfer>; 141 }; 142 143 uart2: serial@20068000 { 144 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 145 reg = <0x20068000 0x100>; 146 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 147 reg-shift = <2>; 148 reg-io-width = <4>; 149 clock-frequency = <24000000>; 150 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 151 clock-names = "baudclk", "apb_pclk"; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&uart2_xfer>; 154 }; 155 156 pwm0: pwm@20050000 { 157 compatible = "rockchip,rk2928-pwm"; 158 reg = <0x20050000 0x10>; 159 #pwm-cells = <3>; 160 pinctrl-names = "active"; 161 pinctrl-0 = <&pwm0_pin>; 162 clocks = <&cru PCLK_PWM>; 163 clock-names = "pwm"; 164 status = "disabled"; 165 }; 166 167 pwm1: pwm@20050010 { 168 compatible = "rockchip,rk2928-pwm"; 169 reg = <0x20050010 0x10>; 170 #pwm-cells = <3>; 171 pinctrl-names = "active"; 172 pinctrl-0 = <&pwm1_pin>; 173 clocks = <&cru PCLK_PWM>; 174 clock-names = "pwm"; 175 status = "disabled"; 176 }; 177 178 pwm2: pwm@20050020 { 179 compatible = "rockchip,rk2928-pwm"; 180 reg = <0x20050020 0x10>; 181 #pwm-cells = <3>; 182 pinctrl-names = "active"; 183 pinctrl-0 = <&pwm2_pin>; 184 clocks = <&cru PCLK_PWM>; 185 clock-names = "pwm"; 186 status = "disabled"; 187 }; 188 189 pwm3: pwm@20050030 { 190 compatible = "rockchip,rk2928-pwm"; 191 reg = <0x20050030 0x10>; 192 #pwm-cells = <2>; 193 pinctrl-names = "active"; 194 pinctrl-0 = <&pwm3_pin>; 195 clocks = <&cru PCLK_PWM>; 196 clock-names = "pwm"; 197 status = "disabled"; 198 }; 199 200 sram: sram@10080000 { 201 compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; 202 reg = <0x10080000 0x2000>; 203 }; 204 205 gic: interrupt-controller@10139000 { 206 compatible = "arm,gic-400"; 207 interrupt-controller; 208 #interrupt-cells = <3>; 209 #address-cells = <0>; 210 211 reg = <0x10139000 0x1000>, 212 <0x1013a000 0x1000>, 213 <0x1013c000 0x2000>, 214 <0x1013e000 0x2000>; 215 interrupts = <GIC_PPI 9 0xf04>; 216 }; 217 218 grf: syscon@20008000 { 219 compatible = "rockchip,rk3036-grf", "syscon"; 220 reg = <0x20008000 0x1000>; 221 }; 222 223 usb_otg: usb@10180000 { 224 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 225 "snps,dwc2"; 226 reg = <0x10180000 0x40000>; 227 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru HCLK_OTG0>; 229 clock-names = "otg"; 230 dr_mode = "otg"; 231 g-np-tx-fifo-size = <16>; 232 g-rx-fifo-size = <275>; 233 g-tx-fifo-size = <256 128 128 64 64 32>; 234 g-use-dma; 235 status = "disabled"; 236 }; 237 238 usb_host: usb@101c0000 { 239 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 240 "snps,dwc2"; 241 reg = <0x101c0000 0x40000>; 242 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru HCLK_OTG1>; 244 clock-names = "otg"; 245 dr_mode = "host"; 246 status = "disabled"; 247 }; 248 249 emmc: dwmmc@1021c000 { 250 compatible = "rockchip,rk3288-dw-mshc"; 251 clock-frequency = <37500000>; 252 max-frequency = <37500000>; 253 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 254 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 255 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 256 dmas = <&pdma 12>; 257 dma-names = "rx-tx"; 258 fifo-depth = <0x100>; 259 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 260 reg = <0x1021c000 0x4000>; 261 broken-cd; 262 bus-width = <8>; 263 cap-mmc-highspeed; 264 mmc-ddr-1_8v; 265 disable-wp; 266 fifo-mode; 267 non-removable; 268 num-slots = <1>; 269 default-sample-phase = <158>; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 272 }; 273 274 sfc: sfc@102080000 { 275 compatible = "rockchip,rksfc"; 276 reg = <0x10208000 0x4000>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 281 clock-names = "clk_sfc", "hclk_sfc"; 282 status = "disabled"; 283 }; 284 285 sdmmc: dwmmc@10214000 { 286 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 287 reg = <0x10214000 0x4000>; 288 clock-frequency = <37500000>; 289 max-frequency = <37500000>; 290 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 291 clock-names = "biu", "ciu"; 292 fifo-depth = <0x100>; 293 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 294 status = "disabled"; 295 }; 296 297 nandc: nandc@10500000 { 298 compatible = "rockchip,rk-nandc"; 299 reg = <0x10500000 0x4000>; 300 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 301 nandc_id = <0>; 302 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 303 clock-names = "clk_nandc", "hclk_nandc"; 304 status = "disabled"; 305 }; 306 307 pinctrl: pinctrl { 308 compatible = "rockchip,rk3036-pinctrl"; 309 rockchip,grf = <&grf>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 gpio0: gpio0@2007c000 { 315 compatible = "rockchip,gpio-bank"; 316 reg = <0x2007c000 0x100>; 317 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&cru PCLK_GPIO0>; 319 320 gpio-controller; 321 #gpio-cells = <2>; 322 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 }; 326 327 gpio1: gpio1@20080000 { 328 compatible = "rockchip,gpio-bank"; 329 reg = <0x20080000 0x100>; 330 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&cru PCLK_GPIO1>; 332 333 gpio-controller; 334 #gpio-cells = <2>; 335 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 }; 339 340 gpio2: gpio2@20084000 { 341 compatible = "rockchip,gpio-bank"; 342 reg = <0x20084000 0x100>; 343 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cru PCLK_GPIO2>; 345 346 gpio-controller; 347 #gpio-cells = <2>; 348 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 }; 352 353 pcfg_pull_up: pcfg-pull-up { 354 bias-pull-up; 355 }; 356 357 pcfg_pull_down: pcfg-pull-down { 358 bias-pull-down; 359 }; 360 361 pcfg_pull_none: pcfg-pull-none { 362 bias-disable; 363 }; 364 365 emmc { 366 /* 367 * We run eMMC at max speed; bump up drive strength. 368 * We also have external pulls, so disable the internal ones. 369 */ 370 emmc_clk: emmc-clk { 371 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 372 }; 373 374 emmc_cmd: emmc-cmd { 375 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; 376 }; 377 378 emmc_bus8: emmc-bus8 { 379 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 380 <1 25 RK_FUNC_2 &pcfg_pull_none>, 381 <1 26 RK_FUNC_2 &pcfg_pull_none>, 382 <1 27 RK_FUNC_2 &pcfg_pull_none>; 383 /* 384 <1 28 RK_FUNC_2 &pcfg_pull_up>, 385 <1 29 RK_FUNC_2 &pcfg_pull_up>, 386 <1 30 RK_FUNC_2 &pcfg_pull_up>, 387 <1 31 RK_FUNC_2 &pcfg_pull_up>; 388 */ 389 }; 390 }; 391 392 uart0 { 393 uart0_xfer: uart0-xfer { 394 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, 395 <0 17 RK_FUNC_1 &pcfg_pull_none>; 396 }; 397 398 uart0_cts: uart0-cts { 399 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 400 }; 401 402 uart0_rts: uart0-rts { 403 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; 404 }; 405 }; 406 407 uart1 { 408 uart1_xfer: uart1-xfer { 409 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, 410 <2 23 RK_FUNC_1 &pcfg_pull_none>; 411 }; 412 /* no rts / cts for uart1 */ 413 }; 414 415 uart2 { 416 uart2_xfer: uart2-xfer { 417 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, 418 <1 19 RK_FUNC_2 &pcfg_pull_none>; 419 }; 420 /* no rts / cts for uart2 */ 421 }; 422 423 pwm0 { 424 pwm0_pin: pwm0-pin { 425 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 426 }; 427 }; 428 429 pwm1 { 430 pwm1_pin: pwm1-pin { 431 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; 432 }; 433 }; 434 435 pwm2 { 436 pwm2_pin: pwm2-pin { 437 rockchip,pins = <0 1 2 &pcfg_pull_none>; 438 }; 439 }; 440 441 pwm3 { 442 pwm3_pin: pwm3-pin { 443 rockchip,pins = <0 27 1 &pcfg_pull_none>; 444 }; 445 }; 446 447 i2c1 { 448 i2c1_xfer: i2c1-xfer { 449 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 450 <0 3 RK_FUNC_1 &pcfg_pull_none>; 451 }; 452 }; 453 }; 454 455 i2c1: i2c@20056000 { 456 compatible = "rockchip,rk3288-i2c"; 457 reg = <0x20056000 0x1000>; 458 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 clock-names = "i2c"; 462 clocks = <&cru PCLK_I2C1>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&i2c1_xfer>; 465 status = "disabled"; 466 }; 467}; 468