1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 3 4#include <dt-bindings/clock/rk1808-cru.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8#include <dt-bindings/power/rk1808-power.h> 9 10/ { 11 compatible = "rockchip,rk1808"; 12 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 serial4 = &uart4; 29 serial5 = &uart5; 30 serial6 = &uart6; 31 serial7 = &uart7; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35", "arm,armv8"; 44 reg = <0x0 0x0>; 45 clocks = <&cru ARMCLK>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a35", "arm,armv8"; 51 reg = <0x0 0x1>; 52 clocks = <&cru ARMCLK>; 53 }; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>; 61 }; 62 63 dmc: dmc { 64 compatible = "rockchip,rk1808-dmc"; 65 }; 66 67 gmac_clkin: external-gmac-clock { 68 compatible = "fixed-clock"; 69 clock-frequency = <125000000>; 70 clock-output-names = "gmac_clkin"; 71 #clock-cells = <0>; 72 }; 73 74 timer { 75 compatible = "arm,armv8-timer"; 76 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 77 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 78 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 79 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 80 arm,no-tick-in-suspend; 81 }; 82 83 xin24m: xin24m { 84 compatible = "fixed-clock"; 85 clock-frequency = <24000000>; 86 clock-output-names = "xin24m"; 87 #clock-cells = <0>; 88 }; 89 90 xin32k: xin32k { 91 compatible = "fixed-clock"; 92 clock-frequency = <32768>; 93 clock-output-names = "xin32k"; 94 #clock-cells = <0>; 95 }; 96 97 usbdrd3: usb { 98 compatible = "rockchip,rk1808-dwc3"; 99 clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, 100 <&cru SCLK_USB3_OTG0_SUSPEND>; 101 clock-names = "ref_clk", "bus_clk", 102 "suspend_clk"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 status = "disabled"; 107 108 usbdrd_dwc3: dwc3@fd000000 { 109 compatible = "snps,dwc3"; 110 reg = <0x0 0xfd000000 0x0 0x200000>; 111 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 112 dr_mode = "otg"; 113 phys = <&u2phy_otg>; 114 phy-names = "usb2-phy"; 115 phy_type = "utmi_wide"; 116 snps,dis_enblslpm_quirk; 117 snps,dis-u2-freeclk-exists-quirk; 118 snps,dis_u2_susphy_quirk; 119 snps,dis-del-phy-power-chg-quirk; 120 snps,tx-ipgap-linecheck-dis-quirk; 121 status = "disabled"; 122 }; 123 }; 124 125 grf: syscon@fe000000 { 126 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; 127 reg = <0x0 0xfe000000 0x0 0x1000>; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 131 io_domains: io-domains { 132 compatible = "rockchip,rk1808-io-voltage-domain"; 133 status = "disabled"; 134 }; 135 136 rgb: rgb { 137 compatible = "rockchip,rk1808-rgb"; 138 status = "disabled"; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 port@0 { 145 reg = <0>; 146 147 rgb_in_vop_lite: endpoint { 148 remote-endpoint = <&vop_lite_out_rgb>; 149 }; 150 }; 151 }; 152 }; 153 }; 154 155 usb2phy_grf: syscon@fe010000 { 156 compatible = "rockchip,rk1808-usb2phy-grf", "syscon", 157 "simple-mfd"; 158 reg = <0x0 0xfe010000 0x0 0x8000>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 162 u2phy: usb2-phy@100 { 163 compatible = "rockchip,rk1808-usb2phy"; 164 reg = <0x100 0x10>; 165 clocks = <&cru SCLK_USBPHY_REF>; 166 clock-names = "phyclk"; 167 #clock-cells = <0>; 168 assigned-clocks = <&cru USB480M>; 169 assigned-clock-parents = <&u2phy>; 170 clock-output-names = "usb480m_phy"; 171 status = "disabled"; 172 173 u2phy_host: host-port { 174 #phy-cells = <0>; 175 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "linestate"; 177 status = "disabled"; 178 }; 179 180 u2phy_otg: otg-port { 181 #phy-cells = <0>; 182 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "otg-bvalid", "otg-id", 186 "linestate"; 187 status = "disabled"; 188 }; 189 }; 190 }; 191 192 pmugrf: syscon@fe020000 { 193 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; 194 reg = <0x0 0xfe020000 0x0 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 198 pmu_io_domains: io-domains { 199 compatible = "rockchip,rk1808-pmu-io-voltage-domain"; 200 status = "disabled"; 201 }; 202 }; 203 204 qos_npu: qos@fe850000 { 205 compatible = "syscon"; 206 reg = <0x0 0xfe850000 0x0 0x20>; 207 }; 208 209 qos_pcie: qos@fe880000 { 210 compatible = "syscon"; 211 reg = <0x0 0xfe880000 0x0 0x20>; 212 }; 213 214 qos_isp: qos@fe8a0000 { 215 compatible = "syscon"; 216 reg = <0x0 0xfe8a0000 0x0 0x20>; 217 }; 218 219 qos_rga_rd: qos@fe8a0080 { 220 compatible = "syscon"; 221 reg = <0x0 0xfe8a0080 0x0 0x20>; 222 }; 223 224 qos_rga_wr: qos@fe8a0100 { 225 compatible = "syscon"; 226 reg = <0x0 0xfe8a0100 0x0 0x20>; 227 }; 228 229 qos_vip: qos@fe8a0180 { 230 compatible = "syscon"; 231 reg = <0x0 0xfe8a0180 0x0 0x20>; 232 }; 233 234 qos_vop_dma: qos@fe8b0000 { 235 compatible = "syscon"; 236 reg = <0x0 0xfe8b0000 0x0 0x20>; 237 }; 238 239 qos_vop_lite: qos@fe8b0080 { 240 compatible = "syscon"; 241 reg = <0x0 0xfe8b0080 0x0 0x20>; 242 }; 243 244 qos_vpu: qos@fe8cc000 { 245 compatible = "syscon"; 246 reg = <0x0 0xfe8c000 0x0 0x20>; 247 }; 248 249 sram: sram@fec00000 { 250 compatible = "mmio-sram"; 251 reg = <0x0 0xfec00000 0x0 0x200000>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 ranges = <0 0x0 0xfec00000 0x200000>; 255 /* reserved for ddr dvfs and system suspend/resume */ 256 ddr-sram@0 { 257 reg = <0x0 0x8000>; 258 }; 259 /* reserved for vad audio buffer */ 260 vad_sram: vad-sram@1c0000 { 261 reg = <0x1c0000 0x40000>; 262 }; 263 }; 264 265 gic: interrupt-controller@ff100000 { 266 compatible = "arm,gic-v3"; 267 #interrupt-cells = <3>; 268 #address-cells = <2>; 269 #size-cells = <2>; 270 ranges; 271 interrupt-controller; 272 273 reg = <0x0 0xff100000 0 0x10000>, /* GICD */ 274 <0x0 0xff140000 0 0xc0000>, /* GICR */ 275 <0x0 0xff300000 0 0x10000>, /* GICC */ 276 <0x0 0xff310000 0 0x10000>, /* GICH */ 277 <0x0 0xff320000 0 0x10000>; /* GICV */ 278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 279 its: interrupt-controller@ff120000 { 280 compatible = "arm,gic-v3-its"; 281 msi-controller; 282 reg = <0x0 0xff120000 0x0 0x20000>; 283 }; 284 }; 285 286 cru: clock-controller@ff350000 { 287 compatible = "rockchip,rk1808-cru"; 288 reg = <0x0 0xff350000 0x0 0x5000>; 289 rockchip,grf = <&grf>; 290 #clock-cells = <1>; 291 #reset-cells = <1>; 292 293 assigned-clocks = 294 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 295 <&cru PLL_PPLL>, <&cru ARMCLK>, 296 <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 297 <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 298 <&cru LSCLK_BUS_PRE>; 299 assigned-clock-rates = 300 <1200000000>, <1000000000>, 301 <416000000>, <816000000>, 302 <200000000>, <100000000>, 303 <300000000>, <200000000>, 304 <100000000>; 305 }; 306 307 mipi_dphy: mipi-dphy@ff370000 { 308 compatible = "rockchip,rk1808-mipi-dphy"; 309 reg = <0x0 0xff370000 0x0 0x500>; 310 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 311 clock-names = "ref", "pclk"; 312 clock-output-names = "mipi_dphy_pll"; 313 #clock-cells = <0>; 314 resets = <&cru SRST_MIPIDSIPHY_P>; 315 reset-names = "apb"; 316 #phy-cells = <0>; 317 rockchip,grf = <&grf>; 318 status = "disabled"; 319 }; 320 321 tsadc: tsadc@ff3a0000 { 322 compatible = "rockchip,rk1808-tsadc"; 323 reg = <0x0 0xff3a0000 0x0 0x100>; 324 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 325 rockchip,grf = <&grf>; 326 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 327 clock-names = "tsadc", "apb_pclk"; 328 assigned-clocks = <&cru SCLK_TSADC>; 329 assigned-clock-rates = <50000>; 330 resets = <&cru SRST_TSADC>; 331 reset-names = "tsadc-apb"; 332 #thermal-sensor-cells = <1>; 333 rockchip,hw-tshut-temp = <120000>; 334 status = "disabled"; 335 }; 336 337 pwm0: pwm@ff3d0000 { 338 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 339 reg = <0x0 0xff3d0000 0x0 0x10>; 340 #pwm-cells = <3>; 341 pinctrl-names = "active"; 342 pinctrl-0 = <&pwm0_pin>; 343 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 344 clock-names = "pwm", "pclk"; 345 status = "disabled"; 346 }; 347 348 pwm1: pwm@ff3d0010 { 349 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 350 reg = <0x0 0xff3d0010 0x0 0x10>; 351 #pwm-cells = <3>; 352 pinctrl-names = "active"; 353 pinctrl-0 = <&pwm1_pin>; 354 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 355 clock-names = "pwm", "pclk"; 356 status = "disabled"; 357 }; 358 359 pwm2: pwm@ff3d0020 { 360 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 361 reg = <0x0 0xff3d0020 0x0 0x10>; 362 #pwm-cells = <3>; 363 pinctrl-names = "active"; 364 pinctrl-0 = <&pwm2_pin>; 365 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 366 clock-names = "pwm", "pclk"; 367 status = "disabled"; 368 }; 369 370 pwm3: pwm@ff3d0030 { 371 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 372 reg = <0x0 0xff3d0030 0x0 0x10>; 373 #pwm-cells = <3>; 374 pinctrl-names = "active"; 375 pinctrl-0 = <&pwm3_pin>; 376 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 377 clock-names = "pwm", "pclk"; 378 status = "disabled"; 379 }; 380 381 pwm4: pwm@ff3d8000 { 382 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 383 reg = <0x0 0xff3d8000 0x0 0x10>; 384 #pwm-cells = <3>; 385 pinctrl-names = "active"; 386 pinctrl-0 = <&pwm4_pin>; 387 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 388 clock-names = "pwm", "pclk"; 389 status = "disabled"; 390 }; 391 392 pwm5: pwm@ff3d8010 { 393 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 394 reg = <0x0 0xff3d8010 0x0 0x10>; 395 #pwm-cells = <3>; 396 pinctrl-names = "active"; 397 pinctrl-0 = <&pwm5_pin>; 398 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 399 clock-names = "pwm", "pclk"; 400 status = "disabled"; 401 }; 402 403 pwm6: pwm@ff3d8020 { 404 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 405 reg = <0x0 0xff3d8020 0x0 0x10>; 406 #pwm-cells = <3>; 407 pinctrl-names = "active"; 408 pinctrl-0 = <&pwm6_pin>; 409 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 410 clock-names = "pwm", "pclk"; 411 status = "disabled"; 412 }; 413 414 pwm7: pwm@ff3d8030 { 415 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 416 reg = <0x0 0xff3d8030 0x0 0x10>; 417 #pwm-cells = <3>; 418 pinctrl-names = "active"; 419 pinctrl-0 = <&pwm7_pin>; 420 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 421 clock-names = "pwm", "pclk"; 422 status = "disabled"; 423 }; 424 425 pmu: power-management@ff3e0000 { 426 compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; 427 reg = <0x0 0xff3e0000 0x0 0x1000>; 428 429 power: power-controller { 430 compatible = "rockchip,rk1808-power-controller"; 431 #power-domain-cells = <1>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 status = "disabled"; 435 436 /* These power domains are grouped by VD_NPU */ 437 pd_npu@RK1808_VD_NPU { 438 reg = <RK1808_VD_NPU>; 439 clocks = <&cru SCLK_NPU>, 440 <&cru ACLK_NPU>, 441 <&cru HCLK_NPU>; 442 pm_qos = <&qos_npu>; 443 }; 444 445 /* These power domains are grouped by VD_LOGIC */ 446 pd_pcie@RK1808_PD_PCIE { 447 reg = <RK1808_PD_PCIE>; 448 clocks = <&cru HSCLK_PCIE>, 449 <&cru LSCLK_PCIE>, 450 <&cru ACLK_PCIE>, 451 <&cru ACLK_PCIE_MST>, 452 <&cru ACLK_PCIE_SLV>, 453 <&cru PCLK_PCIE>, 454 <&cru SCLK_PCIE_AUX>; 455 pm_qos = <&qos_pcie>; 456 }; 457 pd_vpu@RK1808_PD_VPU { 458 reg = <RK1808_PD_VPU>; 459 clocks = <&cru ACLK_VPU>, 460 <&cru HCLK_VPU>; 461 pm_qos = <&qos_vpu>; 462 }; 463 pd_vio@RK1808_PD_VIO { 464 reg = <RK1808_PD_VIO>; 465 clocks = <&cru HSCLK_VIO>, 466 <&cru LSCLK_VIO>, 467 <&cru ACLK_VOPRAW>, 468 <&cru HCLK_VOPRAW>, 469 <&cru ACLK_VOPLITE>, 470 <&cru HCLK_VOPLITE>, 471 <&cru PCLK_DSI_TX>, 472 <&cru PCLK_CSI_TX>, 473 <&cru ACLK_RGA>, 474 <&cru HCLK_RGA>, 475 <&cru ACLK_ISP>, 476 <&cru HCLK_ISP>, 477 <&cru ACLK_CIF>, 478 <&cru HCLK_CIF>, 479 <&cru PCLK_CSI2HOST>, 480 <&cru DCLK_VOPRAW>, 481 <&cru DCLK_VOPLITE>; 482 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 483 <&qos_isp>, <&qos_vip>, 484 <&qos_vop_dma>, <&qos_vop_lite>; 485 }; 486 }; 487 }; 488 489 i2c0: i2c@ff410000 { 490 compatible = "rockchip,rk3399-i2c"; 491 reg = <0x0 0xff410000 0x0 0x1000>; 492 clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; 493 clock-names = "i2c", "pclk"; 494 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&i2c0_xfer>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 dmac: dmac@ff4e0000 { 503 compatible = "arm,pl330", "arm,primecell"; 504 reg = <0x0 0xff4e0000 0x0 0x4000>; 505 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cru ACLK_DMAC>; 507 clock-names = "apb_pclk"; 508 #dma-cells = <1>; 509 peripherals-req-type-burst; 510 }; 511 512 uart0: serial@ff430000 { 513 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 514 reg = <0x0 0xff430000 0x0 0x100>; 515 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 517 clock-names = "baudclk", "apb_pclk"; 518 reg-shift = <2>; 519 reg-io-width = <4>; 520 dmas = <&dmac 0>, <&dmac 1>; 521 dma-names = "tx", "rx"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 524 status = "disabled"; 525 }; 526 527 i2c1: i2c@ff500000 { 528 compatible = "rockchip,rk3399-i2c"; 529 reg = <0x0 0xff500000 0x0 0x1000>; 530 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 531 clock-names = "i2c", "pclk"; 532 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&i2c1_xfer>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 i2c2: i2c@ff504000 { 541 compatible = "rockchip,rk3399-i2c"; 542 reg = <0x0 0xff504000 0x0 0x1000>; 543 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 544 clock-names = "i2c", "pclk"; 545 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&i2c2m0_xfer>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 i2c3: i2c@ff508000 { 554 compatible = "rockchip,rk3399-i2c"; 555 reg = <0x0 0xff508000 0x0 0x1000>; 556 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 557 clock-names = "i2c", "pclk"; 558 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2c3_xfer>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 566 i2c4: i2c@ff50c000 { 567 compatible = "rockchip,rk3399-i2c"; 568 reg = <0x0 0xff50c000 0x0 0x1000>; 569 clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; 570 clock-names = "i2c", "pclk"; 571 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2c4_xfer>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 }; 578 579 i2c5: i2c@ff510000 { 580 compatible = "rockchip,rk3399-i2c"; 581 reg = <0x0 0xff100000 0x0 0x1000>; 582 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 583 clock-names = "i2c", "pclk"; 584 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&i2c5_xfer>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 spi0: spi@ff520000 { 593 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 594 reg = <0x0 0xff520000 0x0 0x1000>; 595 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 599 clock-names = "spiclk", "apb_pclk"; 600 dmas = <&dmac 10>, <&dmac 11>; 601 dma-names = "tx", "rx"; 602 pinctrl-names = "default", "high_speed"; 603 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 604 pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; 605 status = "disabled"; 606 }; 607 608 spi1: spi@ff530000 { 609 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 610 reg = <0x0 0xff530000 0x0 0x1000>; 611 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 615 clock-names = "spiclk", "apb_pclk"; 616 dmas = <&dmac 12>, <&dmac 13>; 617 dma-names = "tx", "rx"; 618 pinctrl-names = "default", "high_speed"; 619 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 620 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; 621 status = "disabled"; 622 }; 623 624 uart1: serial@ff540000 { 625 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 626 reg = <0x0 0xff540000 0x0 0x100>; 627 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 629 clock-names = "baudclk", "apb_pclk"; 630 reg-shift = <2>; 631 reg-io-width = <4>; 632 dmas = <&dmac 2>, <&dmac 3>; 633 dma-names = "tx", "rx"; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>; 636 status = "disabled"; 637 }; 638 639 uart2: serial@ff550000 { 640 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 641 reg = <0x0 0xff550000 0x0 0x100>; 642 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 644 clock-names = "baudclk", "apb_pclk"; 645 reg-shift = <2>; 646 reg-io-width = <4>; 647 dmas = <&dmac 4>, <&dmac 5>; 648 dma-names = "tx", "rx"; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&uart2m0_xfer>; 651 status = "disabled"; 652 }; 653 654 uart3: serial@ff560000 { 655 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 656 reg = <0x0 0xff560000 0x0 0x100>; 657 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 659 clock-names = "baudclk", "apb_pclk"; 660 reg-shift = <2>; 661 reg-io-width = <4>; 662 dmas = <&dmac 6>, <&dmac 7>; 663 dma-names = "tx", "rx"; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>; 666 status = "disabled"; 667 }; 668 669 uart4: serial@ff570000 { 670 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 671 reg = <0x0 0xff570000 0x0 0x100>; 672 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 674 clock-names = "baudclk", "apb_pclk"; 675 reg-shift = <2>; 676 reg-io-width = <4>; 677 dmas = <&dmac 8>, <&dmac 9>; 678 dma-names = "tx", "rx"; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 681 status = "disabled"; 682 }; 683 684 spi2: spi@ff580000 { 685 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 686 reg = <0x0 0xff580000 0x0 0x1000>; 687 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 691 clock-names = "spiclk", "apb_pclk"; 692 dmas = <&dmac 14>, <&dmac 15>; 693 dma-names = "tx", "rx"; 694 pinctrl-names = "default", "high_speed"; 695 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; 696 pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; 697 status = "disabled"; 698 }; 699 700 uart5: serial@ff5a0000 { 701 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 702 reg = <0x0 0xff5a0000 0x0 0x100>; 703 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 705 clock-names = "baudclk", "apb_pclk"; 706 reg-shift = <2>; 707 reg-io-width = <4>; 708 dmas = <&dmac 25>, <&dmac 26>; 709 dma-names = "tx", "rx"; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&uart5_xfer>; 712 status = "disabled"; 713 }; 714 715 uart6: serial@ff5b0000 { 716 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 717 reg = <0x0 0xff5b0000 0x0 0x100>; 718 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 720 clock-names = "baudclk", "apb_pclk"; 721 reg-shift = <2>; 722 reg-io-width = <4>; 723 dmas = <&dmac 27>, <&dmac 28>; 724 dma-names = "tx", "rx"; 725 pinctrl-names = "default"; 726 pinctrl-0 = <&uart6_xfer>; 727 status = "disabled"; 728 }; 729 730 uart7: serial@ff5c0000 { 731 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 732 reg = <0x0 0xff5c0000 0x0 0x100>; 733 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 735 clock-names = "baudclk", "apb_pclk"; 736 reg-shift = <2>; 737 reg-io-width = <4>; 738 dmas = <&dmac 29>, <&dmac 30>; 739 dma-names = "tx", "rx"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&uart7_xfer>; 742 status = "disabled"; 743 }; 744 745 vop_lite: vop@ffb00000 { 746 compatible = "rockchip,rk1808-vop-lit"; 747 reg = <0x0 0xffb00000 0x0 0x200>; 748 reg-names = "regs"; 749 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&cru ACLK_VOPLITE>, <&cru DCLK_VOPLITE>, 751 <&cru HCLK_VOPLITE>; 752 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 753 power-domains = <&power RK1808_PD_VIO>; 754 iommus = <&vopl_mmu>; 755 status = "disabled"; 756 757 vop_lite_out: port { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 vop_lite_out_dsi: endpoint@0 { 762 reg = <0>; 763 remote-endpoint = <&dsi_in_vop_lite>; 764 }; 765 766 vop_lite_out_rgb: endpoint@1 { 767 reg = <1>; 768 remote-endpoint = <&rgb_in_vop_lite>; 769 }; 770 }; 771 }; 772 773 vopl_mmu: iommu@ffb00f00 { 774 compatible = "rockchip,iommu"; 775 reg = <0x0 0xffb00f00 0x0 0x100>; 776 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "vopl_mmu"; 778 clocks = <&cru ACLK_VOPLITE>, <&cru HCLK_VOPLITE>; 779 clock-names = "aclk", "hclk"; 780 power-domains = <&power RK1808_PD_VIO>; 781 #iommu-cells = <0>; 782 status = "disabled"; 783 }; 784 785 vop_raw: vop@ffb40000 { 786 compatible = "rockchip,rk1808-vop-raw"; 787 reg = <0x0 0xffb40000 0x0 0x500>; 788 reg-names = "regs"; 789 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&cru ACLK_VOPRAW>, <&cru DCLK_VOPRAW>, 791 <&cru HCLK_VOPRAW>; 792 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 793 power-domains = <&power RK1808_PD_VIO>; 794 iommus = <&vopr_mmu>; 795 status = "disabled"; 796 797 vop_raw_out: port { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 vop_raw_out_csi: endpoint@0 { 802 reg = <0>; 803 remote-endpoint = <&csi_in_vop_raw>; 804 }; 805 }; 806 }; 807 808 vopr_mmu: iommu@ffb40f00 { 809 compatible = "rockchip,iommu"; 810 reg = <0x0 0xffb40f00 0x0 0x100>; 811 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 812 interrupt-names = "vopr_mmu"; 813 clocks = <&cru ACLK_VOPRAW>, <&cru HCLK_VOPRAW>; 814 clock-names = "aclk", "hclk"; 815 power-domains = <&power RK1808_PD_VIO>; 816 #iommu-cells = <0>; 817 status = "disabled"; 818 }; 819 820 pwm8: pwm@ff5d0000 { 821 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 822 reg = <0x0 0xff5d0000 0x0 0x10>; 823 #pwm-cells = <3>; 824 pinctrl-names = "active"; 825 pinctrl-0 = <&pwm8_pin>; 826 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 827 clock-names = "pwm", "pclk"; 828 status = "disabled"; 829 }; 830 831 pwm9: pwm@fff5d0010 { 832 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 833 reg = <0x0 0xff5d0010 0x0 0x10>; 834 #pwm-cells = <3>; 835 pinctrl-names = "active"; 836 pinctrl-0 = <&pwm9_pin>; 837 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 838 clock-names = "pwm", "pclk"; 839 status = "disabled"; 840 }; 841 842 pwm10: pwm@ff5d0020 { 843 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 844 reg = <0x0 0xff5d0020 0x0 0x10>; 845 #pwm-cells = <3>; 846 pinctrl-names = "active"; 847 pinctrl-0 = <&pwm10_pin>; 848 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 849 clock-names = "pwm", "pclk"; 850 status = "disabled"; 851 }; 852 853 pwm11: pwm@ff5d0030 { 854 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 855 reg = <0x0 0xff5d0030 0x0 0x10>; 856 #pwm-cells = <3>; 857 pinctrl-names = "active"; 858 pinctrl-0 = <&pwm11_pin>; 859 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 860 clock-names = "pwm", "pclk"; 861 status = "disabled"; 862 }; 863 864 i2s0: i2s@ff7e0000 { 865 compatible = "rockchip,rk1808-i2s-tdm"; 866 reg = <0x0 0xff7e0000 0x0 0x1000>; 867 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 869 clock-names = "mclk_tx", "mclk_rx", "hclk"; 870 dmas = <&dmac 16>, <&dmac 17>; 871 dma-names = "tx", "rx"; 872 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 873 reset-names = "tx-m", "rx-m"; 874 rockchip,cru = <&cru>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&i2s0_8ch_sclktx 877 &i2s0_8ch_sclkrx 878 &i2s0_8ch_lrcktx 879 &i2s0_8ch_lrckrx 880 &i2s0_8ch_sdi0 881 &i2s0_8ch_sdi1 882 &i2s0_8ch_sdi2 883 &i2s0_8ch_sdi3 884 &i2s0_8ch_sdo0 885 &i2s0_8ch_sdo1 886 &i2s0_8ch_sdo2 887 &i2s0_8ch_sdo3 888 &i2s0_8ch_mclk>; 889 status = "disabled"; 890 }; 891 892 i2s1: i2s@ff7f0000 { 893 compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s"; 894 reg = <0x0 0xff7f0000 0x0 0x1000>; 895 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 897 clock-names = "i2s_clk", "i2s_hclk"; 898 dmas = <&dmac 18>, <&dmac 19>; 899 dma-names = "tx", "rx"; 900 pinctrl-names = "default"; 901 pinctrl-0 = <&i2s1_2ch_sclk 902 &i2s1_2ch_lrck 903 &i2s1_2ch_sdi 904 &i2s1_2ch_sdo>; 905 status = "disabled"; 906 }; 907 908 pdm: pdm@ff800000 { 909 compatible = "rockchip,rk1808-pdm", "rockchip,pdm"; 910 reg = <0x0 0xff800000 0x0 0x1000>; 911 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 912 clock-names = "pdm_clk", "pdm_hclk"; 913 dmas = <&dmac 24>; 914 dma-names = "rx"; 915 resets = <&cru SRST_PDM>; 916 reset-names = "pdm-m"; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&pdm_clk 919 &pdm_clk1 920 &pdm_sdi0 921 &pdm_sdi1 922 &pdm_sdi2 923 &pdm_sdi3>; 924 status = "disabled"; 925 }; 926 927 vad: vad@ff810000 { 928 compatible = "rockchip,rk1808-vad"; 929 reg = <0x0 0xff810000 0x0 0x10000>; 930 reg-names = "vad"; 931 clocks = <&cru HCLK_VAD>; 932 clock-names = "hclk"; 933 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 934 rockchip,audio-sram = <&vad_sram>; 935 rockchip,audio-src = <0>; 936 rockchip,det-channel = <0>; 937 rockchip,mode = <1>; 938 status = "disabled"; 939 }; 940 941 csi_tx: csi@ffb20000 { 942 compatible = "rockchip,rk1808-mipi-csi"; 943 reg = <0x0 0xffb20000 0x0 0x500>; 944 reg-names = "csi_regs"; 945 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&cru PCLK_CSI_TX>, <&mipi_dphy>; 947 clock-names = "pclk", "hs_clk"; 948 resets = <&cru SRST_CSITX_P>; 949 reset-names = "apb"; 950 phys = <&mipi_dphy>; 951 phy-names = "mipi_dphy"; 952 power-domains = <&power RK1808_PD_VIO>; 953 rockchip,grf = <&grf>; 954 status = "disabled"; 955 956 ports { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 port { 961 csi_in_vop_raw: endpoint { 962 remote-endpoint = <&vop_raw_out_csi>; 963 }; 964 }; 965 }; 966 }; 967 968 dsi: dsi@ffb30000 { 969 compatible = "rockchip,rk1808-mipi-dsi"; 970 reg = <0x0 0xffb30000 0x0 0x500>; 971 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cru PCLK_DSI_TX>, <&mipi_dphy>; 973 clock-names = "pclk", "hs_clk"; 974 resets = <&cru SRST_MIPIDSI_HOST_P>; 975 reset-names = "apb"; 976 phys = <&mipi_dphy>; 977 phy-names = "mipi_dphy"; 978 power-domains = <&power RK1808_PD_VIO>; 979 rockchip,grf = <&grf>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 status = "disabled"; 983 984 ports { 985 port { 986 dsi_in_vop_lite: endpoint { 987 remote-endpoint = <&vop_lite_out_dsi>; 988 }; 989 }; 990 }; 991 }; 992 993 sfc: sfc@ffc50000 { 994 compatible = "rockchip,rksfc"; 995 reg = <0x0 0xffc50000 0x0 0x4000>; 996 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 998 clock-names = "clk_sfc", "hclk_sfc"; 999 status = "disabled"; 1000 }; 1001 1002 sdio: dwmmc@ffc60000 { 1003 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1004 reg = <0x0 0xffc60000 0x0 0x4000>; 1005 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1006 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1007 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1008 max-frequency = <150000000>; 1009 fifo-depth = <0x100>; 1010 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 1013 status = "disabled"; 1014 }; 1015 1016 npu: npu@ffbc0000 { 1017 compatible = "rockchip,npu"; 1018 reg = <0x0 0xffbc0000 0x0 0x1000>; 1019 clocks = <&cru SCLK_NPU>, <&cru HCLK_NPU>; 1020 clock-names = "sclk_npu", "hclk_npu"; 1021 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1022 status = "disabled"; 1023 }; 1024 1025 saradc: saradc@ff3c0000 { 1026 compatible = "rockchip,rk1808-saradc", "rockchip,rk3399-saradc"; 1027 reg = <0x0 0xff3c0000 0x0 0x100>; 1028 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1029 #io-channel-cells = <1>; 1030 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 1031 clock-names = "saradc", "apb_pclk"; 1032 resets = <&cru SRST_SARADC_P>; 1033 reset-names = "saradc-apb"; 1034 status = "disabled"; 1035 }; 1036 1037 sdmmc: dwmmc@ffcf0000 { 1038 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1039 reg = <0x0 0xffcf0000 0x0 0x4000>; 1040 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 1041 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1042 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1043 max-frequency = <150000000>; 1044 fifo-depth = <0x100>; 1045 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd>; 1048 status = "disabled"; 1049 }; 1050 1051 emmc: dwmmc@ffd00000 { 1052 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1053 reg = <0x0 0xffd00000 0x0 0x4000>; 1054 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1055 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1056 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1057 max-frequency = <150000000>; 1058 fifo-depth = <0x100>; 1059 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1060 status = "disabled"; 1061 }; 1062 1063 usb_host0_ehci: usb@ffd80000 { 1064 compatible = "generic-ehci"; 1065 reg = <0x0 0xffd80000 0x0 0x10000>; 1066 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1068 <&u2phy>; 1069 clock-names = "usbhost", "arbiter", "utmi"; 1070 phys = <&u2phy_host>; 1071 phy-names = "usb"; 1072 status = "disabled"; 1073 }; 1074 1075 usb_host0_ohci: usb@ffd90000 { 1076 compatible = "generic-ohci"; 1077 reg = <0x0 0xffd90000 0x0 0x10000>; 1078 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1080 <&u2phy>; 1081 clock-names = "usbhost", "arbiter", "utmi"; 1082 phys = <&u2phy_host>; 1083 phy-names = "usb"; 1084 status = "disabled"; 1085 }; 1086 1087 gmac: ethernet@ffdd0000 { 1088 compatible = "rockchip,rk1808-gmac"; 1089 reg = <0x0 0xffdd0000 0x0 0x10000>; 1090 rockchip,grf = <&grf>; 1091 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1092 interrupt-names = "macirq"; 1093 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 1094 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, 1095 <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, 1096 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; 1097 clock-names = "stmmaceth", "mac_clk_rx", 1098 "mac_clk_tx", "clk_mac_ref", 1099 "clk_mac_refout", "aclk_mac", 1100 "pclk_mac", "clk_mac_speed"; 1101 phy-mode = "rgmii"; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&rgmii_pins>; 1104 resets = <&cru SRST_GAMC_A>; 1105 reset-names = "stmmaceth"; 1106 /* power-domains = <&power RK1808_PD_GMAC>; */ 1107 status = "disabled"; 1108 }; 1109 1110 pinctrl: pinctrl { 1111 compatible = "rockchip,rk1808-pinctrl"; 1112 rockchip,grf = <&grf>; 1113 rockchip,pmu = <&pmugrf>; 1114 #address-cells = <2>; 1115 #size-cells = <2>; 1116 ranges; 1117 1118 gpio0: gpio0@ff4c0000 { 1119 compatible = "rockchip,gpio-bank"; 1120 reg = <0x0 0xff4c0000 0x0 0x100>; 1121 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; 1123 gpio-controller; 1124 #gpio-cells = <2>; 1125 1126 interrupt-controller; 1127 #interrupt-cells = <2>; 1128 }; 1129 1130 gpio1: gpio1@ff690000 { 1131 compatible = "rockchip,gpio-bank"; 1132 reg = <0x0 0xff690000 0x0 0x100>; 1133 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1135 gpio-controller; 1136 #gpio-cells = <2>; 1137 1138 interrupt-controller; 1139 #interrupt-cells = <2>; 1140 }; 1141 1142 gpio2: gpio2@ff6a0000 { 1143 compatible = "rockchip,gpio-bank"; 1144 reg = <0x0 0xff6a0000 0x0 0x100>; 1145 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1147 gpio-controller; 1148 #gpio-cells = <2>; 1149 1150 interrupt-controller; 1151 #interrupt-cells = <2>; 1152 }; 1153 1154 gpio3: gpio3@ff6b0000 { 1155 compatible = "rockchip,gpio-bank"; 1156 reg = <0x0 0xff6b0000 0x0 0x100>; 1157 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1159 gpio-controller; 1160 #gpio-cells = <2>; 1161 1162 interrupt-controller; 1163 #interrupt-cells = <2>; 1164 }; 1165 1166 gpio4: gpio4@ff6c0000 { 1167 compatible = "rockchip,gpio-bank"; 1168 reg = <0x0 0xff6c0000 0x0 0x100>; 1169 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1171 gpio-controller; 1172 #gpio-cells = <2>; 1173 1174 interrupt-controller; 1175 #interrupt-cells = <2>; 1176 }; 1177 1178 pcfg_pull_up: pcfg-pull-up { 1179 bias-pull-up; 1180 }; 1181 1182 pcfg_pull_down: pcfg-pull-down { 1183 bias-pull-down; 1184 }; 1185 1186 pcfg_pull_none: pcfg-pull-none { 1187 bias-disable; 1188 }; 1189 1190 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1191 bias-disable; 1192 drive-strength = <2>; 1193 }; 1194 1195 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1196 bias-pull-up; 1197 drive-strength = <2>; 1198 }; 1199 1200 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1201 bias-pull-up; 1202 drive-strength = <4>; 1203 }; 1204 1205 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1206 bias-disable; 1207 drive-strength = <4>; 1208 }; 1209 1210 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1211 bias-pull-down; 1212 drive-strength = <4>; 1213 }; 1214 1215 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1216 bias-disable; 1217 drive-strength = <8>; 1218 }; 1219 1220 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1221 bias-pull-up; 1222 drive-strength = <8>; 1223 }; 1224 1225 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1226 bias-disable; 1227 drive-strength = <12>; 1228 }; 1229 1230 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1231 bias-pull-up; 1232 drive-strength = <12>; 1233 }; 1234 1235 pcfg_pull_none_smt: pcfg-pull-none-smt { 1236 bias-disable; 1237 input-schmitt-enable; 1238 }; 1239 1240 pcfg_output_high: pcfg-output-high { 1241 output-high; 1242 }; 1243 1244 pcfg_output_low: pcfg-output-low { 1245 output-low; 1246 }; 1247 1248 pcfg_input_high: pcfg-input-high { 1249 bias-pull-up; 1250 input-enable; 1251 }; 1252 1253 pcfg_input: pcfg-input { 1254 input-enable; 1255 }; 1256 1257 emmc { 1258 emmc_clk: emmc-clk { 1259 rockchip,pins = 1260 /* emmc_clkout */ 1261 <1 RK_PB1 1 &pcfg_pull_none>; 1262 }; 1263 1264 emmc_rstnout: emmc-rstnout { 1265 rockchip,pins = 1266 /* emmc_rstn */ 1267 <1 RK_PB3 1 &pcfg_pull_none>; 1268 }; 1269 1270 emmc_bus8: emmc-bus8 { 1271 rockchip,pins = 1272 /* emmc_d0 */ 1273 <1 RK_PA0 1 &pcfg_pull_none>, 1274 /* emmc_d1 */ 1275 <1 RK_PA1 1 &pcfg_pull_none>, 1276 /* emmc_d2 */ 1277 <1 RK_PA2 1 &pcfg_pull_none>, 1278 /* emmc_d3 */ 1279 <1 RK_PA3 1 &pcfg_pull_none>, 1280 /* emmc_d4 */ 1281 <1 RK_PA4 1 &pcfg_pull_none>, 1282 /* emmc_d5 */ 1283 <1 RK_PA5 1 &pcfg_pull_none>, 1284 /* emmc_d6 */ 1285 <1 RK_PA6 1 &pcfg_pull_none>, 1286 /* emmc_d7 */ 1287 <1 RK_PA7 1 &pcfg_pull_none>; 1288 }; 1289 1290 emmc_pwren: emmc-pwren { 1291 rockchip,pins = 1292 <1 RK_PB0 1 &pcfg_pull_none>; 1293 }; 1294 1295 emmc_cmd: emmc-cmd { 1296 rockchip,pins = 1297 <1 RK_PB2 1 &pcfg_pull_none>; 1298 }; 1299 }; 1300 1301 gmac { 1302 rgmii_pins: rgmii-pins { 1303 rockchip,pins = 1304 /* rgmii_txen */ 1305 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 1306 /* rgmii_txd1 */ 1307 <2 RK_PA2 2 &pcfg_pull_none_12ma>, 1308 /* rgmii_txd0 */ 1309 <2 RK_PA3 2 &pcfg_pull_none_12ma>, 1310 /* rgmii_rxd0 */ 1311 <2 RK_PA4 2 &pcfg_pull_none>, 1312 /* rgmii_rxd1 */ 1313 <2 RK_PA5 2 &pcfg_pull_none>, 1314 /* rgmii_rxdv */ 1315 <2 RK_PA7 2 &pcfg_pull_none>, 1316 /* rgmii_mdio */ 1317 <2 RK_PB0 2 &pcfg_pull_none>, 1318 /* rgmii_mdc */ 1319 <2 RK_PB2 2 &pcfg_pull_none>, 1320 /* rgmii_txd3 */ 1321 <2 RK_PB3 2 &pcfg_pull_none_12ma>, 1322 /* rgmii_txd2 */ 1323 <2 RK_PB4 2 &pcfg_pull_none_12ma>, 1324 /* rgmii_rxd2 */ 1325 <2 RK_PB5 2 &pcfg_pull_none>, 1326 /* rgmii_rxd3 */ 1327 <2 RK_PB6 2 &pcfg_pull_none>, 1328 /* rgmii_clk */ 1329 <2 RK_PB7 2 &pcfg_pull_none>, 1330 /* rgmii_txclk */ 1331 <2 RK_PC1 2 &pcfg_pull_none_12ma>, 1332 /* rgmii_rxclk */ 1333 <2 RK_PC2 2 &pcfg_pull_none>; 1334 }; 1335 1336 rmii_pins: rmii-pins { 1337 rockchip,pins = 1338 /* rmii_txen */ 1339 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 1340 /* rmii_txd1 */ 1341 <2 RK_PA2 2 &pcfg_pull_none_12ma>, 1342 /* rmii_txd0 */ 1343 <2 RK_PA3 2 &pcfg_pull_none_12ma>, 1344 /* rmii_rxd0 */ 1345 <2 RK_PA4 2 &pcfg_pull_none>, 1346 /* rmii_rxd1 */ 1347 <2 RK_PA5 2 &pcfg_pull_none>, 1348 /* rmii_rxer */ 1349 <2 RK_PA6 2 &pcfg_pull_none>, 1350 /* rmii_rxdv */ 1351 <2 RK_PA7 2 &pcfg_pull_none>, 1352 /* rmii_mdio */ 1353 <2 RK_PB0 2 &pcfg_pull_none>, 1354 /* rmii_mdc */ 1355 <2 RK_PB2 2 &pcfg_pull_none>, 1356 /* rmii_clk */ 1357 <2 RK_PB7 2 &pcfg_pull_none>; 1358 }; 1359 }; 1360 1361 i2c0 { 1362 i2c0_xfer: i2c0-xfer { 1363 rockchip,pins = 1364 /* i2c0_sda */ 1365 <0 RK_PB1 1 &pcfg_pull_none_smt>, 1366 /* i2c0_scl */ 1367 <0 RK_PB0 1 &pcfg_pull_none_smt>; 1368 }; 1369 }; 1370 1371 i2c1 { 1372 i2c1_xfer: i2c1-xfer { 1373 rockchip,pins = 1374 /* i2c1_sda */ 1375 <0 RK_PC1 1 &pcfg_pull_none_smt>, 1376 /* i2c1_scl */ 1377 <0 RK_PC0 1 &pcfg_pull_none_smt>; 1378 }; 1379 }; 1380 1381 i2c2m0 { 1382 i2c2m0_xfer: i2c2m0-xfer { 1383 rockchip,pins = 1384 /* i2c2m0_sda */ 1385 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1386 /* i2c2m0_scl */ 1387 <3 RK_PB3 2 &pcfg_pull_none_smt>; 1388 }; 1389 }; 1390 1391 i2c3 { 1392 i2c3_xfer: i2c3-xfer { 1393 rockchip,pins = 1394 /* i2c3_sda */ 1395 <2 RK_PD1 1 &pcfg_pull_none_smt>, 1396 /* i2c3_scl */ 1397 <2 RK_PD0 1 &pcfg_pull_none_smt>; 1398 }; 1399 }; 1400 1401 i2c4 { 1402 i2c4_xfer: i2c4-xfer { 1403 rockchip,pins = 1404 /* i2c4_sda */ 1405 <3 RK_PC3 3 &pcfg_pull_none_smt>, 1406 /* i2c4_scl */ 1407 <3 RK_PC2 3 &pcfg_pull_none_smt>; 1408 }; 1409 }; 1410 1411 i2c5 { 1412 i2c5_xfer: i2c5-xfer { 1413 rockchip,pins = 1414 /* i2c5_sda */ 1415 <4 RK_PC2 1 &pcfg_pull_none_smt>, 1416 /* i2c5_scl */ 1417 <4 RK_PC1 1 &pcfg_pull_none_smt>; 1418 }; 1419 }; 1420 1421 i2s1 { 1422 i2s1_2ch_lrck: i2s1-2ch-lrck { 1423 rockchip,pins = 1424 <3 RK_PA0 1 &pcfg_pull_none>; 1425 }; 1426 i2s1_2ch_sclk: i2s1-2ch-sclk { 1427 rockchip,pins = 1428 <3 RK_PA1 1 &pcfg_pull_none>; 1429 }; 1430 i2s1_2ch_mclk: i2s1-2ch-mclk { 1431 rockchip,pins = 1432 <3 RK_PA2 1 &pcfg_pull_none>; 1433 }; 1434 i2s1_2ch_sdo: i2s1-2ch-sdo { 1435 rockchip,pins = 1436 <3 RK_PA3 1 &pcfg_pull_none>; 1437 }; 1438 i2s1_2ch_sdi: i2s1-2ch-sdi { 1439 rockchip,pins = 1440 <3 RK_PA4 1 &pcfg_pull_none>; 1441 }; 1442 }; 1443 1444 i2s0 { 1445 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1446 rockchip,pins = 1447 <3 RK_PA5 1 &pcfg_pull_none>; 1448 }; 1449 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1450 rockchip,pins = 1451 <3 RK_PA6 1 &pcfg_pull_none>; 1452 }; 1453 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1454 rockchip,pins = 1455 <3 RK_PA7 1 &pcfg_pull_none>; 1456 }; 1457 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1458 rockchip,pins = 1459 <3 RK_PB0 1 &pcfg_pull_none>; 1460 }; 1461 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1462 rockchip,pins = 1463 <3 RK_PB1 1 &pcfg_pull_none>; 1464 }; 1465 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1466 rockchip,pins = 1467 <3 RK_PB2 1 &pcfg_pull_none>; 1468 }; 1469 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1470 rockchip,pins = 1471 <3 RK_PB3 1 &pcfg_pull_none>; 1472 }; 1473 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1474 rockchip,pins = 1475 <3 RK_PB4 1 &pcfg_pull_none>; 1476 }; 1477 i2s0_8ch_mclk: i2s0-8ch-mclk { 1478 rockchip,pins = 1479 <3 RK_PB5 1 &pcfg_pull_none>; 1480 }; 1481 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1482 rockchip,pins = 1483 <3 RK_PB6 1 &pcfg_pull_none>; 1484 }; 1485 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1486 rockchip,pins = 1487 <3 RK_PB7 1 &pcfg_pull_none>; 1488 }; 1489 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1490 rockchip,pins = 1491 <3 RK_PC0 1 &pcfg_pull_none>; 1492 }; 1493 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1494 rockchip,pins = 1495 <3 RK_PC1 1 &pcfg_pull_none>; 1496 }; 1497 }; 1498 1499 lcdc { 1500 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1501 rockchip,pins = 1502 /* lcdc_clkm0 */ 1503 <2 RK_PC6 3 &pcfg_pull_none>; 1504 }; 1505 1506 lcdc_rgb_den_pin: lcdc-rgb-den-pin { 1507 rockchip,pins = 1508 /* lcdc_denm0 */ 1509 <2 RK_PC7 3 &pcfg_pull_none>; 1510 }; 1511 1512 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1513 rockchip,pins = 1514 /* lcdc_hsyncm0 */ 1515 <2 RK_PB2 3 &pcfg_pull_none>; 1516 }; 1517 1518 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1519 rockchip,pins = 1520 /* lcdc_vsyncm0 */ 1521 <2 RK_PB3 3 &pcfg_pull_none>; 1522 }; 1523 1524 lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin { 1525 rockchip,pins = 1526 /* lcdc_hsyncm1 */ 1527 <3 RK_PB2 3 &pcfg_pull_none>; 1528 }; 1529 1530 lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin { 1531 rockchip,pins = 1532 /* lcdc_vsyncm1 */ 1533 <3 RK_PB3 3 &pcfg_pull_none>; 1534 }; 1535 1536 lcdc_rgb666_data_pins: lcdc-rgb666-data-pins { 1537 rockchip,pins = 1538 /* lcdc_d0m0 */ 1539 <2 RK_PA2 3 &pcfg_pull_none>, 1540 /* lcdc_d1m0 */ 1541 <2 RK_PA3 3 &pcfg_pull_none>, 1542 /* lcdc_d2m0 */ 1543 <2 RK_PC2 3 &pcfg_pull_none>, 1544 /* lcdc_d3m0 */ 1545 <2 RK_PC3 3 &pcfg_pull_none>, 1546 /* lcdc_d4m0 */ 1547 <2 RK_PC4 3 &pcfg_pull_none>, 1548 /* lcdc_d5m0 */ 1549 <2 RK_PC5 3 &pcfg_pull_none>, 1550 /* lcdc_d6m0 */ 1551 <2 RK_PA0 3 &pcfg_pull_none>, 1552 /* lcdc_d7m0 */ 1553 <2 RK_PA1 3 &pcfg_pull_none>, 1554 /* lcdc_d8 */ 1555 <3 RK_PC2 1 &pcfg_pull_none>, 1556 /* lcdc_d9 */ 1557 <3 RK_PC3 1 &pcfg_pull_none>, 1558 /* lcdc_d10 */ 1559 <3 RK_PC4 1 &pcfg_pull_none>, 1560 /* lcdc_d11 */ 1561 <3 RK_PC5 1 &pcfg_pull_none>, 1562 /* lcdc_d12 */ 1563 <3 RK_PC6 1 &pcfg_pull_none>, 1564 /* lcdc_d13 */ 1565 <3 RK_PC7 1 &pcfg_pull_none>, 1566 /* lcdc_d14 */ 1567 <3 RK_PD0 1 &pcfg_pull_none>, 1568 /* lcdc_d15 */ 1569 <3 RK_PD1 1 &pcfg_pull_none>, 1570 /* lcdc_d16 */ 1571 <3 RK_PD2 1 &pcfg_pull_none>, 1572 /* lcdc_d17 */ 1573 <3 RK_PD3 1 &pcfg_pull_none>; 1574 }; 1575 1576 lcdc_rgb565_data_pins: lcdc-rgb565-data-pins { 1577 rockchip,pins = 1578 /* lcdc_d0m0 */ 1579 <2 RK_PA2 3 &pcfg_pull_none>, 1580 /* lcdc_d1m0 */ 1581 <2 RK_PA3 3 &pcfg_pull_none>, 1582 /* lcdc_d2m0 */ 1583 <2 RK_PC2 3 &pcfg_pull_none>, 1584 /* lcdc_d3m0 */ 1585 <2 RK_PC3 3 &pcfg_pull_none>, 1586 /* lcdc_d4m0 */ 1587 <2 RK_PC4 3 &pcfg_pull_none>, 1588 /* lcdc_d5m0 */ 1589 <2 RK_PC5 3 &pcfg_pull_none>, 1590 /* lcdc_d6m0 */ 1591 <2 RK_PA0 3 &pcfg_pull_none>, 1592 /* lcdc_d7m0 */ 1593 <2 RK_PA1 3 &pcfg_pull_none>, 1594 /* lcdc_d8 */ 1595 <3 RK_PC2 1 &pcfg_pull_none>, 1596 /* lcdc_d9 */ 1597 <3 RK_PC3 1 &pcfg_pull_none>, 1598 /* lcdc_d10 */ 1599 <3 RK_PC4 1 &pcfg_pull_none>, 1600 /* lcdc_d11 */ 1601 <3 RK_PC5 1 &pcfg_pull_none>, 1602 /* lcdc_d12 */ 1603 <3 RK_PC6 1 &pcfg_pull_none>, 1604 /* lcdc_d13 */ 1605 <3 RK_PC7 1 &pcfg_pull_none>, 1606 /* lcdc_d14 */ 1607 <3 RK_PD0 1 &pcfg_pull_none>, 1608 /* lcdc_d15 */ 1609 <3 RK_PD1 1 &pcfg_pull_none>; 1610 }; 1611 }; 1612 1613 pciusb { 1614 pciusb_pins: pciusb-pins { 1615 rockchip,pins = 1616 /* pciusb_debug0 */ 1617 <4 RK_PB4 3 &pcfg_pull_none>, 1618 /* pciusb_debug1 */ 1619 <4 RK_PB5 3 &pcfg_pull_none>, 1620 /* pciusb_debug2 */ 1621 <4 RK_PB6 3 &pcfg_pull_none>, 1622 /* pciusb_debug3 */ 1623 <4 RK_PB7 3 &pcfg_pull_none>, 1624 /* pciusb_debug4 */ 1625 <4 RK_PC0 3 &pcfg_pull_none>, 1626 /* pciusb_debug5 */ 1627 <4 RK_PC1 3 &pcfg_pull_none>, 1628 /* pciusb_debug6 */ 1629 <4 RK_PC2 3 &pcfg_pull_none>, 1630 /* pciusb_debug7 */ 1631 <4 RK_PC3 3 &pcfg_pull_none>; 1632 }; 1633 }; 1634 1635 pdm { 1636 pdm_clk: pdm-clk { 1637 rockchip,pins = 1638 /* pdm_clk0 */ 1639 <3 RK_PB0 2 &pcfg_pull_none>; 1640 }; 1641 1642 pdm_sdi3: pdm-sdi3 { 1643 rockchip,pins = 1644 <3 RK_PA5 2 &pcfg_pull_none>; 1645 }; 1646 1647 pdm_sdi2: pdm-sdi2 { 1648 rockchip,pins = 1649 <3 RK_PA6 2 &pcfg_pull_none>; 1650 }; 1651 1652 pdm_sdi1: pdm-sdi1 { 1653 rockchip,pins = 1654 <3 RK_PA7 2 &pcfg_pull_none>; 1655 }; 1656 1657 pdm_clk1: pdm-clk1 { 1658 rockchip,pins = 1659 <3 RK_PB1 2 &pcfg_pull_none>; 1660 }; 1661 1662 pdm_sdi0: pdm-sdi0 { 1663 rockchip,pins = 1664 <3 RK_PC1 2 &pcfg_pull_none>; 1665 }; 1666 }; 1667 1668 pwm0 { 1669 pwm0_pin: pwm0-pin { 1670 rockchip,pins = 1671 <0 RK_PB7 1 &pcfg_pull_none>; 1672 }; 1673 }; 1674 1675 pwm1 { 1676 pwm1_pin: pwm1-pin { 1677 rockchip,pins = 1678 <0 RK_PC3 1 &pcfg_pull_none>; 1679 }; 1680 }; 1681 1682 pwm2 { 1683 pwm2_pin: pwm2-pin { 1684 rockchip,pins = 1685 <0 RK_PC5 1 &pcfg_pull_none>; 1686 }; 1687 }; 1688 1689 pwm3 { 1690 pwm3_pin: pwm3-pin { 1691 rockchip,pins = 1692 <0 RK_PC4 1 &pcfg_pull_none>; 1693 }; 1694 }; 1695 1696 pwm4 { 1697 pwm4_pin: pwm4-pin { 1698 rockchip,pins = 1699 <1 RK_PB6 2 &pcfg_pull_none>; 1700 }; 1701 }; 1702 1703 pwm5 { 1704 pwm5_pin: pwm5-pin { 1705 rockchip,pins = 1706 <1 RK_PB7 2 &pcfg_pull_none>; 1707 }; 1708 }; 1709 pwm6 { 1710 pwm6_pin: pwm6-pin { 1711 rockchip,pins = 1712 <3 RK_PA1 2 &pcfg_pull_none>; 1713 }; 1714 }; 1715 1716 pwm7 { 1717 pwm7_pin: pwm7-pin { 1718 rockchip,pins = 1719 <3 RK_PA2 2 &pcfg_pull_none>; 1720 }; 1721 }; 1722 1723 pwm8 { 1724 pwm8_pin: pwm8-pin { 1725 rockchip,pins = 1726 <3 RK_PD0 2 &pcfg_pull_none>; 1727 }; 1728 }; 1729 1730 pwm9 { 1731 pwm9_pin: pwm9-pin { 1732 rockchip,pins = 1733 <3 RK_PD1 2 &pcfg_pull_none>; 1734 }; 1735 }; 1736 1737 pwm10 { 1738 pwm10_pin: pwm10-pin { 1739 rockchip,pins = 1740 <3 RK_PD2 2 &pcfg_pull_none>; 1741 }; 1742 }; 1743 1744 pwm11 { 1745 pwm11_pin: pwm11-pin { 1746 rockchip,pins = 1747 <3 RK_PD3 2 &pcfg_pull_none>; 1748 }; 1749 }; 1750 1751 sdmmc0 { 1752 sdmmc0_bus4: sdmmc0-bus4 { 1753 rockchip,pins = 1754 /* sdmmc0_d0 */ 1755 <4 RK_PA2 1 &pcfg_pull_none>, 1756 /* sdmmc0_d1 */ 1757 <4 RK_PA3 1 &pcfg_pull_none>, 1758 /* sdmmc0_d2 */ 1759 <4 RK_PA4 1 &pcfg_pull_none>, 1760 /* sdmmc0_d3 */ 1761 <4 RK_PA5 1 &pcfg_pull_none>; 1762 }; 1763 sdmmc0_cmd: sdmmc0-cmd { 1764 rockchip,pins = 1765 <4 RK_PA0 1 &pcfg_pull_none>; 1766 }; 1767 sdmmc0_clk: sdmmc0-clk { 1768 rockchip,pins = 1769 <4 RK_PA1 1 &pcfg_pull_none>; 1770 }; 1771 }; 1772 1773 sdmmc1 { 1774 sdmmc1_bus4: sdmmc1-bus4 { 1775 rockchip,pins = 1776 /* sdmmc1_d0 */ 1777 <4 RK_PB0 1 &pcfg_pull_none>, 1778 /* sdmmc1_d1 */ 1779 <4 RK_PB1 1 &pcfg_pull_none>, 1780 /* sdmmc1_d2 */ 1781 <4 RK_PB2 1 &pcfg_pull_none>, 1782 /* sdmmc1_d3 */ 1783 <4 RK_PB3 1 &pcfg_pull_none>; 1784 }; 1785 1786 sdmmc1_cmd: sdmmc1-cmd { 1787 rockchip,pins = 1788 <4 RK_PA6 1 &pcfg_pull_none>; 1789 }; 1790 1791 sdmmc1_clk: sdmmc1-clk { 1792 rockchip,pins = 1793 <4 RK_PA7 1 &pcfg_pull_none>; 1794 }; 1795 }; 1796 1797 spi0 { 1798 spi0_mosi: spi0-mosi { 1799 rockchip,pins = 1800 <1 RK_PB4 1 &pcfg_pull_up_4ma>; 1801 }; 1802 1803 spi0_miso: spi0-miso { 1804 rockchip,pins = 1805 <1 RK_PB5 1 &pcfg_pull_up_4ma>; 1806 }; 1807 1808 spi0_csn: spi0-csn { 1809 rockchip,pins = 1810 <1 RK_PB6 1 &pcfg_pull_up_4ma>; 1811 }; 1812 1813 spi0_clk: spi0-clk { 1814 rockchip,pins = 1815 <1 RK_PB7 1 &pcfg_pull_up_4ma>; 1816 }; 1817 1818 spi0_mosi_hs: spi0-mosi-hs { 1819 rockchip,pins = 1820 <1 RK_PB4 1 &pcfg_pull_up_8ma>; 1821 }; 1822 1823 spi0_miso_hs: spi0-miso-hs { 1824 rockchip,pins = 1825 <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1826 }; 1827 1828 spi0_csn_hs: spi0-csn-hs { 1829 rockchip,pins = 1830 <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1831 }; 1832 1833 spi0_clk_hs: spi0-clk-hs { 1834 rockchip,pins = 1835 <1 RK_PB7 1 &pcfg_pull_up_8ma>; 1836 }; 1837 }; 1838 1839 spi1 { 1840 spi1_clk: spi1-clk { 1841 rockchip,pins = 1842 <4 RK_PB4 2 &pcfg_pull_up_4ma>; 1843 }; 1844 1845 spi1_mosi: spi1-mosi { 1846 rockchip,pins = 1847 <4 RK_PB5 2 &pcfg_pull_up_4ma>; 1848 }; 1849 1850 spi1_csn0: spi1-csn0 { 1851 rockchip,pins = 1852 <4 RK_PB6 2 &pcfg_pull_up_4ma>; 1853 }; 1854 1855 spi1_miso: spi1-miso { 1856 rockchip,pins = 1857 <4 RK_PB7 2 &pcfg_pull_up_4ma>; 1858 }; 1859 1860 spi1_csn1: spi1-csn1 { 1861 rockchip,pins = 1862 <4 RK_PC0 2 &pcfg_pull_up_4ma>; 1863 }; 1864 1865 spi1_clk_hs: spi1-clk-hs { 1866 rockchip,pins = 1867 <4 RK_PB4 2 &pcfg_pull_up_8ma>; 1868 }; 1869 1870 spi1_mosi_hs: spi1-mosi-hs { 1871 rockchip,pins = 1872 <4 RK_PB5 2 &pcfg_pull_up_8ma>; 1873 }; 1874 1875 spi1_csn0_hs: spi1-csn0-hs { 1876 rockchip,pins = 1877 <4 RK_PB6 2 &pcfg_pull_up_8ma>; 1878 }; 1879 1880 spi1_miso_hs: spi1-miso-hs { 1881 rockchip,pins = 1882 <4 RK_PB7 2 &pcfg_pull_up_8ma>; 1883 }; 1884 1885 spi1_csn1_hs: spi1-csn1-hs { 1886 rockchip,pins = 1887 <4 RK_PC0 2 &pcfg_pull_up_8ma>; 1888 }; 1889 }; 1890 1891 spi1m1 { 1892 spi1m1_clk: spi1m1-clk { 1893 rockchip,pins = 1894 <3 RK_PC7 3 &pcfg_pull_up_4ma>; 1895 }; 1896 1897 spi1m1_mosi: spi1m1-mosi { 1898 rockchip,pins = 1899 <3 RK_PD0 3 &pcfg_pull_up_4ma>; 1900 }; 1901 1902 spi1m1_csn0: spi1m1-csn0 { 1903 rockchip,pins = 1904 <3 RK_PD1 3 &pcfg_pull_up_4ma>; 1905 }; 1906 1907 spi1m1_miso: spi1m1-miso { 1908 rockchip,pins = 1909 <3 RK_PD2 3 &pcfg_pull_up_4ma>; 1910 }; 1911 1912 spi1m1_csn1: spi1m1-csn1 { 1913 rockchip,pins = 1914 <3 RK_PD3 3 &pcfg_pull_up_4ma>; 1915 }; 1916 1917 spi1m1_clk_hs: spi1m1-clk-hs { 1918 rockchip,pins = 1919 <3 RK_PC7 3 &pcfg_pull_up_8ma>; 1920 }; 1921 1922 spi1m1_mosi_hs: spi1m1-mosi-hs { 1923 rockchip,pins = 1924 <3 RK_PD0 3 &pcfg_pull_up_8ma>; 1925 }; 1926 1927 spi1m1_csn0_hs: spi1m1-csn0-hs { 1928 rockchip,pins = 1929 <3 RK_PD1 3 &pcfg_pull_up_8ma>; 1930 }; 1931 1932 spi1m1_miso_hs: spi1m1-miso-hs { 1933 rockchip,pins = 1934 <3 RK_PD2 3 &pcfg_pull_up_8ma>; 1935 }; 1936 1937 spi1m1_csn1_hs: spi1m1-csn1-hs { 1938 rockchip,pins = 1939 <3 RK_PD3 3 &pcfg_pull_up_8ma>; 1940 }; 1941 }; 1942 1943 spi2m0 { 1944 spi2m0_miso: spi2m0-miso { 1945 rockchip,pins = 1946 <1 RK_PA6 2 &pcfg_pull_up_4ma>; 1947 }; 1948 1949 spi2m0_clk: spi2m0-clk { 1950 rockchip,pins = 1951 <1 RK_PA7 2 &pcfg_pull_up_4ma>; 1952 }; 1953 1954 spi2m0_mosi: spi2m0-mosi { 1955 rockchip,pins = 1956 <1 RK_PB0 2 &pcfg_pull_up_4ma>; 1957 }; 1958 1959 spi2m0_csn: spi2m0-csn { 1960 rockchip,pins = 1961 <1 RK_PB1 2 &pcfg_pull_up_4ma>; 1962 }; 1963 1964 spi2m0_miso_hs: spi2m0-miso-hs { 1965 rockchip,pins = 1966 <1 RK_PA6 2 &pcfg_pull_none>; 1967 }; 1968 1969 spi2m0_clk_hs: spi2m0-clk-hs { 1970 rockchip,pins = 1971 <1 RK_PA7 2 &pcfg_pull_none>; 1972 }; 1973 1974 spi2m0_mosi_hs: spi2m0-mosi-hs { 1975 rockchip,pins = 1976 <1 RK_PB0 2 &pcfg_pull_none>; 1977 }; 1978 1979 spi2m0_csn_hs: spi2m0-csn-hs { 1980 rockchip,pins = 1981 <1 RK_PB1 2 &pcfg_pull_none>; 1982 }; 1983 }; 1984 1985 spi2m1 { 1986 spi2m1_miso: spi2m1-miso { 1987 rockchip,pins = 1988 <2 RK_PA4 3 &pcfg_pull_up_4ma>; 1989 }; 1990 1991 spi2m1_clk: spi2m1-clk { 1992 rockchip,pins = 1993 <2 RK_PA5 3 &pcfg_pull_up_4ma>; 1994 }; 1995 1996 spi2m1_mosi: spi2m1-mosi { 1997 rockchip,pins = 1998 <2 RK_PA6 3 &pcfg_pull_up_4ma>; 1999 }; 2000 2001 spi2m1_csn: spi2m1-csn { 2002 rockchip,pins = 2003 <2 RK_PA7 3 &pcfg_pull_up_4ma>; 2004 }; 2005 2006 spi2m1_miso_hs: spi2m1-miso-hs { 2007 rockchip,pins = 2008 <2 RK_PA4 3 &pcfg_pull_up_8ma>; 2009 }; 2010 2011 spi2m1_clk_hs: spi2m1-clk-hs { 2012 rockchip,pins = 2013 <2 RK_PA5 3 &pcfg_pull_up_8ma>; 2014 }; 2015 2016 spi2m1_mosi_hs: spi2m1-mosi-hs { 2017 rockchip,pins = 2018 <2 RK_PA6 3 &pcfg_pull_up_8ma>; 2019 }; 2020 2021 spi2m1_csn_hs: spi2m1-csn-hs { 2022 rockchip,pins = 2023 <2 RK_PA7 3 &pcfg_pull_up_8ma>; 2024 }; 2025 }; 2026 2027 uart0 { 2028 uart0_xfer: uart0-xfer { 2029 rockchip,pins = 2030 /* uart0_rx */ 2031 <0 RK_PB3 1 &pcfg_pull_none>, 2032 /* uart0_tx */ 2033 <0 RK_PB2 1 &pcfg_pull_none>; 2034 }; 2035 2036 uart0_cts: uart0-cts { 2037 rockchip,pins = 2038 <0 RK_PB4 1 &pcfg_pull_none>; 2039 }; 2040 2041 uart0_rts: uart0-rts { 2042 rockchip,pins = 2043 <0 RK_PB5 1 &pcfg_pull_none>; 2044 }; 2045 }; 2046 2047 uart1 { 2048 uart1m0_xfer: uart1m0-xfer { 2049 rockchip,pins = 2050 /* uart1_rxm0 */ 2051 <4 RK_PB0 2 &pcfg_pull_none>, 2052 /* uart1_txm0 */ 2053 <4 RK_PB1 2 &pcfg_pull_none>; 2054 }; 2055 2056 uart1m1_xfer: uart1m1-xfer { 2057 rockchip,pins = 2058 /* uart1_rxm1 */ 2059 <1 RK_PB4 3 &pcfg_pull_none>, 2060 /* uart1_txm1 */ 2061 <1 RK_PB5 3 &pcfg_pull_none>; 2062 }; 2063 2064 uart1_cts: uart1-cts { 2065 rockchip,pins = 2066 <4 RK_PB2 2 &pcfg_pull_none>; 2067 }; 2068 2069 uart1_rts: uart1-rts { 2070 rockchip,pins = 2071 <4 RK_PB3 2 &pcfg_pull_none>; 2072 }; 2073 }; 2074 2075 uart2 { 2076 uart2m0_xfer: uart2m0-xfer { 2077 rockchip,pins = 2078 /* uart2_rxm0 */ 2079 <4 RK_PA3 2 &pcfg_pull_none>, 2080 /* uart2_txm0 */ 2081 <4 RK_PA2 2 &pcfg_pull_none>; 2082 }; 2083 2084 uart2m1_xfer: uart2m1-xfer { 2085 rockchip,pins = 2086 /* uart2_rxm1 */ 2087 <2 RK_PD1 2 &pcfg_pull_none>, 2088 /* uart2_txm1 */ 2089 <2 RK_PD0 2 &pcfg_pull_none>; 2090 }; 2091 2092 uart2m2_xfer: uart2m2-xfer { 2093 rockchip,pins = 2094 /* uart2_rxm2 */ 2095 <3 RK_PA4 2 &pcfg_pull_none>, 2096 /* uart2_txm2 */ 2097 <3 RK_PA3 2 &pcfg_pull_none>; 2098 }; 2099 }; 2100 2101 uart3 { 2102 uart3m0_xfer: uart3m0-xfer { 2103 rockchip,pins = 2104 /* uart3_rxm0 */ 2105 <0 RK_PC5 2 &pcfg_pull_none>, 2106 /* uart3_txm0 */ 2107 <0 RK_PC4 2 &pcfg_pull_none>; 2108 }; 2109 2110 uart3_ctsm0: uart3-ctsm0 { 2111 rockchip,pins = 2112 <0 RK_PC7 2 &pcfg_pull_none>; 2113 }; 2114 2115 uart3_rtsm0: uart3-rtsm0 { 2116 rockchip,pins = 2117 <0 RK_PD0 2 &pcfg_pull_none>; 2118 }; 2119 }; 2120 2121 uart4 { 2122 uart4_xfer: uart4-xfer { 2123 rockchip,pins = 2124 /* uart4_rx */ 2125 <4 RK_PB4 1 &pcfg_pull_none>, 2126 /* uart4_tx */ 2127 <4 RK_PB5 1 &pcfg_pull_none>; 2128 }; 2129 2130 uart4_cts: uart4-cts { 2131 rockchip,pins = 2132 <4 RK_PB6 1 &pcfg_pull_none>; 2133 }; 2134 2135 uart4_rts: uart4-rts { 2136 rockchip,pins = 2137 <4 RK_PB7 1 &pcfg_pull_none>; 2138 }; 2139 }; 2140 2141 uart5 { 2142 uart5_xfer: uart5-xfer { 2143 rockchip,pins = 2144 /* uart5_rx */ 2145 <3 RK_PC3 1 &pcfg_pull_none>, 2146 /* uart5_tx */ 2147 <3 RK_PC2 1 &pcfg_pull_none>; 2148 }; 2149 }; 2150 2151 uart6 { 2152 uart6_xfer: uart6-xfer { 2153 rockchip,pins = 2154 /* uart6_rx */ 2155 <3 RK_PC5 1 &pcfg_pull_none>, 2156 /* uart6_tx */ 2157 <3 RK_PC4 1 &pcfg_pull_none>; 2158 }; 2159 }; 2160 2161 uart7 { 2162 uart7_xfer: uart7-xfer { 2163 rockchip,pins = 2164 /* uart7_rx */ 2165 <3 RK_PC7 1 &pcfg_pull_none>, 2166 /* uart7_tx */ 2167 <3 RK_PC6 1 &pcfg_pull_none>; 2168 }; 2169 }; 2170 2171 tsadc { 2172 tsadc_otp_gpio: tsadc-otp-gpio { 2173 rockchip,pins = 2174 <0 RK_PA6 0 &pcfg_pull_none>; 2175 }; 2176 2177 tsadc_otp_out: tsadc-otp-out { 2178 rockchip,pins = 2179 <0 RK_PA6 2 &pcfg_pull_none>; 2180 }; 2181 }; 2182 }; 2183}; 2184