1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 3 4#include <dt-bindings/clock/rk1808-cru.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8#include <dt-bindings/power/rk1808-power.h> 9 10/ { 11 compatible = "rockchip,rk1808"; 12 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 serial4 = &uart4; 29 serial5 = &uart5; 30 serial6 = &uart6; 31 serial7 = &uart7; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35", "arm,armv8"; 44 reg = <0x0 0x0>; 45 clocks = <&cru ARMCLK>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a35", "arm,armv8"; 51 reg = <0x0 0x1>; 52 clocks = <&cru ARMCLK>; 53 }; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>; 61 }; 62 63 dmc: dmc { 64 compatible = "rockchip,rk1808-dmc"; 65 }; 66 67 gmac_clkin: external-gmac-clock { 68 compatible = "fixed-clock"; 69 clock-frequency = <125000000>; 70 clock-output-names = "gmac_clkin"; 71 #clock-cells = <0>; 72 }; 73 74 timer { 75 compatible = "arm,armv8-timer"; 76 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 77 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 78 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 79 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 80 arm,no-tick-in-suspend; 81 }; 82 83 xin24m: xin24m { 84 compatible = "fixed-clock"; 85 clock-frequency = <24000000>; 86 clock-output-names = "xin24m"; 87 #clock-cells = <0>; 88 }; 89 90 xin32k: xin32k { 91 compatible = "fixed-clock"; 92 clock-frequency = <32768>; 93 clock-output-names = "xin32k"; 94 #clock-cells = <0>; 95 }; 96 97 usbdrd3: usb { 98 compatible = "rockchip,rk1808-dwc3"; 99 clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, 100 <&cru SCLK_USB3_OTG0_SUSPEND>; 101 clock-names = "ref_clk", "bus_clk", 102 "suspend_clk"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 status = "disabled"; 107 108 usbdrd_dwc3: dwc3@fd000000 { 109 compatible = "snps,dwc3"; 110 reg = <0x0 0xfd000000 0x0 0x200000>; 111 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 112 dr_mode = "otg"; 113 phys = <&u2phy_otg>; 114 phy-names = "usb2-phy"; 115 phy_type = "utmi_wide"; 116 snps,dis_enblslpm_quirk; 117 snps,dis-u2-freeclk-exists-quirk; 118 snps,dis_u2_susphy_quirk; 119 snps,dis-del-phy-power-chg-quirk; 120 snps,tx-ipgap-linecheck-dis-quirk; 121 status = "disabled"; 122 }; 123 }; 124 125 grf: syscon@fe000000 { 126 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; 127 reg = <0x0 0xfe000000 0x0 0x1000>; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 131 io_domains: io-domains { 132 compatible = "rockchip,rk1808-io-voltage-domain"; 133 status = "disabled"; 134 }; 135 136 rgb: rgb { 137 compatible = "rockchip,rk1808-rgb"; 138 status = "disabled"; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 port@0 { 145 reg = <0>; 146 147 rgb_in_vop_lite: endpoint { 148 remote-endpoint = <&vop_lite_out_rgb>; 149 }; 150 }; 151 }; 152 }; 153 }; 154 155 usb2phy_grf: syscon@fe010000 { 156 compatible = "rockchip,rk1808-usb2phy-grf", "syscon", 157 "simple-mfd"; 158 reg = <0x0 0xfe010000 0x0 0x8000>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 162 u2phy: usb2-phy@100 { 163 compatible = "rockchip,rk1808-usb2phy"; 164 reg = <0x100 0x10>; 165 clocks = <&cru SCLK_USBPHY_REF>; 166 clock-names = "phyclk"; 167 #clock-cells = <0>; 168 assigned-clocks = <&cru USB480M>; 169 assigned-clock-parents = <&u2phy>; 170 clock-output-names = "usb480m_phy"; 171 status = "disabled"; 172 173 u2phy_host: host-port { 174 #phy-cells = <0>; 175 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "linestate"; 177 status = "disabled"; 178 }; 179 180 u2phy_otg: otg-port { 181 #phy-cells = <0>; 182 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "otg-bvalid", "otg-id", 186 "linestate"; 187 status = "disabled"; 188 }; 189 }; 190 }; 191 192 pmugrf: syscon@fe020000 { 193 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; 194 reg = <0x0 0xfe020000 0x0 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 198 pmu_io_domains: io-domains { 199 compatible = "rockchip,rk1808-pmu-io-voltage-domain"; 200 status = "disabled"; 201 }; 202 }; 203 204 qos_npu: qos@fe850000 { 205 compatible = "syscon"; 206 reg = <0x0 0xfe850000 0x0 0x20>; 207 }; 208 209 qos_pcie: qos@fe880000 { 210 compatible = "syscon"; 211 reg = <0x0 0xfe880000 0x0 0x20>; 212 }; 213 214 qos_isp: qos@fe8a0000 { 215 compatible = "syscon"; 216 reg = <0x0 0xfe8a0000 0x0 0x20>; 217 }; 218 219 qos_rga_rd: qos@fe8a0080 { 220 compatible = "syscon"; 221 reg = <0x0 0xfe8a0080 0x0 0x20>; 222 }; 223 224 qos_rga_wr: qos@fe8a0100 { 225 compatible = "syscon"; 226 reg = <0x0 0xfe8a0100 0x0 0x20>; 227 }; 228 229 qos_vip: qos@fe8a0180 { 230 compatible = "syscon"; 231 reg = <0x0 0xfe8a0180 0x0 0x20>; 232 }; 233 234 qos_vop_dma: qos@fe8b0000 { 235 compatible = "syscon"; 236 reg = <0x0 0xfe8b0000 0x0 0x20>; 237 }; 238 239 qos_vop_lite: qos@fe8b0080 { 240 compatible = "syscon"; 241 reg = <0x0 0xfe8b0080 0x0 0x20>; 242 }; 243 244 qos_vpu: qos@fe8cc000 { 245 compatible = "syscon"; 246 reg = <0x0 0xfe8c000 0x0 0x20>; 247 }; 248 249 sram: sram@fec00000 { 250 compatible = "mmio-sram"; 251 reg = <0x0 0xfec00000 0x0 0x200000>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 ranges = <0 0x0 0xfec00000 0x200000>; 255 /* reserved for ddr dvfs and system suspend/resume */ 256 ddr-sram@0 { 257 reg = <0x0 0x8000>; 258 }; 259 /* reserved for vad audio buffer */ 260 vad_sram: vad-sram@1c0000 { 261 reg = <0x1c0000 0x40000>; 262 }; 263 }; 264 265 gic: interrupt-controller@ff100000 { 266 compatible = "arm,gic-v3"; 267 #interrupt-cells = <3>; 268 #address-cells = <2>; 269 #size-cells = <2>; 270 ranges; 271 interrupt-controller; 272 273 reg = <0x0 0xff100000 0 0x10000>, /* GICD */ 274 <0x0 0xff140000 0 0xc0000>, /* GICR */ 275 <0x0 0xff300000 0 0x10000>, /* GICC */ 276 <0x0 0xff310000 0 0x10000>, /* GICH */ 277 <0x0 0xff320000 0 0x10000>; /* GICV */ 278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 279 its: interrupt-controller@ff120000 { 280 compatible = "arm,gic-v3-its"; 281 msi-controller; 282 reg = <0x0 0xff120000 0x0 0x20000>; 283 }; 284 }; 285 286 cru: clock-controller@ff350000 { 287 compatible = "rockchip,rk1808-cru"; 288 reg = <0x0 0xff350000 0x0 0x5000>; 289 rockchip,grf = <&grf>; 290 #clock-cells = <1>; 291 #reset-cells = <1>; 292 293 assigned-clocks = 294 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 295 <&cru PLL_PPLL>, <&cru ARMCLK>, 296 <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 297 <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 298 <&cru LSCLK_BUS_PRE>; 299 assigned-clock-rates = 300 <1200000000>, <1000000000>, 301 <416000000>, <816000000>, 302 <200000000>, <100000000>, 303 <300000000>, <200000000>, 304 <100000000>; 305 }; 306 307 mipi_dphy: mipi-dphy@ff370000 { 308 compatible = "rockchip,rk1808-mipi-dphy"; 309 reg = <0x0 0xff370000 0x0 0x500>; 310 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 311 clock-names = "ref", "pclk"; 312 clock-output-names = "mipi_dphy_pll"; 313 #clock-cells = <0>; 314 resets = <&cru SRST_MIPIDSIPHY_P>; 315 reset-names = "apb"; 316 #phy-cells = <0>; 317 rockchip,grf = <&grf>; 318 status = "disabled"; 319 }; 320 321 tsadc: tsadc@ff3a0000 { 322 compatible = "rockchip,rk1808-tsadc"; 323 reg = <0x0 0xff3a0000 0x0 0x100>; 324 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 325 rockchip,grf = <&grf>; 326 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 327 clock-names = "tsadc", "apb_pclk"; 328 assigned-clocks = <&cru SCLK_TSADC>; 329 assigned-clock-rates = <50000>; 330 resets = <&cru SRST_TSADC>; 331 reset-names = "tsadc-apb"; 332 #thermal-sensor-cells = <1>; 333 rockchip,hw-tshut-temp = <120000>; 334 status = "disabled"; 335 }; 336 337 pwm0: pwm@ff3d0000 { 338 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 339 reg = <0x0 0xff3d0000 0x0 0x10>; 340 #pwm-cells = <3>; 341 pinctrl-names = "active"; 342 pinctrl-0 = <&pwm0_pin>; 343 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 344 clock-names = "pwm", "pclk"; 345 status = "disabled"; 346 }; 347 348 pwm1: pwm@ff3d0010 { 349 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 350 reg = <0x0 0xff3d0010 0x0 0x10>; 351 #pwm-cells = <3>; 352 pinctrl-names = "active"; 353 pinctrl-0 = <&pwm1_pin>; 354 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 355 clock-names = "pwm", "pclk"; 356 status = "disabled"; 357 }; 358 359 pwm2: pwm@ff3d0020 { 360 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 361 reg = <0x0 0xff3d0020 0x0 0x10>; 362 #pwm-cells = <3>; 363 pinctrl-names = "active"; 364 pinctrl-0 = <&pwm2_pin>; 365 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 366 clock-names = "pwm", "pclk"; 367 status = "disabled"; 368 }; 369 370 pwm3: pwm@ff3d0030 { 371 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 372 reg = <0x0 0xff3d0030 0x0 0x10>; 373 #pwm-cells = <3>; 374 pinctrl-names = "active"; 375 pinctrl-0 = <&pwm3_pin>; 376 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 377 clock-names = "pwm", "pclk"; 378 status = "disabled"; 379 }; 380 381 pwm4: pwm@ff3d8000 { 382 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 383 reg = <0x0 0xff3d8000 0x0 0x10>; 384 #pwm-cells = <3>; 385 pinctrl-names = "active"; 386 pinctrl-0 = <&pwm4_pin>; 387 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 388 clock-names = "pwm", "pclk"; 389 status = "disabled"; 390 }; 391 392 pwm5: pwm@ff3d8010 { 393 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 394 reg = <0x0 0xff3d8010 0x0 0x10>; 395 #pwm-cells = <3>; 396 pinctrl-names = "active"; 397 pinctrl-0 = <&pwm5_pin>; 398 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 399 clock-names = "pwm", "pclk"; 400 status = "disabled"; 401 }; 402 403 pwm6: pwm@ff3d8020 { 404 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 405 reg = <0x0 0xff3d8020 0x0 0x10>; 406 #pwm-cells = <3>; 407 pinctrl-names = "active"; 408 pinctrl-0 = <&pwm6_pin>; 409 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 410 clock-names = "pwm", "pclk"; 411 status = "disabled"; 412 }; 413 414 pwm7: pwm@ff3d8030 { 415 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 416 reg = <0x0 0xff3d8030 0x0 0x10>; 417 #pwm-cells = <3>; 418 pinctrl-names = "active"; 419 pinctrl-0 = <&pwm7_pin>; 420 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 421 clock-names = "pwm", "pclk"; 422 status = "disabled"; 423 }; 424 425 pmu: power-management@ff3e0000 { 426 compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; 427 reg = <0x0 0xff3e0000 0x0 0x1000>; 428 429 power: power-controller { 430 compatible = "rockchip,rk1808-power-controller"; 431 #power-domain-cells = <1>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 status = "disabled"; 435 436 /* These power domains are grouped by VD_NPU */ 437 pd_npu@RK1808_VD_NPU { 438 reg = <RK1808_VD_NPU>; 439 clocks = <&cru SCLK_NPU>, 440 <&cru ACLK_NPU>, 441 <&cru HCLK_NPU>; 442 pm_qos = <&qos_npu>; 443 }; 444 445 /* These power domains are grouped by VD_LOGIC */ 446 pd_pcie@RK1808_PD_PCIE { 447 reg = <RK1808_PD_PCIE>; 448 clocks = <&cru HSCLK_PCIE>, 449 <&cru LSCLK_PCIE>, 450 <&cru ACLK_PCIE>, 451 <&cru ACLK_PCIE_MST>, 452 <&cru ACLK_PCIE_SLV>, 453 <&cru PCLK_PCIE>, 454 <&cru SCLK_PCIE_AUX>; 455 pm_qos = <&qos_pcie>; 456 }; 457 pd_vpu@RK1808_PD_VPU { 458 reg = <RK1808_PD_VPU>; 459 clocks = <&cru ACLK_VPU>, 460 <&cru HCLK_VPU>; 461 pm_qos = <&qos_vpu>; 462 }; 463 pd_vio@RK1808_PD_VIO { 464 reg = <RK1808_PD_VIO>; 465 clocks = <&cru HSCLK_VIO>, 466 <&cru LSCLK_VIO>, 467 <&cru ACLK_VOPRAW>, 468 <&cru HCLK_VOPRAW>, 469 <&cru ACLK_VOPLITE>, 470 <&cru HCLK_VOPLITE>, 471 <&cru PCLK_DSI_TX>, 472 <&cru PCLK_CSI_TX>, 473 <&cru ACLK_RGA>, 474 <&cru HCLK_RGA>, 475 <&cru ACLK_ISP>, 476 <&cru HCLK_ISP>, 477 <&cru ACLK_CIF>, 478 <&cru HCLK_CIF>, 479 <&cru PCLK_CSI2HOST>, 480 <&cru DCLK_VOPRAW>, 481 <&cru DCLK_VOPLITE>; 482 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 483 <&qos_isp>, <&qos_vip>, 484 <&qos_vop_dma>, <&qos_vop_lite>; 485 }; 486 }; 487 }; 488 489 i2c0: i2c@ff410000 { 490 compatible = "rockchip,rk3399-i2c"; 491 reg = <0x0 0xff410000 0x0 0x1000>; 492 clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; 493 clock-names = "i2c", "pclk"; 494 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&i2c0_xfer>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 dmac: dmac@ff4e0000 { 503 compatible = "arm,pl330", "arm,primecell"; 504 reg = <0x0 0xff4e0000 0x0 0x4000>; 505 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cru ACLK_DMAC>; 507 clock-names = "apb_pclk"; 508 #dma-cells = <1>; 509 peripherals-req-type-burst; 510 }; 511 512 uart0: serial@ff430000 { 513 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 514 reg = <0x0 0xff430000 0x0 0x100>; 515 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 517 clock-names = "baudclk", "apb_pclk"; 518 reg-shift = <2>; 519 reg-io-width = <4>; 520 dmas = <&dmac 0>, <&dmac 1>; 521 dma-names = "tx", "rx"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 524 status = "disabled"; 525 }; 526 527 i2c1: i2c@ff500000 { 528 compatible = "rockchip,rk3399-i2c"; 529 reg = <0x0 0xff500000 0x0 0x1000>; 530 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 531 clock-names = "i2c", "pclk"; 532 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&i2c1_xfer>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 i2c2: i2c@ff504000 { 541 compatible = "rockchip,rk3399-i2c"; 542 reg = <0x0 0xff504000 0x0 0x1000>; 543 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 544 clock-names = "i2c", "pclk"; 545 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&i2c2m0_xfer>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 i2c3: i2c@ff508000 { 554 compatible = "rockchip,rk3399-i2c"; 555 reg = <0x0 0xff508000 0x0 0x1000>; 556 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 557 clock-names = "i2c", "pclk"; 558 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2c3_xfer>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 566 i2c4: i2c@ff50c000 { 567 compatible = "rockchip,rk3399-i2c"; 568 reg = <0x0 0xff50c000 0x0 0x1000>; 569 clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; 570 clock-names = "i2c", "pclk"; 571 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2c4_xfer>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 }; 578 579 i2c5: i2c@ff510000 { 580 compatible = "rockchip,rk3399-i2c"; 581 reg = <0x0 0xff100000 0x0 0x1000>; 582 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 583 clock-names = "i2c", "pclk"; 584 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&i2c5_xfer>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 spi0: spi@ff520000 { 593 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 594 reg = <0x0 0xff520000 0x0 0x1000>; 595 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 599 clock-names = "spiclk", "apb_pclk"; 600 dmas = <&dmac 10>, <&dmac 11>; 601 dma-names = "tx", "rx"; 602 pinctrl-names = "default", "high_speed"; 603 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 604 pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; 605 status = "disabled"; 606 }; 607 608 spi1: spi@ff530000 { 609 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 610 reg = <0x0 0xff530000 0x0 0x1000>; 611 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 615 clock-names = "spiclk", "apb_pclk"; 616 dmas = <&dmac 12>, <&dmac 13>; 617 dma-names = "tx", "rx"; 618 pinctrl-names = "default", "high_speed"; 619 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 620 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; 621 status = "disabled"; 622 }; 623 624 uart1: serial@ff540000 { 625 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 626 reg = <0x0 0xff540000 0x0 0x100>; 627 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 629 clock-names = "baudclk", "apb_pclk"; 630 reg-shift = <2>; 631 reg-io-width = <4>; 632 dmas = <&dmac 2>, <&dmac 3>; 633 dma-names = "tx", "rx"; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>; 636 status = "disabled"; 637 }; 638 639 uart2: serial@ff550000 { 640 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 641 reg = <0x0 0xff550000 0x0 0x100>; 642 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 644 clock-names = "baudclk", "apb_pclk"; 645 reg-shift = <2>; 646 reg-io-width = <4>; 647 dmas = <&dmac 4>, <&dmac 5>; 648 dma-names = "tx", "rx"; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&uart2m0_xfer>; 651 status = "disabled"; 652 }; 653 654 uart3: serial@ff560000 { 655 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 656 reg = <0x0 0xff560000 0x0 0x100>; 657 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 659 clock-names = "baudclk", "apb_pclk"; 660 reg-shift = <2>; 661 reg-io-width = <4>; 662 dmas = <&dmac 6>, <&dmac 7>; 663 dma-names = "tx", "rx"; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>; 666 status = "disabled"; 667 }; 668 669 uart4: serial@ff570000 { 670 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 671 reg = <0x0 0xff570000 0x0 0x100>; 672 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 674 clock-names = "baudclk", "apb_pclk"; 675 reg-shift = <2>; 676 reg-io-width = <4>; 677 dmas = <&dmac 8>, <&dmac 9>; 678 dma-names = "tx", "rx"; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 681 status = "disabled"; 682 }; 683 684 spi2: spi@ff580000 { 685 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 686 reg = <0x0 0xff580000 0x0 0x1000>; 687 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 691 clock-names = "spiclk", "apb_pclk"; 692 dmas = <&dmac 14>, <&dmac 15>; 693 dma-names = "tx", "rx"; 694 pinctrl-names = "default", "high_speed"; 695 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; 696 pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; 697 status = "disabled"; 698 }; 699 700 uart5: serial@ff5a0000 { 701 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 702 reg = <0x0 0xff5a0000 0x0 0x100>; 703 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 705 clock-names = "baudclk", "apb_pclk"; 706 reg-shift = <2>; 707 reg-io-width = <4>; 708 dmas = <&dmac 25>, <&dmac 26>; 709 dma-names = "tx", "rx"; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&uart5_xfer>; 712 status = "disabled"; 713 }; 714 715 uart6: serial@ff5b0000 { 716 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 717 reg = <0x0 0xff5b0000 0x0 0x100>; 718 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 720 clock-names = "baudclk", "apb_pclk"; 721 reg-shift = <2>; 722 reg-io-width = <4>; 723 dmas = <&dmac 27>, <&dmac 28>; 724 dma-names = "tx", "rx"; 725 pinctrl-names = "default"; 726 pinctrl-0 = <&uart6_xfer>; 727 status = "disabled"; 728 }; 729 730 uart7: serial@ff5c0000 { 731 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 732 reg = <0x0 0xff5c0000 0x0 0x100>; 733 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 735 clock-names = "baudclk", "apb_pclk"; 736 reg-shift = <2>; 737 reg-io-width = <4>; 738 dmas = <&dmac 29>, <&dmac 30>; 739 dma-names = "tx", "rx"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&uart7_xfer>; 742 status = "disabled"; 743 }; 744 745 vop_lite: vop@ffb00000 { 746 compatible = "rockchip,rk1808-vop-lit"; 747 reg = <0x0 0xffb00000 0x0 0x200>; 748 reg-names = "regs"; 749 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&cru ACLK_VOPLITE>, <&cru DCLK_VOPLITE>, 751 <&cru HCLK_VOPLITE>; 752 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 753 power-domains = <&power RK1808_PD_VIO>; 754 iommus = <&vopl_mmu>; 755 status = "disabled"; 756 757 vop_lite_out: port { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 vop_lite_out_dsi: endpoint@0 { 762 reg = <0>; 763 remote-endpoint = <&dsi_in_vop_lite>; 764 }; 765 766 vop_lite_out_rgb: endpoint@1 { 767 reg = <1>; 768 remote-endpoint = <&rgb_in_vop_lite>; 769 }; 770 }; 771 }; 772 773 vopl_mmu: iommu@ffb00f00 { 774 compatible = "rockchip,iommu"; 775 reg = <0x0 0xffb00f00 0x0 0x100>; 776 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "vopl_mmu"; 778 clocks = <&cru ACLK_VOPLITE>, <&cru HCLK_VOPLITE>; 779 clock-names = "aclk", "hclk"; 780 power-domains = <&power RK1808_PD_VIO>; 781 #iommu-cells = <0>; 782 status = "disabled"; 783 }; 784 785 vop_raw: vop@ffb40000 { 786 compatible = "rockchip,rk1808-vop-raw"; 787 reg = <0x0 0xffb40000 0x0 0x500>; 788 reg-names = "regs"; 789 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&cru ACLK_VOPRAW>, <&cru DCLK_VOPRAW>, 791 <&cru HCLK_VOPRAW>; 792 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 793 power-domains = <&power RK1808_PD_VIO>; 794 iommus = <&vopr_mmu>; 795 status = "disabled"; 796 797 vop_raw_out: port { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 vop_raw_out_csi: endpoint@0 { 802 reg = <0>; 803 remote-endpoint = <&csi_in_vop_raw>; 804 }; 805 }; 806 }; 807 808 vopr_mmu: iommu@ffb40f00 { 809 compatible = "rockchip,iommu"; 810 reg = <0x0 0xffb40f00 0x0 0x100>; 811 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 812 interrupt-names = "vopr_mmu"; 813 clocks = <&cru ACLK_VOPRAW>, <&cru HCLK_VOPRAW>; 814 clock-names = "aclk", "hclk"; 815 power-domains = <&power RK1808_PD_VIO>; 816 #iommu-cells = <0>; 817 status = "disabled"; 818 }; 819 820 pwm8: pwm@ff5d0000 { 821 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 822 reg = <0x0 0xff5d0000 0x0 0x10>; 823 #pwm-cells = <3>; 824 pinctrl-names = "active"; 825 pinctrl-0 = <&pwm8_pin>; 826 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 827 clock-names = "pwm", "pclk"; 828 status = "disabled"; 829 }; 830 831 pwm9: pwm@fff5d0010 { 832 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 833 reg = <0x0 0xff5d0010 0x0 0x10>; 834 #pwm-cells = <3>; 835 pinctrl-names = "active"; 836 pinctrl-0 = <&pwm9_pin>; 837 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 838 clock-names = "pwm", "pclk"; 839 status = "disabled"; 840 }; 841 842 pwm10: pwm@ff5d0020 { 843 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 844 reg = <0x0 0xff5d0020 0x0 0x10>; 845 #pwm-cells = <3>; 846 pinctrl-names = "active"; 847 pinctrl-0 = <&pwm10_pin>; 848 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 849 clock-names = "pwm", "pclk"; 850 status = "disabled"; 851 }; 852 853 pwm11: pwm@ff5d0030 { 854 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 855 reg = <0x0 0xff5d0030 0x0 0x10>; 856 #pwm-cells = <3>; 857 pinctrl-names = "active"; 858 pinctrl-0 = <&pwm11_pin>; 859 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 860 clock-names = "pwm", "pclk"; 861 status = "disabled"; 862 }; 863 864 i2s0: i2s@ff7e0000 { 865 compatible = "rockchip,rk1808-i2s-tdm"; 866 reg = <0x0 0xff7e0000 0x0 0x1000>; 867 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 869 clock-names = "mclk_tx", "mclk_rx", "hclk"; 870 dmas = <&dmac 16>, <&dmac 17>; 871 dma-names = "tx", "rx"; 872 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 873 reset-names = "tx-m", "rx-m"; 874 rockchip,cru = <&cru>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&i2s0_8ch_sclktx 877 &i2s0_8ch_sclkrx 878 &i2s0_8ch_lrcktx 879 &i2s0_8ch_lrckrx 880 &i2s0_8ch_sdi0 881 &i2s0_8ch_sdi1 882 &i2s0_8ch_sdi2 883 &i2s0_8ch_sdi3 884 &i2s0_8ch_sdo0 885 &i2s0_8ch_sdo1 886 &i2s0_8ch_sdo2 887 &i2s0_8ch_sdo3 888 &i2s0_8ch_mclk>; 889 status = "disabled"; 890 }; 891 892 i2s1: i2s@ff7f0000 { 893 compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s"; 894 reg = <0x0 0xff7f0000 0x0 0x1000>; 895 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 897 clock-names = "i2s_clk", "i2s_hclk"; 898 dmas = <&dmac 18>, <&dmac 19>; 899 dma-names = "tx", "rx"; 900 pinctrl-names = "default"; 901 pinctrl-0 = <&i2s1_2ch_sclk 902 &i2s1_2ch_lrck 903 &i2s1_2ch_sdi 904 &i2s1_2ch_sdo>; 905 status = "disabled"; 906 }; 907 908 pdm: pdm@ff800000 { 909 compatible = "rockchip,rk1808-pdm", "rockchip,pdm"; 910 reg = <0x0 0xff800000 0x0 0x1000>; 911 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 912 clock-names = "pdm_clk", "pdm_hclk"; 913 dmas = <&dmac 24>; 914 dma-names = "rx"; 915 resets = <&cru SRST_PDM>; 916 reset-names = "pdm-m"; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&pdm_clk 919 &pdm_clk1 920 &pdm_sdi0 921 &pdm_sdi1 922 &pdm_sdi2 923 &pdm_sdi3>; 924 status = "disabled"; 925 }; 926 927 vad: vad@ff810000 { 928 compatible = "rockchip,rk1808-vad"; 929 reg = <0x0 0xff810000 0x0 0x10000>; 930 reg-names = "vad"; 931 clocks = <&cru HCLK_VAD>; 932 clock-names = "hclk"; 933 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 934 rockchip,audio-sram = <&vad_sram>; 935 rockchip,audio-src = <0>; 936 rockchip,det-channel = <0>; 937 rockchip,mode = <1>; 938 status = "disabled"; 939 }; 940 941 csi_tx: csi@ffb20000 { 942 compatible = "rockchip,rk1808-mipi-csi"; 943 reg = <0x0 0xffb20000 0x0 0x500>; 944 reg-names = "csi_regs"; 945 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&cru PCLK_CSI_TX>, <&mipi_dphy>; 947 clock-names = "pclk", "hs_clk"; 948 resets = <&cru SRST_CSITX_P>; 949 reset-names = "apb"; 950 phys = <&mipi_dphy>; 951 phy-names = "mipi_dphy"; 952 power-domains = <&power RK1808_PD_VIO>; 953 rockchip,grf = <&grf>; 954 status = "disabled"; 955 956 ports { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 port { 961 csi_in_vop_raw: endpoint { 962 remote-endpoint = <&vop_raw_out_csi>; 963 }; 964 }; 965 }; 966 }; 967 968 dsi: dsi@ffb30000 { 969 compatible = "rockchip,rk1808-mipi-dsi"; 970 reg = <0x0 0xffb30000 0x0 0x500>; 971 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cru PCLK_DSI_TX>, <&mipi_dphy>; 973 clock-names = "pclk", "hs_clk"; 974 resets = <&cru SRST_MIPIDSI_HOST_P>; 975 reset-names = "apb"; 976 phys = <&mipi_dphy>; 977 phy-names = "mipi_dphy"; 978 power-domains = <&power RK1808_PD_VIO>; 979 rockchip,grf = <&grf>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 status = "disabled"; 983 984 ports { 985 port { 986 dsi_in_vop_lite: endpoint { 987 remote-endpoint = <&vop_lite_out_dsi>; 988 }; 989 }; 990 }; 991 }; 992 993 sdio: dwmmc@ffc60000 { 994 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 995 reg = <0x0 0xffc60000 0x0 0x4000>; 996 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 997 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 998 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 999 max-frequency = <150000000>; 1000 fifo-depth = <0x100>; 1001 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 1004 status = "disabled"; 1005 }; 1006 1007 npu: npu@ffbc0000 { 1008 compatible = "rockchip,npu"; 1009 reg = <0x0 0xffbc0000 0x0 0x1000>; 1010 clocks = <&cru SCLK_NPU>, <&cru HCLK_NPU>; 1011 clock-names = "sclk_npu", "hclk_npu"; 1012 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1013 status = "disabled"; 1014 }; 1015 1016 saradc: saradc@ff3c0000 { 1017 compatible = "rockchip,rk1808-saradc", "rockchip,rk3399-saradc"; 1018 reg = <0x0 0xff3c0000 0x0 0x100>; 1019 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1020 #io-channel-cells = <1>; 1021 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 1022 clock-names = "saradc", "apb_pclk"; 1023 resets = <&cru SRST_SARADC_P>; 1024 reset-names = "saradc-apb"; 1025 status = "disabled"; 1026 }; 1027 1028 sdmmc: dwmmc@ffcf0000 { 1029 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1030 reg = <0x0 0xffcf0000 0x0 0x4000>; 1031 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 1032 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1033 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1034 max-frequency = <150000000>; 1035 fifo-depth = <0x100>; 1036 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd>; 1039 status = "disabled"; 1040 }; 1041 1042 emmc: dwmmc@ffd00000 { 1043 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1044 reg = <0x0 0xffd00000 0x0 0x4000>; 1045 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1046 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1047 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1048 max-frequency = <150000000>; 1049 fifo-depth = <0x100>; 1050 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1051 status = "disabled"; 1052 }; 1053 1054 usb_host0_ehci: usb@ffd80000 { 1055 compatible = "generic-ehci"; 1056 reg = <0x0 0xffd80000 0x0 0x10000>; 1057 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1059 <&u2phy>; 1060 clock-names = "usbhost", "arbiter", "utmi"; 1061 phys = <&u2phy_host>; 1062 phy-names = "usb"; 1063 status = "disabled"; 1064 }; 1065 1066 usb_host0_ohci: usb@ffd90000 { 1067 compatible = "generic-ohci"; 1068 reg = <0x0 0xffd90000 0x0 0x10000>; 1069 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1071 <&u2phy>; 1072 clock-names = "usbhost", "arbiter", "utmi"; 1073 phys = <&u2phy_host>; 1074 phy-names = "usb"; 1075 status = "disabled"; 1076 }; 1077 1078 gmac: ethernet@ffdd0000 { 1079 compatible = "rockchip,rk1808-gmac"; 1080 reg = <0x0 0xffdd0000 0x0 0x10000>; 1081 rockchip,grf = <&grf>; 1082 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1083 interrupt-names = "macirq"; 1084 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 1085 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, 1086 <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, 1087 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; 1088 clock-names = "stmmaceth", "mac_clk_rx", 1089 "mac_clk_tx", "clk_mac_ref", 1090 "clk_mac_refout", "aclk_mac", 1091 "pclk_mac", "clk_mac_speed"; 1092 phy-mode = "rgmii"; 1093 pinctrl-names = "default"; 1094 pinctrl-0 = <&rgmii_pins>; 1095 resets = <&cru SRST_GAMC_A>; 1096 reset-names = "stmmaceth"; 1097 /* power-domains = <&power RK1808_PD_GMAC>; */ 1098 status = "disabled"; 1099 }; 1100 1101 pinctrl: pinctrl { 1102 compatible = "rockchip,rk1808-pinctrl"; 1103 rockchip,grf = <&grf>; 1104 rockchip,pmu = <&pmugrf>; 1105 #address-cells = <2>; 1106 #size-cells = <2>; 1107 ranges; 1108 1109 gpio0: gpio0@ff4c0000 { 1110 compatible = "rockchip,gpio-bank"; 1111 reg = <0x0 0xff4c0000 0x0 0x100>; 1112 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; 1114 gpio-controller; 1115 #gpio-cells = <2>; 1116 1117 interrupt-controller; 1118 #interrupt-cells = <2>; 1119 }; 1120 1121 gpio1: gpio1@ff690000 { 1122 compatible = "rockchip,gpio-bank"; 1123 reg = <0x0 0xff690000 0x0 0x100>; 1124 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1126 gpio-controller; 1127 #gpio-cells = <2>; 1128 1129 interrupt-controller; 1130 #interrupt-cells = <2>; 1131 }; 1132 1133 gpio2: gpio2@ff6a0000 { 1134 compatible = "rockchip,gpio-bank"; 1135 reg = <0x0 0xff6a0000 0x0 0x100>; 1136 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1138 gpio-controller; 1139 #gpio-cells = <2>; 1140 1141 interrupt-controller; 1142 #interrupt-cells = <2>; 1143 }; 1144 1145 gpio3: gpio3@ff6b0000 { 1146 compatible = "rockchip,gpio-bank"; 1147 reg = <0x0 0xff6b0000 0x0 0x100>; 1148 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1150 gpio-controller; 1151 #gpio-cells = <2>; 1152 1153 interrupt-controller; 1154 #interrupt-cells = <2>; 1155 }; 1156 1157 gpio4: gpio4@ff6c0000 { 1158 compatible = "rockchip,gpio-bank"; 1159 reg = <0x0 0xff6c0000 0x0 0x100>; 1160 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1162 gpio-controller; 1163 #gpio-cells = <2>; 1164 1165 interrupt-controller; 1166 #interrupt-cells = <2>; 1167 }; 1168 1169 pcfg_pull_up: pcfg-pull-up { 1170 bias-pull-up; 1171 }; 1172 1173 pcfg_pull_down: pcfg-pull-down { 1174 bias-pull-down; 1175 }; 1176 1177 pcfg_pull_none: pcfg-pull-none { 1178 bias-disable; 1179 }; 1180 1181 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1182 bias-disable; 1183 drive-strength = <2>; 1184 }; 1185 1186 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1187 bias-pull-up; 1188 drive-strength = <2>; 1189 }; 1190 1191 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1192 bias-pull-up; 1193 drive-strength = <4>; 1194 }; 1195 1196 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1197 bias-disable; 1198 drive-strength = <4>; 1199 }; 1200 1201 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1202 bias-pull-down; 1203 drive-strength = <4>; 1204 }; 1205 1206 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1207 bias-disable; 1208 drive-strength = <8>; 1209 }; 1210 1211 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1212 bias-pull-up; 1213 drive-strength = <8>; 1214 }; 1215 1216 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1217 bias-disable; 1218 drive-strength = <12>; 1219 }; 1220 1221 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1222 bias-pull-up; 1223 drive-strength = <12>; 1224 }; 1225 1226 pcfg_pull_none_smt: pcfg-pull-none-smt { 1227 bias-disable; 1228 input-schmitt-enable; 1229 }; 1230 1231 pcfg_output_high: pcfg-output-high { 1232 output-high; 1233 }; 1234 1235 pcfg_output_low: pcfg-output-low { 1236 output-low; 1237 }; 1238 1239 pcfg_input_high: pcfg-input-high { 1240 bias-pull-up; 1241 input-enable; 1242 }; 1243 1244 pcfg_input: pcfg-input { 1245 input-enable; 1246 }; 1247 1248 emmc { 1249 emmc_clk: emmc-clk { 1250 rockchip,pins = 1251 /* emmc_clkout */ 1252 <1 RK_PB1 1 &pcfg_pull_none>; 1253 }; 1254 1255 emmc_rstnout: emmc-rstnout { 1256 rockchip,pins = 1257 /* emmc_rstn */ 1258 <1 RK_PB3 1 &pcfg_pull_none>; 1259 }; 1260 1261 emmc_bus8: emmc-bus8 { 1262 rockchip,pins = 1263 /* emmc_d0 */ 1264 <1 RK_PA0 1 &pcfg_pull_none>, 1265 /* emmc_d1 */ 1266 <1 RK_PA1 1 &pcfg_pull_none>, 1267 /* emmc_d2 */ 1268 <1 RK_PA2 1 &pcfg_pull_none>, 1269 /* emmc_d3 */ 1270 <1 RK_PA3 1 &pcfg_pull_none>, 1271 /* emmc_d4 */ 1272 <1 RK_PA4 1 &pcfg_pull_none>, 1273 /* emmc_d5 */ 1274 <1 RK_PA5 1 &pcfg_pull_none>, 1275 /* emmc_d6 */ 1276 <1 RK_PA6 1 &pcfg_pull_none>, 1277 /* emmc_d7 */ 1278 <1 RK_PA7 1 &pcfg_pull_none>; 1279 }; 1280 1281 emmc_pwren: emmc-pwren { 1282 rockchip,pins = 1283 <1 RK_PB0 1 &pcfg_pull_none>; 1284 }; 1285 1286 emmc_cmd: emmc-cmd { 1287 rockchip,pins = 1288 <1 RK_PB2 1 &pcfg_pull_none>; 1289 }; 1290 }; 1291 1292 gmac { 1293 rgmii_pins: rgmii-pins { 1294 rockchip,pins = 1295 /* rgmii_txen */ 1296 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 1297 /* rgmii_txd1 */ 1298 <2 RK_PA2 2 &pcfg_pull_none_12ma>, 1299 /* rgmii_txd0 */ 1300 <2 RK_PA3 2 &pcfg_pull_none_12ma>, 1301 /* rgmii_rxd0 */ 1302 <2 RK_PA4 2 &pcfg_pull_none>, 1303 /* rgmii_rxd1 */ 1304 <2 RK_PA5 2 &pcfg_pull_none>, 1305 /* rgmii_rxdv */ 1306 <2 RK_PA7 2 &pcfg_pull_none>, 1307 /* rgmii_mdio */ 1308 <2 RK_PB0 2 &pcfg_pull_none>, 1309 /* rgmii_mdc */ 1310 <2 RK_PB2 2 &pcfg_pull_none>, 1311 /* rgmii_txd3 */ 1312 <2 RK_PB3 2 &pcfg_pull_none_12ma>, 1313 /* rgmii_txd2 */ 1314 <2 RK_PB4 2 &pcfg_pull_none_12ma>, 1315 /* rgmii_rxd2 */ 1316 <2 RK_PB5 2 &pcfg_pull_none>, 1317 /* rgmii_rxd3 */ 1318 <2 RK_PB6 2 &pcfg_pull_none>, 1319 /* rgmii_clk */ 1320 <2 RK_PB7 2 &pcfg_pull_none>, 1321 /* rgmii_txclk */ 1322 <2 RK_PC1 2 &pcfg_pull_none_12ma>, 1323 /* rgmii_rxclk */ 1324 <2 RK_PC2 2 &pcfg_pull_none>; 1325 }; 1326 1327 rmii_pins: rmii-pins { 1328 rockchip,pins = 1329 /* rmii_txen */ 1330 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 1331 /* rmii_txd1 */ 1332 <2 RK_PA2 2 &pcfg_pull_none_12ma>, 1333 /* rmii_txd0 */ 1334 <2 RK_PA3 2 &pcfg_pull_none_12ma>, 1335 /* rmii_rxd0 */ 1336 <2 RK_PA4 2 &pcfg_pull_none>, 1337 /* rmii_rxd1 */ 1338 <2 RK_PA5 2 &pcfg_pull_none>, 1339 /* rmii_rxer */ 1340 <2 RK_PA6 2 &pcfg_pull_none>, 1341 /* rmii_rxdv */ 1342 <2 RK_PA7 2 &pcfg_pull_none>, 1343 /* rmii_mdio */ 1344 <2 RK_PB0 2 &pcfg_pull_none>, 1345 /* rmii_mdc */ 1346 <2 RK_PB2 2 &pcfg_pull_none>, 1347 /* rmii_clk */ 1348 <2 RK_PB7 2 &pcfg_pull_none>; 1349 }; 1350 }; 1351 1352 i2c0 { 1353 i2c0_xfer: i2c0-xfer { 1354 rockchip,pins = 1355 /* i2c0_sda */ 1356 <0 RK_PB1 1 &pcfg_pull_none_smt>, 1357 /* i2c0_scl */ 1358 <0 RK_PB0 1 &pcfg_pull_none_smt>; 1359 }; 1360 }; 1361 1362 i2c1 { 1363 i2c1_xfer: i2c1-xfer { 1364 rockchip,pins = 1365 /* i2c1_sda */ 1366 <0 RK_PC1 1 &pcfg_pull_none_smt>, 1367 /* i2c1_scl */ 1368 <0 RK_PC0 1 &pcfg_pull_none_smt>; 1369 }; 1370 }; 1371 1372 i2c2m0 { 1373 i2c2m0_xfer: i2c2m0-xfer { 1374 rockchip,pins = 1375 /* i2c2m0_sda */ 1376 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1377 /* i2c2m0_scl */ 1378 <3 RK_PB3 2 &pcfg_pull_none_smt>; 1379 }; 1380 }; 1381 1382 i2c3 { 1383 i2c3_xfer: i2c3-xfer { 1384 rockchip,pins = 1385 /* i2c3_sda */ 1386 <2 RK_PD1 1 &pcfg_pull_none_smt>, 1387 /* i2c3_scl */ 1388 <2 RK_PD0 1 &pcfg_pull_none_smt>; 1389 }; 1390 }; 1391 1392 i2c4 { 1393 i2c4_xfer: i2c4-xfer { 1394 rockchip,pins = 1395 /* i2c4_sda */ 1396 <3 RK_PC3 3 &pcfg_pull_none_smt>, 1397 /* i2c4_scl */ 1398 <3 RK_PC2 3 &pcfg_pull_none_smt>; 1399 }; 1400 }; 1401 1402 i2c5 { 1403 i2c5_xfer: i2c5-xfer { 1404 rockchip,pins = 1405 /* i2c5_sda */ 1406 <4 RK_PC2 1 &pcfg_pull_none_smt>, 1407 /* i2c5_scl */ 1408 <4 RK_PC1 1 &pcfg_pull_none_smt>; 1409 }; 1410 }; 1411 1412 i2s1 { 1413 i2s1_2ch_lrck: i2s1-2ch-lrck { 1414 rockchip,pins = 1415 <3 RK_PA0 1 &pcfg_pull_none>; 1416 }; 1417 i2s1_2ch_sclk: i2s1-2ch-sclk { 1418 rockchip,pins = 1419 <3 RK_PA1 1 &pcfg_pull_none>; 1420 }; 1421 i2s1_2ch_mclk: i2s1-2ch-mclk { 1422 rockchip,pins = 1423 <3 RK_PA2 1 &pcfg_pull_none>; 1424 }; 1425 i2s1_2ch_sdo: i2s1-2ch-sdo { 1426 rockchip,pins = 1427 <3 RK_PA3 1 &pcfg_pull_none>; 1428 }; 1429 i2s1_2ch_sdi: i2s1-2ch-sdi { 1430 rockchip,pins = 1431 <3 RK_PA4 1 &pcfg_pull_none>; 1432 }; 1433 }; 1434 1435 i2s0 { 1436 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1437 rockchip,pins = 1438 <3 RK_PA5 1 &pcfg_pull_none>; 1439 }; 1440 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1441 rockchip,pins = 1442 <3 RK_PA6 1 &pcfg_pull_none>; 1443 }; 1444 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1445 rockchip,pins = 1446 <3 RK_PA7 1 &pcfg_pull_none>; 1447 }; 1448 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1449 rockchip,pins = 1450 <3 RK_PB0 1 &pcfg_pull_none>; 1451 }; 1452 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1453 rockchip,pins = 1454 <3 RK_PB1 1 &pcfg_pull_none>; 1455 }; 1456 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1457 rockchip,pins = 1458 <3 RK_PB2 1 &pcfg_pull_none>; 1459 }; 1460 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1461 rockchip,pins = 1462 <3 RK_PB3 1 &pcfg_pull_none>; 1463 }; 1464 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1465 rockchip,pins = 1466 <3 RK_PB4 1 &pcfg_pull_none>; 1467 }; 1468 i2s0_8ch_mclk: i2s0-8ch-mclk { 1469 rockchip,pins = 1470 <3 RK_PB5 1 &pcfg_pull_none>; 1471 }; 1472 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1473 rockchip,pins = 1474 <3 RK_PB6 1 &pcfg_pull_none>; 1475 }; 1476 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1477 rockchip,pins = 1478 <3 RK_PB7 1 &pcfg_pull_none>; 1479 }; 1480 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1481 rockchip,pins = 1482 <3 RK_PC0 1 &pcfg_pull_none>; 1483 }; 1484 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1485 rockchip,pins = 1486 <3 RK_PC1 1 &pcfg_pull_none>; 1487 }; 1488 }; 1489 1490 lcdc { 1491 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1492 rockchip,pins = 1493 /* lcdc_clkm0 */ 1494 <2 RK_PC6 3 &pcfg_pull_none>; 1495 }; 1496 1497 lcdc_rgb_den_pin: lcdc-rgb-den-pin { 1498 rockchip,pins = 1499 /* lcdc_denm0 */ 1500 <2 RK_PC7 3 &pcfg_pull_none>; 1501 }; 1502 1503 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1504 rockchip,pins = 1505 /* lcdc_hsyncm0 */ 1506 <2 RK_PB2 3 &pcfg_pull_none>; 1507 }; 1508 1509 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1510 rockchip,pins = 1511 /* lcdc_vsyncm0 */ 1512 <2 RK_PB3 3 &pcfg_pull_none>; 1513 }; 1514 1515 lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin { 1516 rockchip,pins = 1517 /* lcdc_hsyncm1 */ 1518 <3 RK_PB2 3 &pcfg_pull_none>; 1519 }; 1520 1521 lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin { 1522 rockchip,pins = 1523 /* lcdc_vsyncm1 */ 1524 <3 RK_PB3 3 &pcfg_pull_none>; 1525 }; 1526 1527 lcdc_rgb666_data_pins: lcdc-rgb666-data-pins { 1528 rockchip,pins = 1529 /* lcdc_d0m0 */ 1530 <2 RK_PA2 3 &pcfg_pull_none>, 1531 /* lcdc_d1m0 */ 1532 <2 RK_PA3 3 &pcfg_pull_none>, 1533 /* lcdc_d2m0 */ 1534 <2 RK_PC2 3 &pcfg_pull_none>, 1535 /* lcdc_d3m0 */ 1536 <2 RK_PC3 3 &pcfg_pull_none>, 1537 /* lcdc_d4m0 */ 1538 <2 RK_PC4 3 &pcfg_pull_none>, 1539 /* lcdc_d5m0 */ 1540 <2 RK_PC5 3 &pcfg_pull_none>, 1541 /* lcdc_d6m0 */ 1542 <2 RK_PA0 3 &pcfg_pull_none>, 1543 /* lcdc_d7m0 */ 1544 <2 RK_PA1 3 &pcfg_pull_none>, 1545 /* lcdc_d8 */ 1546 <3 RK_PC2 1 &pcfg_pull_none>, 1547 /* lcdc_d9 */ 1548 <3 RK_PC3 1 &pcfg_pull_none>, 1549 /* lcdc_d10 */ 1550 <3 RK_PC4 1 &pcfg_pull_none>, 1551 /* lcdc_d11 */ 1552 <3 RK_PC5 1 &pcfg_pull_none>, 1553 /* lcdc_d12 */ 1554 <3 RK_PC6 1 &pcfg_pull_none>, 1555 /* lcdc_d13 */ 1556 <3 RK_PC7 1 &pcfg_pull_none>, 1557 /* lcdc_d14 */ 1558 <3 RK_PD0 1 &pcfg_pull_none>, 1559 /* lcdc_d15 */ 1560 <3 RK_PD1 1 &pcfg_pull_none>, 1561 /* lcdc_d16 */ 1562 <3 RK_PD2 1 &pcfg_pull_none>, 1563 /* lcdc_d17 */ 1564 <3 RK_PD3 1 &pcfg_pull_none>; 1565 }; 1566 1567 lcdc_rgb565_data_pins: lcdc-rgb565-data-pins { 1568 rockchip,pins = 1569 /* lcdc_d0m0 */ 1570 <2 RK_PA2 3 &pcfg_pull_none>, 1571 /* lcdc_d1m0 */ 1572 <2 RK_PA3 3 &pcfg_pull_none>, 1573 /* lcdc_d2m0 */ 1574 <2 RK_PC2 3 &pcfg_pull_none>, 1575 /* lcdc_d3m0 */ 1576 <2 RK_PC3 3 &pcfg_pull_none>, 1577 /* lcdc_d4m0 */ 1578 <2 RK_PC4 3 &pcfg_pull_none>, 1579 /* lcdc_d5m0 */ 1580 <2 RK_PC5 3 &pcfg_pull_none>, 1581 /* lcdc_d6m0 */ 1582 <2 RK_PA0 3 &pcfg_pull_none>, 1583 /* lcdc_d7m0 */ 1584 <2 RK_PA1 3 &pcfg_pull_none>, 1585 /* lcdc_d8 */ 1586 <3 RK_PC2 1 &pcfg_pull_none>, 1587 /* lcdc_d9 */ 1588 <3 RK_PC3 1 &pcfg_pull_none>, 1589 /* lcdc_d10 */ 1590 <3 RK_PC4 1 &pcfg_pull_none>, 1591 /* lcdc_d11 */ 1592 <3 RK_PC5 1 &pcfg_pull_none>, 1593 /* lcdc_d12 */ 1594 <3 RK_PC6 1 &pcfg_pull_none>, 1595 /* lcdc_d13 */ 1596 <3 RK_PC7 1 &pcfg_pull_none>, 1597 /* lcdc_d14 */ 1598 <3 RK_PD0 1 &pcfg_pull_none>, 1599 /* lcdc_d15 */ 1600 <3 RK_PD1 1 &pcfg_pull_none>; 1601 }; 1602 }; 1603 1604 pciusb { 1605 pciusb_pins: pciusb-pins { 1606 rockchip,pins = 1607 /* pciusb_debug0 */ 1608 <4 RK_PB4 3 &pcfg_pull_none>, 1609 /* pciusb_debug1 */ 1610 <4 RK_PB5 3 &pcfg_pull_none>, 1611 /* pciusb_debug2 */ 1612 <4 RK_PB6 3 &pcfg_pull_none>, 1613 /* pciusb_debug3 */ 1614 <4 RK_PB7 3 &pcfg_pull_none>, 1615 /* pciusb_debug4 */ 1616 <4 RK_PC0 3 &pcfg_pull_none>, 1617 /* pciusb_debug5 */ 1618 <4 RK_PC1 3 &pcfg_pull_none>, 1619 /* pciusb_debug6 */ 1620 <4 RK_PC2 3 &pcfg_pull_none>, 1621 /* pciusb_debug7 */ 1622 <4 RK_PC3 3 &pcfg_pull_none>; 1623 }; 1624 }; 1625 1626 pdm { 1627 pdm_clk: pdm-clk { 1628 rockchip,pins = 1629 /* pdm_clk0 */ 1630 <3 RK_PB0 2 &pcfg_pull_none>; 1631 }; 1632 1633 pdm_sdi3: pdm-sdi3 { 1634 rockchip,pins = 1635 <3 RK_PA5 2 &pcfg_pull_none>; 1636 }; 1637 1638 pdm_sdi2: pdm-sdi2 { 1639 rockchip,pins = 1640 <3 RK_PA6 2 &pcfg_pull_none>; 1641 }; 1642 1643 pdm_sdi1: pdm-sdi1 { 1644 rockchip,pins = 1645 <3 RK_PA7 2 &pcfg_pull_none>; 1646 }; 1647 1648 pdm_clk1: pdm-clk1 { 1649 rockchip,pins = 1650 <3 RK_PB1 2 &pcfg_pull_none>; 1651 }; 1652 1653 pdm_sdi0: pdm-sdi0 { 1654 rockchip,pins = 1655 <3 RK_PC1 2 &pcfg_pull_none>; 1656 }; 1657 }; 1658 1659 pwm0 { 1660 pwm0_pin: pwm0-pin { 1661 rockchip,pins = 1662 <0 RK_PB7 1 &pcfg_pull_none>; 1663 }; 1664 }; 1665 1666 pwm1 { 1667 pwm1_pin: pwm1-pin { 1668 rockchip,pins = 1669 <0 RK_PC3 1 &pcfg_pull_none>; 1670 }; 1671 }; 1672 1673 pwm2 { 1674 pwm2_pin: pwm2-pin { 1675 rockchip,pins = 1676 <0 RK_PC5 1 &pcfg_pull_none>; 1677 }; 1678 }; 1679 1680 pwm3 { 1681 pwm3_pin: pwm3-pin { 1682 rockchip,pins = 1683 <0 RK_PC4 1 &pcfg_pull_none>; 1684 }; 1685 }; 1686 1687 pwm4 { 1688 pwm4_pin: pwm4-pin { 1689 rockchip,pins = 1690 <1 RK_PB6 2 &pcfg_pull_none>; 1691 }; 1692 }; 1693 1694 pwm5 { 1695 pwm5_pin: pwm5-pin { 1696 rockchip,pins = 1697 <1 RK_PB7 2 &pcfg_pull_none>; 1698 }; 1699 }; 1700 pwm6 { 1701 pwm6_pin: pwm6-pin { 1702 rockchip,pins = 1703 <3 RK_PA1 2 &pcfg_pull_none>; 1704 }; 1705 }; 1706 1707 pwm7 { 1708 pwm7_pin: pwm7-pin { 1709 rockchip,pins = 1710 <3 RK_PA2 2 &pcfg_pull_none>; 1711 }; 1712 }; 1713 1714 pwm8 { 1715 pwm8_pin: pwm8-pin { 1716 rockchip,pins = 1717 <3 RK_PD0 2 &pcfg_pull_none>; 1718 }; 1719 }; 1720 1721 pwm9 { 1722 pwm9_pin: pwm9-pin { 1723 rockchip,pins = 1724 <3 RK_PD1 2 &pcfg_pull_none>; 1725 }; 1726 }; 1727 1728 pwm10 { 1729 pwm10_pin: pwm10-pin { 1730 rockchip,pins = 1731 <3 RK_PD2 2 &pcfg_pull_none>; 1732 }; 1733 }; 1734 1735 pwm11 { 1736 pwm11_pin: pwm11-pin { 1737 rockchip,pins = 1738 <3 RK_PD3 2 &pcfg_pull_none>; 1739 }; 1740 }; 1741 1742 sdmmc0 { 1743 sdmmc0_bus4: sdmmc0-bus4 { 1744 rockchip,pins = 1745 /* sdmmc0_d0 */ 1746 <4 RK_PA2 1 &pcfg_pull_none>, 1747 /* sdmmc0_d1 */ 1748 <4 RK_PA3 1 &pcfg_pull_none>, 1749 /* sdmmc0_d2 */ 1750 <4 RK_PA4 1 &pcfg_pull_none>, 1751 /* sdmmc0_d3 */ 1752 <4 RK_PA5 1 &pcfg_pull_none>; 1753 }; 1754 sdmmc0_cmd: sdmmc0-cmd { 1755 rockchip,pins = 1756 <4 RK_PA0 1 &pcfg_pull_none>; 1757 }; 1758 sdmmc0_clk: sdmmc0-clk { 1759 rockchip,pins = 1760 <4 RK_PA1 1 &pcfg_pull_none>; 1761 }; 1762 }; 1763 1764 sdmmc1 { 1765 sdmmc1_bus4: sdmmc1-bus4 { 1766 rockchip,pins = 1767 /* sdmmc1_d0 */ 1768 <4 RK_PB0 1 &pcfg_pull_none>, 1769 /* sdmmc1_d1 */ 1770 <4 RK_PB1 1 &pcfg_pull_none>, 1771 /* sdmmc1_d2 */ 1772 <4 RK_PB2 1 &pcfg_pull_none>, 1773 /* sdmmc1_d3 */ 1774 <4 RK_PB3 1 &pcfg_pull_none>; 1775 }; 1776 1777 sdmmc1_cmd: sdmmc1-cmd { 1778 rockchip,pins = 1779 <4 RK_PA6 1 &pcfg_pull_none>; 1780 }; 1781 1782 sdmmc1_clk: sdmmc1-clk { 1783 rockchip,pins = 1784 <4 RK_PA7 1 &pcfg_pull_none>; 1785 }; 1786 }; 1787 1788 spi0 { 1789 spi0_mosi: spi0-mosi { 1790 rockchip,pins = 1791 <1 RK_PB4 1 &pcfg_pull_up_4ma>; 1792 }; 1793 1794 spi0_miso: spi0-miso { 1795 rockchip,pins = 1796 <1 RK_PB5 1 &pcfg_pull_up_4ma>; 1797 }; 1798 1799 spi0_csn: spi0-csn { 1800 rockchip,pins = 1801 <1 RK_PB6 1 &pcfg_pull_up_4ma>; 1802 }; 1803 1804 spi0_clk: spi0-clk { 1805 rockchip,pins = 1806 <1 RK_PB7 1 &pcfg_pull_up_4ma>; 1807 }; 1808 1809 spi0_mosi_hs: spi0-mosi-hs { 1810 rockchip,pins = 1811 <1 RK_PB4 1 &pcfg_pull_up_8ma>; 1812 }; 1813 1814 spi0_miso_hs: spi0-miso-hs { 1815 rockchip,pins = 1816 <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1817 }; 1818 1819 spi0_csn_hs: spi0-csn-hs { 1820 rockchip,pins = 1821 <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1822 }; 1823 1824 spi0_clk_hs: spi0-clk-hs { 1825 rockchip,pins = 1826 <1 RK_PB7 1 &pcfg_pull_up_8ma>; 1827 }; 1828 }; 1829 1830 spi1 { 1831 spi1_clk: spi1-clk { 1832 rockchip,pins = 1833 <4 RK_PB4 2 &pcfg_pull_up_4ma>; 1834 }; 1835 1836 spi1_mosi: spi1-mosi { 1837 rockchip,pins = 1838 <4 RK_PB5 2 &pcfg_pull_up_4ma>; 1839 }; 1840 1841 spi1_csn0: spi1-csn0 { 1842 rockchip,pins = 1843 <4 RK_PB6 2 &pcfg_pull_up_4ma>; 1844 }; 1845 1846 spi1_miso: spi1-miso { 1847 rockchip,pins = 1848 <4 RK_PB7 2 &pcfg_pull_up_4ma>; 1849 }; 1850 1851 spi1_csn1: spi1-csn1 { 1852 rockchip,pins = 1853 <4 RK_PC0 2 &pcfg_pull_up_4ma>; 1854 }; 1855 1856 spi1_clk_hs: spi1-clk-hs { 1857 rockchip,pins = 1858 <4 RK_PB4 2 &pcfg_pull_up_8ma>; 1859 }; 1860 1861 spi1_mosi_hs: spi1-mosi-hs { 1862 rockchip,pins = 1863 <4 RK_PB5 2 &pcfg_pull_up_8ma>; 1864 }; 1865 1866 spi1_csn0_hs: spi1-csn0-hs { 1867 rockchip,pins = 1868 <4 RK_PB6 2 &pcfg_pull_up_8ma>; 1869 }; 1870 1871 spi1_miso_hs: spi1-miso-hs { 1872 rockchip,pins = 1873 <4 RK_PB7 2 &pcfg_pull_up_8ma>; 1874 }; 1875 1876 spi1_csn1_hs: spi1-csn1-hs { 1877 rockchip,pins = 1878 <4 RK_PC0 2 &pcfg_pull_up_8ma>; 1879 }; 1880 }; 1881 1882 spi1m1 { 1883 spi1m1_clk: spi1m1-clk { 1884 rockchip,pins = 1885 <3 RK_PC7 3 &pcfg_pull_up_4ma>; 1886 }; 1887 1888 spi1m1_mosi: spi1m1-mosi { 1889 rockchip,pins = 1890 <3 RK_PD0 3 &pcfg_pull_up_4ma>; 1891 }; 1892 1893 spi1m1_csn0: spi1m1-csn0 { 1894 rockchip,pins = 1895 <3 RK_PD1 3 &pcfg_pull_up_4ma>; 1896 }; 1897 1898 spi1m1_miso: spi1m1-miso { 1899 rockchip,pins = 1900 <3 RK_PD2 3 &pcfg_pull_up_4ma>; 1901 }; 1902 1903 spi1m1_csn1: spi1m1-csn1 { 1904 rockchip,pins = 1905 <3 RK_PD3 3 &pcfg_pull_up_4ma>; 1906 }; 1907 1908 spi1m1_clk_hs: spi1m1-clk-hs { 1909 rockchip,pins = 1910 <3 RK_PC7 3 &pcfg_pull_up_8ma>; 1911 }; 1912 1913 spi1m1_mosi_hs: spi1m1-mosi-hs { 1914 rockchip,pins = 1915 <3 RK_PD0 3 &pcfg_pull_up_8ma>; 1916 }; 1917 1918 spi1m1_csn0_hs: spi1m1-csn0-hs { 1919 rockchip,pins = 1920 <3 RK_PD1 3 &pcfg_pull_up_8ma>; 1921 }; 1922 1923 spi1m1_miso_hs: spi1m1-miso-hs { 1924 rockchip,pins = 1925 <3 RK_PD2 3 &pcfg_pull_up_8ma>; 1926 }; 1927 1928 spi1m1_csn1_hs: spi1m1-csn1-hs { 1929 rockchip,pins = 1930 <3 RK_PD3 3 &pcfg_pull_up_8ma>; 1931 }; 1932 }; 1933 1934 spi2m0 { 1935 spi2m0_miso: spi2m0-miso { 1936 rockchip,pins = 1937 <1 RK_PA6 2 &pcfg_pull_up_4ma>; 1938 }; 1939 1940 spi2m0_clk: spi2m0-clk { 1941 rockchip,pins = 1942 <1 RK_PA7 2 &pcfg_pull_up_4ma>; 1943 }; 1944 1945 spi2m0_mosi: spi2m0-mosi { 1946 rockchip,pins = 1947 <1 RK_PB0 2 &pcfg_pull_up_4ma>; 1948 }; 1949 1950 spi2m0_csn: spi2m0-csn { 1951 rockchip,pins = 1952 <1 RK_PB1 2 &pcfg_pull_up_4ma>; 1953 }; 1954 1955 spi2m0_miso_hs: spi2m0-miso-hs { 1956 rockchip,pins = 1957 <1 RK_PA6 2 &pcfg_pull_none>; 1958 }; 1959 1960 spi2m0_clk_hs: spi2m0-clk-hs { 1961 rockchip,pins = 1962 <1 RK_PA7 2 &pcfg_pull_none>; 1963 }; 1964 1965 spi2m0_mosi_hs: spi2m0-mosi-hs { 1966 rockchip,pins = 1967 <1 RK_PB0 2 &pcfg_pull_none>; 1968 }; 1969 1970 spi2m0_csn_hs: spi2m0-csn-hs { 1971 rockchip,pins = 1972 <1 RK_PB1 2 &pcfg_pull_none>; 1973 }; 1974 }; 1975 1976 spi2m1 { 1977 spi2m1_miso: spi2m1-miso { 1978 rockchip,pins = 1979 <2 RK_PA4 3 &pcfg_pull_up_4ma>; 1980 }; 1981 1982 spi2m1_clk: spi2m1-clk { 1983 rockchip,pins = 1984 <2 RK_PA5 3 &pcfg_pull_up_4ma>; 1985 }; 1986 1987 spi2m1_mosi: spi2m1-mosi { 1988 rockchip,pins = 1989 <2 RK_PA6 3 &pcfg_pull_up_4ma>; 1990 }; 1991 1992 spi2m1_csn: spi2m1-csn { 1993 rockchip,pins = 1994 <2 RK_PA7 3 &pcfg_pull_up_4ma>; 1995 }; 1996 1997 spi2m1_miso_hs: spi2m1-miso-hs { 1998 rockchip,pins = 1999 <2 RK_PA4 3 &pcfg_pull_up_8ma>; 2000 }; 2001 2002 spi2m1_clk_hs: spi2m1-clk-hs { 2003 rockchip,pins = 2004 <2 RK_PA5 3 &pcfg_pull_up_8ma>; 2005 }; 2006 2007 spi2m1_mosi_hs: spi2m1-mosi-hs { 2008 rockchip,pins = 2009 <2 RK_PA6 3 &pcfg_pull_up_8ma>; 2010 }; 2011 2012 spi2m1_csn_hs: spi2m1-csn-hs { 2013 rockchip,pins = 2014 <2 RK_PA7 3 &pcfg_pull_up_8ma>; 2015 }; 2016 }; 2017 2018 uart0 { 2019 uart0_xfer: uart0-xfer { 2020 rockchip,pins = 2021 /* uart0_rx */ 2022 <0 RK_PB3 1 &pcfg_pull_none>, 2023 /* uart0_tx */ 2024 <0 RK_PB2 1 &pcfg_pull_none>; 2025 }; 2026 2027 uart0_cts: uart0-cts { 2028 rockchip,pins = 2029 <0 RK_PB4 1 &pcfg_pull_none>; 2030 }; 2031 2032 uart0_rts: uart0-rts { 2033 rockchip,pins = 2034 <0 RK_PB5 1 &pcfg_pull_none>; 2035 }; 2036 }; 2037 2038 uart1 { 2039 uart1m0_xfer: uart1m0-xfer { 2040 rockchip,pins = 2041 /* uart1_rxm0 */ 2042 <4 RK_PB0 2 &pcfg_pull_none>, 2043 /* uart1_txm0 */ 2044 <4 RK_PB1 2 &pcfg_pull_none>; 2045 }; 2046 2047 uart1m1_xfer: uart1m1-xfer { 2048 rockchip,pins = 2049 /* uart1_rxm1 */ 2050 <1 RK_PB4 3 &pcfg_pull_none>, 2051 /* uart1_txm1 */ 2052 <1 RK_PB5 3 &pcfg_pull_none>; 2053 }; 2054 2055 uart1_cts: uart1-cts { 2056 rockchip,pins = 2057 <4 RK_PB2 2 &pcfg_pull_none>; 2058 }; 2059 2060 uart1_rts: uart1-rts { 2061 rockchip,pins = 2062 <4 RK_PB3 2 &pcfg_pull_none>; 2063 }; 2064 }; 2065 2066 uart2 { 2067 uart2m0_xfer: uart2m0-xfer { 2068 rockchip,pins = 2069 /* uart2_rxm0 */ 2070 <4 RK_PA3 2 &pcfg_pull_none>, 2071 /* uart2_txm0 */ 2072 <4 RK_PA2 2 &pcfg_pull_none>; 2073 }; 2074 2075 uart2m1_xfer: uart2m1-xfer { 2076 rockchip,pins = 2077 /* uart2_rxm1 */ 2078 <2 RK_PD1 2 &pcfg_pull_none>, 2079 /* uart2_txm1 */ 2080 <2 RK_PD0 2 &pcfg_pull_none>; 2081 }; 2082 2083 uart2m2_xfer: uart2m2-xfer { 2084 rockchip,pins = 2085 /* uart2_rxm2 */ 2086 <3 RK_PA4 2 &pcfg_pull_none>, 2087 /* uart2_txm2 */ 2088 <3 RK_PA3 2 &pcfg_pull_none>; 2089 }; 2090 }; 2091 2092 uart3 { 2093 uart3m0_xfer: uart3m0-xfer { 2094 rockchip,pins = 2095 /* uart3_rxm0 */ 2096 <0 RK_PC5 2 &pcfg_pull_none>, 2097 /* uart3_txm0 */ 2098 <0 RK_PC4 2 &pcfg_pull_none>; 2099 }; 2100 2101 uart3_ctsm0: uart3-ctsm0 { 2102 rockchip,pins = 2103 <0 RK_PC7 2 &pcfg_pull_none>; 2104 }; 2105 2106 uart3_rtsm0: uart3-rtsm0 { 2107 rockchip,pins = 2108 <0 RK_PD0 2 &pcfg_pull_none>; 2109 }; 2110 }; 2111 2112 uart4 { 2113 uart4_xfer: uart4-xfer { 2114 rockchip,pins = 2115 /* uart4_rx */ 2116 <4 RK_PB4 1 &pcfg_pull_none>, 2117 /* uart4_tx */ 2118 <4 RK_PB5 1 &pcfg_pull_none>; 2119 }; 2120 2121 uart4_cts: uart4-cts { 2122 rockchip,pins = 2123 <4 RK_PB6 1 &pcfg_pull_none>; 2124 }; 2125 2126 uart4_rts: uart4-rts { 2127 rockchip,pins = 2128 <4 RK_PB7 1 &pcfg_pull_none>; 2129 }; 2130 }; 2131 2132 uart5 { 2133 uart5_xfer: uart5-xfer { 2134 rockchip,pins = 2135 /* uart5_rx */ 2136 <3 RK_PC3 1 &pcfg_pull_none>, 2137 /* uart5_tx */ 2138 <3 RK_PC2 1 &pcfg_pull_none>; 2139 }; 2140 }; 2141 2142 uart6 { 2143 uart6_xfer: uart6-xfer { 2144 rockchip,pins = 2145 /* uart6_rx */ 2146 <3 RK_PC5 1 &pcfg_pull_none>, 2147 /* uart6_tx */ 2148 <3 RK_PC4 1 &pcfg_pull_none>; 2149 }; 2150 }; 2151 2152 uart7 { 2153 uart7_xfer: uart7-xfer { 2154 rockchip,pins = 2155 /* uart7_rx */ 2156 <3 RK_PC7 1 &pcfg_pull_none>, 2157 /* uart7_tx */ 2158 <3 RK_PC6 1 &pcfg_pull_none>; 2159 }; 2160 }; 2161 2162 tsadc { 2163 tsadc_otp_gpio: tsadc-otp-gpio { 2164 rockchip,pins = 2165 <0 RK_PA6 0 &pcfg_pull_none>; 2166 }; 2167 2168 tsadc_otp_out: tsadc-otp-out { 2169 rockchip,pins = 2170 <0 RK_PA6 2 &pcfg_pull_none>; 2171 }; 2172 }; 2173 }; 2174}; 2175