1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 3 4#include <dt-bindings/clock/rk1808-cru.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8#include <dt-bindings/power/rk1808-power.h> 9 10/ { 11 compatible = "rockchip,rk1808"; 12 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 serial4 = &uart4; 29 serial5 = &uart5; 30 serial6 = &uart6; 31 serial7 = &uart7; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35", "arm,armv8"; 44 reg = <0x0 0x0>; 45 clocks = <&cru ARMCLK>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a35", "arm,armv8"; 51 reg = <0x0 0x1>; 52 clocks = <&cru ARMCLK>; 53 }; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>; 61 }; 62 63 dmc: dmc { 64 compatible = "rockchip,rk1808-dmc"; 65 }; 66 67 gmac_clkin: external-gmac-clock { 68 compatible = "fixed-clock"; 69 clock-frequency = <125000000>; 70 clock-output-names = "gmac_clkin"; 71 #clock-cells = <0>; 72 }; 73 74 timer { 75 compatible = "arm,armv8-timer"; 76 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 77 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 78 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 79 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 80 arm,no-tick-in-suspend; 81 }; 82 83 xin24m: xin24m { 84 compatible = "fixed-clock"; 85 clock-frequency = <24000000>; 86 clock-output-names = "xin24m"; 87 #clock-cells = <0>; 88 }; 89 90 xin32k: xin32k { 91 compatible = "fixed-clock"; 92 clock-frequency = <32768>; 93 clock-output-names = "xin32k"; 94 #clock-cells = <0>; 95 }; 96 97 usbdrd3: usb { 98 compatible = "rockchip,rk1808-dwc3"; 99 clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, 100 <&cru SCLK_USB3_OTG0_SUSPEND>; 101 clock-names = "ref_clk", "bus_clk", 102 "suspend_clk"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 status = "disabled"; 107 108 usbdrd_dwc3: dwc3@fd000000 { 109 compatible = "snps,dwc3"; 110 reg = <0x0 0xfd000000 0x0 0x200000>; 111 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 112 dr_mode = "otg"; 113 phys = <&u2phy_otg>; 114 phy-names = "usb2-phy"; 115 phy_type = "utmi_wide"; 116 snps,dis_enblslpm_quirk; 117 snps,dis-u2-freeclk-exists-quirk; 118 snps,dis_u2_susphy_quirk; 119 snps,dis-del-phy-power-chg-quirk; 120 snps,tx-ipgap-linecheck-dis-quirk; 121 status = "disabled"; 122 }; 123 }; 124 125 grf: syscon@fe000000 { 126 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; 127 reg = <0x0 0xfe000000 0x0 0x1000>; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 131 io_domains: io-domains { 132 compatible = "rockchip,rk1808-io-voltage-domain"; 133 status = "disabled"; 134 }; 135 136 rgb: rgb { 137 compatible = "rockchip,rk1808-rgb"; 138 status = "disabled"; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 port@0 { 145 reg = <0>; 146 147 rgb_in_vop_lite: endpoint { 148 remote-endpoint = <&vop_lite_out_rgb>; 149 }; 150 }; 151 }; 152 }; 153 }; 154 155 usb2phy_grf: syscon@fe010000 { 156 compatible = "rockchip,rk1808-usb2phy-grf", "syscon", 157 "simple-mfd"; 158 reg = <0x0 0xfe010000 0x0 0x8000>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 162 u2phy: usb2-phy@100 { 163 compatible = "rockchip,rk1808-usb2phy"; 164 reg = <0x100 0x10>; 165 clocks = <&cru SCLK_USBPHY_REF>; 166 clock-names = "phyclk"; 167 #clock-cells = <0>; 168 assigned-clocks = <&cru USB480M>; 169 assigned-clock-parents = <&u2phy>; 170 clock-output-names = "usb480m_phy"; 171 status = "disabled"; 172 173 u2phy_host: host-port { 174 #phy-cells = <0>; 175 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "linestate"; 177 status = "disabled"; 178 }; 179 180 u2phy_otg: otg-port { 181 #phy-cells = <0>; 182 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "otg-bvalid", "otg-id", 186 "linestate"; 187 status = "disabled"; 188 }; 189 }; 190 }; 191 192 pmugrf: syscon@fe020000 { 193 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; 194 reg = <0x0 0xfe020000 0x0 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 198 pmu_io_domains: io-domains { 199 compatible = "rockchip,rk1808-pmu-io-voltage-domain"; 200 status = "disabled"; 201 }; 202 }; 203 204 qos_npu: qos@fe850000 { 205 compatible = "syscon"; 206 reg = <0x0 0xfe850000 0x0 0x20>; 207 }; 208 209 qos_pcie: qos@fe880000 { 210 compatible = "syscon"; 211 reg = <0x0 0xfe880000 0x0 0x20>; 212 }; 213 214 qos_isp: qos@fe8a0000 { 215 compatible = "syscon"; 216 reg = <0x0 0xfe8a0000 0x0 0x20>; 217 }; 218 219 qos_rga_rd: qos@fe8a0080 { 220 compatible = "syscon"; 221 reg = <0x0 0xfe8a0080 0x0 0x20>; 222 }; 223 224 qos_rga_wr: qos@fe8a0100 { 225 compatible = "syscon"; 226 reg = <0x0 0xfe8a0100 0x0 0x20>; 227 }; 228 229 qos_vip: qos@fe8a0180 { 230 compatible = "syscon"; 231 reg = <0x0 0xfe8a0180 0x0 0x20>; 232 }; 233 234 qos_vop_dma: qos@fe8b0000 { 235 compatible = "syscon"; 236 reg = <0x0 0xfe8b0000 0x0 0x20>; 237 }; 238 239 qos_vop_lite: qos@fe8b0080 { 240 compatible = "syscon"; 241 reg = <0x0 0xfe8b0080 0x0 0x20>; 242 }; 243 244 qos_vpu: qos@fe8cc000 { 245 compatible = "syscon"; 246 reg = <0x0 0xfe8c000 0x0 0x20>; 247 }; 248 249 sram: sram@fec00000 { 250 compatible = "mmio-sram"; 251 reg = <0x0 0xfec00000 0x0 0x200000>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 ranges = <0 0x0 0xfec00000 0x200000>; 255 /* reserved for ddr dvfs and system suspend/resume */ 256 ddr-sram@0 { 257 reg = <0x0 0x8000>; 258 }; 259 /* reserved for vad audio buffer */ 260 vad_sram: vad-sram@1c0000 { 261 reg = <0x1c0000 0x40000>; 262 }; 263 }; 264 265 gic: interrupt-controller@ff100000 { 266 compatible = "arm,gic-v3"; 267 #interrupt-cells = <3>; 268 #address-cells = <2>; 269 #size-cells = <2>; 270 ranges; 271 interrupt-controller; 272 273 reg = <0x0 0xff100000 0 0x10000>, /* GICD */ 274 <0x0 0xff140000 0 0xc0000>, /* GICR */ 275 <0x0 0xff300000 0 0x10000>, /* GICC */ 276 <0x0 0xff310000 0 0x10000>, /* GICH */ 277 <0x0 0xff320000 0 0x10000>; /* GICV */ 278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 279 its: interrupt-controller@ff120000 { 280 compatible = "arm,gic-v3-its"; 281 msi-controller; 282 reg = <0x0 0xff120000 0x0 0x20000>; 283 }; 284 }; 285 286 cru: clock-controller@ff350000 { 287 compatible = "rockchip,rk1808-cru"; 288 reg = <0x0 0xff350000 0x0 0x5000>; 289 rockchip,grf = <&grf>; 290 #clock-cells = <1>; 291 #reset-cells = <1>; 292 293 assigned-clocks = 294 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 295 <&cru PLL_PPLL>, <&cru ARMCLK>, 296 <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 297 <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 298 <&cru LSCLK_BUS_PRE>; 299 assigned-clock-rates = 300 <1200000000>, <1000000000>, 301 <416000000>, <816000000>, 302 <200000000>, <100000000>, 303 <300000000>, <200000000>, 304 <100000000>; 305 }; 306 307 mipi_dphy: mipi-dphy@ff370000 { 308 compatible = "rockchip,rk1808-mipi-dphy"; 309 reg = <0x0 0xff370000 0x0 0x500>; 310 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 311 clock-names = "ref", "pclk"; 312 clock-output-names = "mipi_dphy_pll"; 313 #clock-cells = <0>; 314 resets = <&cru SRST_MIPIDSIPHY_P>; 315 reset-names = "apb"; 316 #phy-cells = <0>; 317 rockchip,grf = <&grf>; 318 status = "disabled"; 319 }; 320 321 tsadc: tsadc@ff3a0000 { 322 compatible = "rockchip,rk1808-tsadc"; 323 reg = <0x0 0xff3a0000 0x0 0x100>; 324 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 325 rockchip,grf = <&grf>; 326 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 327 clock-names = "tsadc", "apb_pclk"; 328 assigned-clocks = <&cru SCLK_TSADC>; 329 assigned-clock-rates = <50000>; 330 resets = <&cru SRST_TSADC>; 331 reset-names = "tsadc-apb"; 332 #thermal-sensor-cells = <1>; 333 rockchip,hw-tshut-temp = <120000>; 334 status = "disabled"; 335 }; 336 337 pwm0: pwm@ff3d0000 { 338 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 339 reg = <0x0 0xff3d0000 0x0 0x10>; 340 #pwm-cells = <3>; 341 pinctrl-names = "active"; 342 pinctrl-0 = <&pwm0_pin>; 343 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 344 clock-names = "pwm", "pclk"; 345 status = "disabled"; 346 }; 347 348 pwm1: pwm@ff3d0010 { 349 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 350 reg = <0x0 0xff3d0010 0x0 0x10>; 351 #pwm-cells = <3>; 352 pinctrl-names = "active"; 353 pinctrl-0 = <&pwm1_pin>; 354 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 355 clock-names = "pwm", "pclk"; 356 status = "disabled"; 357 }; 358 359 pwm2: pwm@ff3d0020 { 360 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 361 reg = <0x0 0xff3d0020 0x0 0x10>; 362 #pwm-cells = <3>; 363 pinctrl-names = "active"; 364 pinctrl-0 = <&pwm2_pin>; 365 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 366 clock-names = "pwm", "pclk"; 367 status = "disabled"; 368 }; 369 370 pwm3: pwm@ff3d0030 { 371 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 372 reg = <0x0 0xff3d0030 0x0 0x10>; 373 #pwm-cells = <3>; 374 pinctrl-names = "active"; 375 pinctrl-0 = <&pwm3_pin>; 376 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 377 clock-names = "pwm", "pclk"; 378 status = "disabled"; 379 }; 380 381 pwm4: pwm@ff3d8000 { 382 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 383 reg = <0x0 0xff3d8000 0x0 0x10>; 384 #pwm-cells = <3>; 385 pinctrl-names = "active"; 386 pinctrl-0 = <&pwm4_pin>; 387 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 388 clock-names = "pwm", "pclk"; 389 status = "disabled"; 390 }; 391 392 pwm5: pwm@ff3d8010 { 393 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 394 reg = <0x0 0xff3d8010 0x0 0x10>; 395 #pwm-cells = <3>; 396 pinctrl-names = "active"; 397 pinctrl-0 = <&pwm5_pin>; 398 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 399 clock-names = "pwm", "pclk"; 400 status = "disabled"; 401 }; 402 403 pwm6: pwm@ff3d8020 { 404 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 405 reg = <0x0 0xff3d8020 0x0 0x10>; 406 #pwm-cells = <3>; 407 pinctrl-names = "active"; 408 pinctrl-0 = <&pwm6_pin>; 409 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 410 clock-names = "pwm", "pclk"; 411 status = "disabled"; 412 }; 413 414 pwm7: pwm@ff3d8030 { 415 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 416 reg = <0x0 0xff3d8030 0x0 0x10>; 417 #pwm-cells = <3>; 418 pinctrl-names = "active"; 419 pinctrl-0 = <&pwm7_pin>; 420 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 421 clock-names = "pwm", "pclk"; 422 status = "disabled"; 423 }; 424 425 pmu: power-management@ff3e0000 { 426 compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; 427 reg = <0x0 0xff3e0000 0x0 0x1000>; 428 429 power: power-controller { 430 compatible = "rockchip,rk1808-power-controller"; 431 #power-domain-cells = <1>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 status = "disabled"; 435 436 /* These power domains are grouped by VD_NPU */ 437 pd_npu@RK1808_VD_NPU { 438 reg = <RK1808_VD_NPU>; 439 clocks = <&cru SCLK_NPU>, 440 <&cru ACLK_NPU>, 441 <&cru HCLK_NPU>; 442 pm_qos = <&qos_npu>; 443 }; 444 445 /* These power domains are grouped by VD_LOGIC */ 446 pd_pcie@RK1808_PD_PCIE { 447 reg = <RK1808_PD_PCIE>; 448 clocks = <&cru HSCLK_PCIE>, 449 <&cru LSCLK_PCIE>, 450 <&cru ACLK_PCIE>, 451 <&cru ACLK_PCIE_MST>, 452 <&cru ACLK_PCIE_SLV>, 453 <&cru PCLK_PCIE>, 454 <&cru SCLK_PCIE_AUX>; 455 pm_qos = <&qos_pcie>; 456 }; 457 pd_vpu@RK1808_PD_VPU { 458 reg = <RK1808_PD_VPU>; 459 clocks = <&cru ACLK_VPU>, 460 <&cru HCLK_VPU>; 461 pm_qos = <&qos_vpu>; 462 }; 463 pd_vio@RK1808_PD_VIO { 464 reg = <RK1808_PD_VIO>; 465 clocks = <&cru HSCLK_VIO>, 466 <&cru LSCLK_VIO>, 467 <&cru ACLK_VOPRAW>, 468 <&cru HCLK_VOPRAW>, 469 <&cru ACLK_VOPLITE>, 470 <&cru HCLK_VOPLITE>, 471 <&cru PCLK_DSI_TX>, 472 <&cru PCLK_CSI_TX>, 473 <&cru ACLK_RGA>, 474 <&cru HCLK_RGA>, 475 <&cru ACLK_ISP>, 476 <&cru HCLK_ISP>, 477 <&cru ACLK_CIF>, 478 <&cru HCLK_CIF>, 479 <&cru PCLK_CSI2HOST>, 480 <&cru DCLK_VOPRAW>, 481 <&cru DCLK_VOPLITE>; 482 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 483 <&qos_isp>, <&qos_vip>, 484 <&qos_vop_dma>, <&qos_vop_lite>; 485 }; 486 }; 487 }; 488 489 i2c0: i2c@ff410000 { 490 compatible = "rockchip,rk3399-i2c"; 491 reg = <0x0 0xff410000 0x0 0x1000>; 492 clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; 493 clock-names = "i2c", "pclk"; 494 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&i2c0_xfer>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 dmac: dmac@ff4e0000 { 503 compatible = "arm,pl330", "arm,primecell"; 504 reg = <0x0 0xff4e0000 0x0 0x4000>; 505 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cru ACLK_DMAC>; 507 clock-names = "apb_pclk"; 508 #dma-cells = <1>; 509 peripherals-req-type-burst; 510 }; 511 512 uart0: serial@ff430000 { 513 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 514 reg = <0x0 0xff430000 0x0 0x100>; 515 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 517 clock-names = "baudclk", "apb_pclk"; 518 reg-shift = <2>; 519 reg-io-width = <4>; 520 dmas = <&dmac 0>, <&dmac 1>; 521 dma-names = "tx", "rx"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 524 status = "disabled"; 525 }; 526 527 i2c1: i2c@ff500000 { 528 compatible = "rockchip,rk3399-i2c"; 529 reg = <0x0 0xff500000 0x0 0x1000>; 530 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 531 clock-names = "i2c", "pclk"; 532 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&i2c1_xfer>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 i2c2: i2c@ff504000 { 541 compatible = "rockchip,rk3399-i2c"; 542 reg = <0x0 0xff504000 0x0 0x1000>; 543 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 544 clock-names = "i2c", "pclk"; 545 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&i2c2m0_xfer>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 i2c3: i2c@ff508000 { 554 compatible = "rockchip,rk3399-i2c"; 555 reg = <0x0 0xff508000 0x0 0x1000>; 556 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 557 clock-names = "i2c", "pclk"; 558 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2c3_xfer>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 566 i2c4: i2c@ff50c000 { 567 compatible = "rockchip,rk3399-i2c"; 568 reg = <0x0 0xff50c000 0x0 0x1000>; 569 clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; 570 clock-names = "i2c", "pclk"; 571 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2c4_xfer>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 }; 578 579 i2c5: i2c@ff510000 { 580 compatible = "rockchip,rk3399-i2c"; 581 reg = <0x0 0xff100000 0x0 0x1000>; 582 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 583 clock-names = "i2c", "pclk"; 584 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&i2c5_xfer>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 spi0: spi@ff520000 { 593 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 594 reg = <0x0 0xff520000 0x0 0x1000>; 595 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 599 clock-names = "spiclk", "apb_pclk"; 600 dmas = <&dmac 10>, <&dmac 11>; 601 dma-names = "tx", "rx"; 602 pinctrl-names = "default", "high_speed"; 603 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 604 pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; 605 status = "disabled"; 606 }; 607 608 spi1: spi@ff530000 { 609 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 610 reg = <0x0 0xff530000 0x0 0x1000>; 611 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 615 clock-names = "spiclk", "apb_pclk"; 616 dmas = <&dmac 12>, <&dmac 13>; 617 dma-names = "tx", "rx"; 618 pinctrl-names = "default", "high_speed"; 619 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 620 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; 621 status = "disabled"; 622 }; 623 624 uart1: serial@ff540000 { 625 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 626 reg = <0x0 0xff540000 0x0 0x100>; 627 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 629 clock-names = "baudclk", "apb_pclk"; 630 reg-shift = <2>; 631 reg-io-width = <4>; 632 dmas = <&dmac 2>, <&dmac 3>; 633 dma-names = "tx", "rx"; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>; 636 status = "disabled"; 637 }; 638 639 uart2: serial@ff550000 { 640 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 641 reg = <0x0 0xff550000 0x0 0x100>; 642 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 644 clock-names = "baudclk", "apb_pclk"; 645 reg-shift = <2>; 646 reg-io-width = <4>; 647 dmas = <&dmac 4>, <&dmac 5>; 648 dma-names = "tx", "rx"; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&uart2m0_xfer>; 651 status = "disabled"; 652 }; 653 654 uart3: serial@ff560000 { 655 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 656 reg = <0x0 0xff560000 0x0 0x100>; 657 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 659 clock-names = "baudclk", "apb_pclk"; 660 reg-shift = <2>; 661 reg-io-width = <4>; 662 dmas = <&dmac 6>, <&dmac 7>; 663 dma-names = "tx", "rx"; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>; 666 status = "disabled"; 667 }; 668 669 uart4: serial@ff570000 { 670 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 671 reg = <0x0 0xff570000 0x0 0x100>; 672 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 674 clock-names = "baudclk", "apb_pclk"; 675 reg-shift = <2>; 676 reg-io-width = <4>; 677 dmas = <&dmac 8>, <&dmac 9>; 678 dma-names = "tx", "rx"; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 681 status = "disabled"; 682 }; 683 684 spi2: spi@ff580000 { 685 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 686 reg = <0x0 0xff580000 0x0 0x1000>; 687 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 691 clock-names = "spiclk", "apb_pclk"; 692 dmas = <&dmac 14>, <&dmac 15>; 693 dma-names = "tx", "rx"; 694 pinctrl-names = "default", "high_speed"; 695 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; 696 pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; 697 status = "disabled"; 698 }; 699 700 uart5: serial@ff5a0000 { 701 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 702 reg = <0x0 0xff5a0000 0x0 0x100>; 703 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 705 clock-names = "baudclk", "apb_pclk"; 706 reg-shift = <2>; 707 reg-io-width = <4>; 708 dmas = <&dmac 25>, <&dmac 26>; 709 dma-names = "tx", "rx"; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&uart5_xfer>; 712 status = "disabled"; 713 }; 714 715 uart6: serial@ff5b0000 { 716 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 717 reg = <0x0 0xff5b0000 0x0 0x100>; 718 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 720 clock-names = "baudclk", "apb_pclk"; 721 reg-shift = <2>; 722 reg-io-width = <4>; 723 dmas = <&dmac 27>, <&dmac 28>; 724 dma-names = "tx", "rx"; 725 pinctrl-names = "default"; 726 pinctrl-0 = <&uart6_xfer>; 727 status = "disabled"; 728 }; 729 730 uart7: serial@ff5c0000 { 731 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 732 reg = <0x0 0xff5c0000 0x0 0x100>; 733 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 735 clock-names = "baudclk", "apb_pclk"; 736 reg-shift = <2>; 737 reg-io-width = <4>; 738 dmas = <&dmac 29>, <&dmac 30>; 739 dma-names = "tx", "rx"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&uart7_xfer>; 742 status = "disabled"; 743 }; 744 745 vop_lite: vop@ffb00000 { 746 compatible = "rockchip,rk1808-vop-lit"; 747 reg = <0x0 0xffb00000 0x0 0x200>; 748 reg-names = "regs"; 749 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&cru ACLK_VOPLITE>, <&cru DCLK_VOPLITE>, 751 <&cru HCLK_VOPLITE>; 752 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 753 power-domains = <&power RK1808_PD_VIO>; 754 iommus = <&vopl_mmu>; 755 status = "disabled"; 756 757 vop_lite_out: port { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 vop_lite_out_dsi: endpoint@0 { 762 reg = <0>; 763 remote-endpoint = <&dsi_in_vop_lite>; 764 }; 765 766 vop_lite_out_rgb: endpoint@1 { 767 reg = <1>; 768 remote-endpoint = <&rgb_in_vop_lite>; 769 }; 770 }; 771 }; 772 773 vopl_mmu: iommu@ffb00f00 { 774 compatible = "rockchip,iommu"; 775 reg = <0x0 0xffb00f00 0x0 0x100>; 776 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "vopl_mmu"; 778 clocks = <&cru ACLK_VOPLITE>, <&cru HCLK_VOPLITE>; 779 clock-names = "aclk", "hclk"; 780 power-domains = <&power RK1808_PD_VIO>; 781 #iommu-cells = <0>; 782 status = "disabled"; 783 }; 784 785 vop_raw: vop@ffb40000 { 786 compatible = "rockchip,rk1808-vop-raw"; 787 reg = <0x0 0xffb40000 0x0 0x500>; 788 reg-names = "regs"; 789 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&cru ACLK_VOPRAW>, <&cru DCLK_VOPRAW>, 791 <&cru HCLK_VOPRAW>; 792 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 793 power-domains = <&power RK1808_PD_VIO>; 794 iommus = <&vopr_mmu>; 795 status = "disabled"; 796 797 vop_raw_out: port { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 vop_raw_out_csi: endpoint@0 { 802 reg = <0>; 803 remote-endpoint = <&csi_in_vop_raw>; 804 }; 805 }; 806 }; 807 808 vopr_mmu: iommu@ffb40f00 { 809 compatible = "rockchip,iommu"; 810 reg = <0x0 0xffb40f00 0x0 0x100>; 811 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 812 interrupt-names = "vopr_mmu"; 813 clocks = <&cru ACLK_VOPRAW>, <&cru HCLK_VOPRAW>; 814 clock-names = "aclk", "hclk"; 815 power-domains = <&power RK1808_PD_VIO>; 816 #iommu-cells = <0>; 817 status = "disabled"; 818 }; 819 820 pwm8: pwm@ff5d0000 { 821 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 822 reg = <0x0 0xff5d0000 0x0 0x10>; 823 #pwm-cells = <3>; 824 pinctrl-names = "active"; 825 pinctrl-0 = <&pwm8_pin>; 826 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 827 clock-names = "pwm", "pclk"; 828 status = "disabled"; 829 }; 830 831 pwm9: pwm@fff5d0010 { 832 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 833 reg = <0x0 0xff5d0010 0x0 0x10>; 834 #pwm-cells = <3>; 835 pinctrl-names = "active"; 836 pinctrl-0 = <&pwm9_pin>; 837 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 838 clock-names = "pwm", "pclk"; 839 status = "disabled"; 840 }; 841 842 pwm10: pwm@ff5d0020 { 843 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 844 reg = <0x0 0xff5d0020 0x0 0x10>; 845 #pwm-cells = <3>; 846 pinctrl-names = "active"; 847 pinctrl-0 = <&pwm10_pin>; 848 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 849 clock-names = "pwm", "pclk"; 850 status = "disabled"; 851 }; 852 853 pwm11: pwm@ff5d0030 { 854 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 855 reg = <0x0 0xff5d0030 0x0 0x10>; 856 #pwm-cells = <3>; 857 pinctrl-names = "active"; 858 pinctrl-0 = <&pwm11_pin>; 859 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 860 clock-names = "pwm", "pclk"; 861 status = "disabled"; 862 }; 863 864 crypto: crypto@ff630000 { 865 compatible = "rockchip,rk1808-crypto"; 866 reg = <0x0 0xff630000 0x0 0x10000>; 867 clock-names = "sclk_crypto", "sclk_crypto_apk"; 868 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 869 clock-frequency = <200000000>, <300000000>; 870 status = "disabled"; 871 }; 872 873 i2s0: i2s@ff7e0000 { 874 compatible = "rockchip,rk1808-i2s-tdm"; 875 reg = <0x0 0xff7e0000 0x0 0x1000>; 876 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 878 clock-names = "mclk_tx", "mclk_rx", "hclk"; 879 dmas = <&dmac 16>, <&dmac 17>; 880 dma-names = "tx", "rx"; 881 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 882 reset-names = "tx-m", "rx-m"; 883 rockchip,cru = <&cru>; 884 pinctrl-names = "default"; 885 pinctrl-0 = <&i2s0_8ch_sclktx 886 &i2s0_8ch_sclkrx 887 &i2s0_8ch_lrcktx 888 &i2s0_8ch_lrckrx 889 &i2s0_8ch_sdi0 890 &i2s0_8ch_sdi1 891 &i2s0_8ch_sdi2 892 &i2s0_8ch_sdi3 893 &i2s0_8ch_sdo0 894 &i2s0_8ch_sdo1 895 &i2s0_8ch_sdo2 896 &i2s0_8ch_sdo3 897 &i2s0_8ch_mclk>; 898 status = "disabled"; 899 }; 900 901 i2s1: i2s@ff7f0000 { 902 compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s"; 903 reg = <0x0 0xff7f0000 0x0 0x1000>; 904 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 906 clock-names = "i2s_clk", "i2s_hclk"; 907 dmas = <&dmac 18>, <&dmac 19>; 908 dma-names = "tx", "rx"; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&i2s1_2ch_sclk 911 &i2s1_2ch_lrck 912 &i2s1_2ch_sdi 913 &i2s1_2ch_sdo>; 914 status = "disabled"; 915 }; 916 917 pdm: pdm@ff800000 { 918 compatible = "rockchip,rk1808-pdm", "rockchip,pdm"; 919 reg = <0x0 0xff800000 0x0 0x1000>; 920 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 921 clock-names = "pdm_clk", "pdm_hclk"; 922 dmas = <&dmac 24>; 923 dma-names = "rx"; 924 resets = <&cru SRST_PDM>; 925 reset-names = "pdm-m"; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&pdm_clk 928 &pdm_clk1 929 &pdm_sdi0 930 &pdm_sdi1 931 &pdm_sdi2 932 &pdm_sdi3>; 933 status = "disabled"; 934 }; 935 936 vad: vad@ff810000 { 937 compatible = "rockchip,rk1808-vad"; 938 reg = <0x0 0xff810000 0x0 0x10000>; 939 reg-names = "vad"; 940 clocks = <&cru HCLK_VAD>; 941 clock-names = "hclk"; 942 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 943 rockchip,audio-sram = <&vad_sram>; 944 rockchip,audio-src = <0>; 945 rockchip,det-channel = <0>; 946 rockchip,mode = <1>; 947 status = "disabled"; 948 }; 949 950 csi_tx: csi@ffb20000 { 951 compatible = "rockchip,rk1808-mipi-csi"; 952 reg = <0x0 0xffb20000 0x0 0x500>; 953 reg-names = "csi_regs"; 954 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&cru PCLK_CSI_TX>, <&mipi_dphy>; 956 clock-names = "pclk", "hs_clk"; 957 resets = <&cru SRST_CSITX_P>; 958 reset-names = "apb"; 959 phys = <&mipi_dphy>; 960 phy-names = "mipi_dphy"; 961 power-domains = <&power RK1808_PD_VIO>; 962 rockchip,grf = <&grf>; 963 status = "disabled"; 964 965 ports { 966 #address-cells = <1>; 967 #size-cells = <0>; 968 969 port { 970 csi_in_vop_raw: endpoint { 971 remote-endpoint = <&vop_raw_out_csi>; 972 }; 973 }; 974 }; 975 }; 976 977 dsi: dsi@ffb30000 { 978 compatible = "rockchip,rk1808-mipi-dsi"; 979 reg = <0x0 0xffb30000 0x0 0x500>; 980 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&cru PCLK_DSI_TX>, <&mipi_dphy>; 982 clock-names = "pclk", "hs_clk"; 983 resets = <&cru SRST_MIPIDSI_HOST_P>; 984 reset-names = "apb"; 985 phys = <&mipi_dphy>; 986 phy-names = "mipi_dphy"; 987 power-domains = <&power RK1808_PD_VIO>; 988 rockchip,grf = <&grf>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 status = "disabled"; 992 993 ports { 994 port { 995 dsi_in_vop_lite: endpoint { 996 remote-endpoint = <&vop_lite_out_dsi>; 997 }; 998 }; 999 }; 1000 }; 1001 1002 sfc: sfc@ffc50000 { 1003 compatible = "rockchip,rksfc"; 1004 reg = <0x0 0xffc50000 0x0 0x4000>; 1005 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1007 clock-names = "clk_sfc", "hclk_sfc"; 1008 status = "disabled"; 1009 }; 1010 1011 sdio: dwmmc@ffc60000 { 1012 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1013 reg = <0x0 0xffc60000 0x0 0x4000>; 1014 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1015 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1016 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1017 max-frequency = <150000000>; 1018 fifo-depth = <0x100>; 1019 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 1022 status = "disabled"; 1023 }; 1024 1025 npu: npu@ffbc0000 { 1026 compatible = "rockchip,npu"; 1027 reg = <0x0 0xffbc0000 0x0 0x1000>; 1028 clocks = <&cru SCLK_NPU>, <&cru HCLK_NPU>; 1029 clock-names = "sclk_npu", "hclk_npu"; 1030 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1031 status = "disabled"; 1032 }; 1033 1034 saradc: saradc@ff3c0000 { 1035 compatible = "rockchip,rk1808-saradc", "rockchip,rk3399-saradc"; 1036 reg = <0x0 0xff3c0000 0x0 0x100>; 1037 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1038 #io-channel-cells = <1>; 1039 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 1040 clock-names = "saradc", "apb_pclk"; 1041 resets = <&cru SRST_SARADC_P>; 1042 reset-names = "saradc-apb"; 1043 status = "disabled"; 1044 }; 1045 1046 sdmmc: dwmmc@ffcf0000 { 1047 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1048 reg = <0x0 0xffcf0000 0x0 0x4000>; 1049 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 1050 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1051 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1052 max-frequency = <150000000>; 1053 fifo-depth = <0x100>; 1054 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd>; 1057 status = "disabled"; 1058 }; 1059 1060 emmc: dwmmc@ffd00000 { 1061 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1062 reg = <0x0 0xffd00000 0x0 0x4000>; 1063 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1064 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1065 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1066 max-frequency = <150000000>; 1067 fifo-depth = <0x100>; 1068 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1069 status = "disabled"; 1070 }; 1071 1072 usb_host0_ehci: usb@ffd80000 { 1073 compatible = "generic-ehci"; 1074 reg = <0x0 0xffd80000 0x0 0x10000>; 1075 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1077 <&u2phy>; 1078 clock-names = "usbhost", "arbiter", "utmi"; 1079 phys = <&u2phy_host>; 1080 phy-names = "usb"; 1081 status = "disabled"; 1082 }; 1083 1084 usb_host0_ohci: usb@ffd90000 { 1085 compatible = "generic-ohci"; 1086 reg = <0x0 0xffd90000 0x0 0x10000>; 1087 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1089 <&u2phy>; 1090 clock-names = "usbhost", "arbiter", "utmi"; 1091 phys = <&u2phy_host>; 1092 phy-names = "usb"; 1093 status = "disabled"; 1094 }; 1095 1096 gmac: ethernet@ffdd0000 { 1097 compatible = "rockchip,rk1808-gmac"; 1098 reg = <0x0 0xffdd0000 0x0 0x10000>; 1099 rockchip,grf = <&grf>; 1100 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1101 interrupt-names = "macirq"; 1102 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 1103 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, 1104 <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, 1105 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; 1106 clock-names = "stmmaceth", "mac_clk_rx", 1107 "mac_clk_tx", "clk_mac_ref", 1108 "clk_mac_refout", "aclk_mac", 1109 "pclk_mac", "clk_mac_speed"; 1110 phy-mode = "rgmii"; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&rgmii_pins>; 1113 resets = <&cru SRST_GAMC_A>; 1114 reset-names = "stmmaceth"; 1115 /* power-domains = <&power RK1808_PD_GMAC>; */ 1116 status = "disabled"; 1117 }; 1118 1119 pinctrl: pinctrl { 1120 compatible = "rockchip,rk1808-pinctrl"; 1121 rockchip,grf = <&grf>; 1122 rockchip,pmu = <&pmugrf>; 1123 #address-cells = <2>; 1124 #size-cells = <2>; 1125 ranges; 1126 1127 gpio0: gpio0@ff4c0000 { 1128 compatible = "rockchip,gpio-bank"; 1129 reg = <0x0 0xff4c0000 0x0 0x100>; 1130 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; 1132 gpio-controller; 1133 #gpio-cells = <2>; 1134 1135 interrupt-controller; 1136 #interrupt-cells = <2>; 1137 }; 1138 1139 gpio1: gpio1@ff690000 { 1140 compatible = "rockchip,gpio-bank"; 1141 reg = <0x0 0xff690000 0x0 0x100>; 1142 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1144 gpio-controller; 1145 #gpio-cells = <2>; 1146 1147 interrupt-controller; 1148 #interrupt-cells = <2>; 1149 }; 1150 1151 gpio2: gpio2@ff6a0000 { 1152 compatible = "rockchip,gpio-bank"; 1153 reg = <0x0 0xff6a0000 0x0 0x100>; 1154 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1156 gpio-controller; 1157 #gpio-cells = <2>; 1158 1159 interrupt-controller; 1160 #interrupt-cells = <2>; 1161 }; 1162 1163 gpio3: gpio3@ff6b0000 { 1164 compatible = "rockchip,gpio-bank"; 1165 reg = <0x0 0xff6b0000 0x0 0x100>; 1166 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1168 gpio-controller; 1169 #gpio-cells = <2>; 1170 1171 interrupt-controller; 1172 #interrupt-cells = <2>; 1173 }; 1174 1175 gpio4: gpio4@ff6c0000 { 1176 compatible = "rockchip,gpio-bank"; 1177 reg = <0x0 0xff6c0000 0x0 0x100>; 1178 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1180 gpio-controller; 1181 #gpio-cells = <2>; 1182 1183 interrupt-controller; 1184 #interrupt-cells = <2>; 1185 }; 1186 1187 pcfg_pull_up: pcfg-pull-up { 1188 bias-pull-up; 1189 }; 1190 1191 pcfg_pull_down: pcfg-pull-down { 1192 bias-pull-down; 1193 }; 1194 1195 pcfg_pull_none: pcfg-pull-none { 1196 bias-disable; 1197 }; 1198 1199 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1200 bias-disable; 1201 drive-strength = <2>; 1202 }; 1203 1204 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1205 bias-pull-up; 1206 drive-strength = <2>; 1207 }; 1208 1209 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1210 bias-pull-up; 1211 drive-strength = <4>; 1212 }; 1213 1214 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1215 bias-disable; 1216 drive-strength = <4>; 1217 }; 1218 1219 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1220 bias-pull-down; 1221 drive-strength = <4>; 1222 }; 1223 1224 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1225 bias-disable; 1226 drive-strength = <8>; 1227 }; 1228 1229 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1230 bias-pull-up; 1231 drive-strength = <8>; 1232 }; 1233 1234 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1235 bias-disable; 1236 drive-strength = <12>; 1237 }; 1238 1239 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1240 bias-pull-up; 1241 drive-strength = <12>; 1242 }; 1243 1244 pcfg_pull_none_smt: pcfg-pull-none-smt { 1245 bias-disable; 1246 input-schmitt-enable; 1247 }; 1248 1249 pcfg_output_high: pcfg-output-high { 1250 output-high; 1251 }; 1252 1253 pcfg_output_low: pcfg-output-low { 1254 output-low; 1255 }; 1256 1257 pcfg_input_high: pcfg-input-high { 1258 bias-pull-up; 1259 input-enable; 1260 }; 1261 1262 pcfg_input: pcfg-input { 1263 input-enable; 1264 }; 1265 1266 emmc { 1267 emmc_clk: emmc-clk { 1268 rockchip,pins = 1269 /* emmc_clkout */ 1270 <1 RK_PB1 1 &pcfg_pull_none>; 1271 }; 1272 1273 emmc_rstnout: emmc-rstnout { 1274 rockchip,pins = 1275 /* emmc_rstn */ 1276 <1 RK_PB3 1 &pcfg_pull_none>; 1277 }; 1278 1279 emmc_bus8: emmc-bus8 { 1280 rockchip,pins = 1281 /* emmc_d0 */ 1282 <1 RK_PA0 1 &pcfg_pull_none>, 1283 /* emmc_d1 */ 1284 <1 RK_PA1 1 &pcfg_pull_none>, 1285 /* emmc_d2 */ 1286 <1 RK_PA2 1 &pcfg_pull_none>, 1287 /* emmc_d3 */ 1288 <1 RK_PA3 1 &pcfg_pull_none>, 1289 /* emmc_d4 */ 1290 <1 RK_PA4 1 &pcfg_pull_none>, 1291 /* emmc_d5 */ 1292 <1 RK_PA5 1 &pcfg_pull_none>, 1293 /* emmc_d6 */ 1294 <1 RK_PA6 1 &pcfg_pull_none>, 1295 /* emmc_d7 */ 1296 <1 RK_PA7 1 &pcfg_pull_none>; 1297 }; 1298 1299 emmc_pwren: emmc-pwren { 1300 rockchip,pins = 1301 <1 RK_PB0 1 &pcfg_pull_none>; 1302 }; 1303 1304 emmc_cmd: emmc-cmd { 1305 rockchip,pins = 1306 <1 RK_PB2 1 &pcfg_pull_none>; 1307 }; 1308 }; 1309 1310 gmac { 1311 rgmii_pins: rgmii-pins { 1312 rockchip,pins = 1313 /* rgmii_txen */ 1314 <2 RK_PA1 2 &pcfg_pull_none_4ma>, 1315 /* rgmii_txd1 */ 1316 <2 RK_PA2 2 &pcfg_pull_none_4ma>, 1317 /* rgmii_txd0 */ 1318 <2 RK_PA3 2 &pcfg_pull_none_4ma>, 1319 /* rgmii_rxd0 */ 1320 <2 RK_PA4 2 &pcfg_pull_none>, 1321 /* rgmii_rxd1 */ 1322 <2 RK_PA5 2 &pcfg_pull_none>, 1323 /* rgmii_rxdv */ 1324 <2 RK_PA7 2 &pcfg_pull_none>, 1325 /* rgmii_mdio */ 1326 <2 RK_PB0 2 &pcfg_pull_none_2ma>, 1327 /* rgmii_mdc */ 1328 <2 RK_PB2 2 &pcfg_pull_none_2ma>, 1329 /* rgmii_txd3 */ 1330 <2 RK_PB3 2 &pcfg_pull_none_4ma>, 1331 /* rgmii_txd2 */ 1332 <2 RK_PB4 2 &pcfg_pull_none_4ma>, 1333 /* rgmii_rxd2 */ 1334 <2 RK_PB5 2 &pcfg_pull_none>, 1335 /* rgmii_rxd3 */ 1336 <2 RK_PB6 2 &pcfg_pull_none>, 1337 /* rgmii_clk */ 1338 <2 RK_PB7 2 &pcfg_pull_none>, 1339 /* rgmii_txclk */ 1340 <2 RK_PC1 2 &pcfg_pull_none_4ma>, 1341 /* rgmii_rxclk */ 1342 <2 RK_PC2 2 &pcfg_pull_none>; 1343 }; 1344 1345 rmii_pins: rmii-pins { 1346 rockchip,pins = 1347 /* rmii_txen */ 1348 <2 RK_PA1 2 &pcfg_pull_none_4ma>, 1349 /* rmii_txd1 */ 1350 <2 RK_PA2 2 &pcfg_pull_none_4ma>, 1351 /* rmii_txd0 */ 1352 <2 RK_PA3 2 &pcfg_pull_none_4ma>, 1353 /* rmii_rxd0 */ 1354 <2 RK_PA4 2 &pcfg_pull_none>, 1355 /* rmii_rxd1 */ 1356 <2 RK_PA5 2 &pcfg_pull_none>, 1357 /* rmii_rxer */ 1358 <2 RK_PA6 2 &pcfg_pull_none>, 1359 /* rmii_rxdv */ 1360 <2 RK_PA7 2 &pcfg_pull_none>, 1361 /* rmii_mdio */ 1362 <2 RK_PB0 2 &pcfg_pull_none_2ma>, 1363 /* rmii_mdc */ 1364 <2 RK_PB2 2 &pcfg_pull_none_2ma>, 1365 /* rmii_clk */ 1366 <2 RK_PB7 2 &pcfg_pull_none>; 1367 }; 1368 }; 1369 1370 i2c0 { 1371 i2c0_xfer: i2c0-xfer { 1372 rockchip,pins = 1373 /* i2c0_sda */ 1374 <0 RK_PB1 1 &pcfg_pull_none_smt>, 1375 /* i2c0_scl */ 1376 <0 RK_PB0 1 &pcfg_pull_none_smt>; 1377 }; 1378 }; 1379 1380 i2c1 { 1381 i2c1_xfer: i2c1-xfer { 1382 rockchip,pins = 1383 /* i2c1_sda */ 1384 <0 RK_PC1 1 &pcfg_pull_none_smt>, 1385 /* i2c1_scl */ 1386 <0 RK_PC0 1 &pcfg_pull_none_smt>; 1387 }; 1388 }; 1389 1390 i2c2m0 { 1391 i2c2m0_xfer: i2c2m0-xfer { 1392 rockchip,pins = 1393 /* i2c2m0_sda */ 1394 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1395 /* i2c2m0_scl */ 1396 <3 RK_PB3 2 &pcfg_pull_none_smt>; 1397 }; 1398 }; 1399 1400 i2c3 { 1401 i2c3_xfer: i2c3-xfer { 1402 rockchip,pins = 1403 /* i2c3_sda */ 1404 <2 RK_PD1 1 &pcfg_pull_none_smt>, 1405 /* i2c3_scl */ 1406 <2 RK_PD0 1 &pcfg_pull_none_smt>; 1407 }; 1408 }; 1409 1410 i2c4 { 1411 i2c4_xfer: i2c4-xfer { 1412 rockchip,pins = 1413 /* i2c4_sda */ 1414 <3 RK_PC3 3 &pcfg_pull_none_smt>, 1415 /* i2c4_scl */ 1416 <3 RK_PC2 3 &pcfg_pull_none_smt>; 1417 }; 1418 }; 1419 1420 i2c5 { 1421 i2c5_xfer: i2c5-xfer { 1422 rockchip,pins = 1423 /* i2c5_sda */ 1424 <4 RK_PC2 1 &pcfg_pull_none_smt>, 1425 /* i2c5_scl */ 1426 <4 RK_PC1 1 &pcfg_pull_none_smt>; 1427 }; 1428 }; 1429 1430 i2s1 { 1431 i2s1_2ch_lrck: i2s1-2ch-lrck { 1432 rockchip,pins = 1433 <3 RK_PA0 1 &pcfg_pull_none>; 1434 }; 1435 i2s1_2ch_sclk: i2s1-2ch-sclk { 1436 rockchip,pins = 1437 <3 RK_PA1 1 &pcfg_pull_none>; 1438 }; 1439 i2s1_2ch_mclk: i2s1-2ch-mclk { 1440 rockchip,pins = 1441 <3 RK_PA2 1 &pcfg_pull_none>; 1442 }; 1443 i2s1_2ch_sdo: i2s1-2ch-sdo { 1444 rockchip,pins = 1445 <3 RK_PA3 1 &pcfg_pull_none>; 1446 }; 1447 i2s1_2ch_sdi: i2s1-2ch-sdi { 1448 rockchip,pins = 1449 <3 RK_PA4 1 &pcfg_pull_none>; 1450 }; 1451 }; 1452 1453 i2s0 { 1454 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1455 rockchip,pins = 1456 <3 RK_PA5 1 &pcfg_pull_none>; 1457 }; 1458 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1459 rockchip,pins = 1460 <3 RK_PA6 1 &pcfg_pull_none>; 1461 }; 1462 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1463 rockchip,pins = 1464 <3 RK_PA7 1 &pcfg_pull_none>; 1465 }; 1466 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1467 rockchip,pins = 1468 <3 RK_PB0 1 &pcfg_pull_none>; 1469 }; 1470 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1471 rockchip,pins = 1472 <3 RK_PB1 1 &pcfg_pull_none>; 1473 }; 1474 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1475 rockchip,pins = 1476 <3 RK_PB2 1 &pcfg_pull_none>; 1477 }; 1478 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1479 rockchip,pins = 1480 <3 RK_PB3 1 &pcfg_pull_none>; 1481 }; 1482 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1483 rockchip,pins = 1484 <3 RK_PB4 1 &pcfg_pull_none>; 1485 }; 1486 i2s0_8ch_mclk: i2s0-8ch-mclk { 1487 rockchip,pins = 1488 <3 RK_PB5 1 &pcfg_pull_none>; 1489 }; 1490 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1491 rockchip,pins = 1492 <3 RK_PB6 1 &pcfg_pull_none>; 1493 }; 1494 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1495 rockchip,pins = 1496 <3 RK_PB7 1 &pcfg_pull_none>; 1497 }; 1498 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1499 rockchip,pins = 1500 <3 RK_PC0 1 &pcfg_pull_none>; 1501 }; 1502 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1503 rockchip,pins = 1504 <3 RK_PC1 1 &pcfg_pull_none>; 1505 }; 1506 }; 1507 1508 lcdc { 1509 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1510 rockchip,pins = 1511 /* lcdc_clkm0 */ 1512 <2 RK_PC6 3 &pcfg_pull_none>; 1513 }; 1514 1515 lcdc_rgb_den_pin: lcdc-rgb-den-pin { 1516 rockchip,pins = 1517 /* lcdc_denm0 */ 1518 <2 RK_PC7 3 &pcfg_pull_none>; 1519 }; 1520 1521 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1522 rockchip,pins = 1523 /* lcdc_hsyncm0 */ 1524 <2 RK_PB2 3 &pcfg_pull_none>; 1525 }; 1526 1527 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1528 rockchip,pins = 1529 /* lcdc_vsyncm0 */ 1530 <2 RK_PB3 3 &pcfg_pull_none>; 1531 }; 1532 1533 lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin { 1534 rockchip,pins = 1535 /* lcdc_hsyncm1 */ 1536 <3 RK_PB2 3 &pcfg_pull_none>; 1537 }; 1538 1539 lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin { 1540 rockchip,pins = 1541 /* lcdc_vsyncm1 */ 1542 <3 RK_PB3 3 &pcfg_pull_none>; 1543 }; 1544 1545 lcdc_rgb666_data_pins: lcdc-rgb666-data-pins { 1546 rockchip,pins = 1547 /* lcdc_d0m0 */ 1548 <2 RK_PA2 3 &pcfg_pull_none>, 1549 /* lcdc_d1m0 */ 1550 <2 RK_PA3 3 &pcfg_pull_none>, 1551 /* lcdc_d2m0 */ 1552 <2 RK_PC2 3 &pcfg_pull_none>, 1553 /* lcdc_d3m0 */ 1554 <2 RK_PC3 3 &pcfg_pull_none>, 1555 /* lcdc_d4m0 */ 1556 <2 RK_PC4 3 &pcfg_pull_none>, 1557 /* lcdc_d5m0 */ 1558 <2 RK_PC5 3 &pcfg_pull_none>, 1559 /* lcdc_d6m0 */ 1560 <2 RK_PA0 3 &pcfg_pull_none>, 1561 /* lcdc_d7m0 */ 1562 <2 RK_PA1 3 &pcfg_pull_none>, 1563 /* lcdc_d8 */ 1564 <3 RK_PC2 1 &pcfg_pull_none>, 1565 /* lcdc_d9 */ 1566 <3 RK_PC3 1 &pcfg_pull_none>, 1567 /* lcdc_d10 */ 1568 <3 RK_PC4 1 &pcfg_pull_none>, 1569 /* lcdc_d11 */ 1570 <3 RK_PC5 1 &pcfg_pull_none>, 1571 /* lcdc_d12 */ 1572 <3 RK_PC6 1 &pcfg_pull_none>, 1573 /* lcdc_d13 */ 1574 <3 RK_PC7 1 &pcfg_pull_none>, 1575 /* lcdc_d14 */ 1576 <3 RK_PD0 1 &pcfg_pull_none>, 1577 /* lcdc_d15 */ 1578 <3 RK_PD1 1 &pcfg_pull_none>, 1579 /* lcdc_d16 */ 1580 <3 RK_PD2 1 &pcfg_pull_none>, 1581 /* lcdc_d17 */ 1582 <3 RK_PD3 1 &pcfg_pull_none>; 1583 }; 1584 1585 lcdc_rgb565_data_pins: lcdc-rgb565-data-pins { 1586 rockchip,pins = 1587 /* lcdc_d0m0 */ 1588 <2 RK_PA2 3 &pcfg_pull_none>, 1589 /* lcdc_d1m0 */ 1590 <2 RK_PA3 3 &pcfg_pull_none>, 1591 /* lcdc_d2m0 */ 1592 <2 RK_PC2 3 &pcfg_pull_none>, 1593 /* lcdc_d3m0 */ 1594 <2 RK_PC3 3 &pcfg_pull_none>, 1595 /* lcdc_d4m0 */ 1596 <2 RK_PC4 3 &pcfg_pull_none>, 1597 /* lcdc_d5m0 */ 1598 <2 RK_PC5 3 &pcfg_pull_none>, 1599 /* lcdc_d6m0 */ 1600 <2 RK_PA0 3 &pcfg_pull_none>, 1601 /* lcdc_d7m0 */ 1602 <2 RK_PA1 3 &pcfg_pull_none>, 1603 /* lcdc_d8 */ 1604 <3 RK_PC2 1 &pcfg_pull_none>, 1605 /* lcdc_d9 */ 1606 <3 RK_PC3 1 &pcfg_pull_none>, 1607 /* lcdc_d10 */ 1608 <3 RK_PC4 1 &pcfg_pull_none>, 1609 /* lcdc_d11 */ 1610 <3 RK_PC5 1 &pcfg_pull_none>, 1611 /* lcdc_d12 */ 1612 <3 RK_PC6 1 &pcfg_pull_none>, 1613 /* lcdc_d13 */ 1614 <3 RK_PC7 1 &pcfg_pull_none>, 1615 /* lcdc_d14 */ 1616 <3 RK_PD0 1 &pcfg_pull_none>, 1617 /* lcdc_d15 */ 1618 <3 RK_PD1 1 &pcfg_pull_none>; 1619 }; 1620 }; 1621 1622 pciusb { 1623 pciusb_pins: pciusb-pins { 1624 rockchip,pins = 1625 /* pciusb_debug0 */ 1626 <4 RK_PB4 3 &pcfg_pull_none>, 1627 /* pciusb_debug1 */ 1628 <4 RK_PB5 3 &pcfg_pull_none>, 1629 /* pciusb_debug2 */ 1630 <4 RK_PB6 3 &pcfg_pull_none>, 1631 /* pciusb_debug3 */ 1632 <4 RK_PB7 3 &pcfg_pull_none>, 1633 /* pciusb_debug4 */ 1634 <4 RK_PC0 3 &pcfg_pull_none>, 1635 /* pciusb_debug5 */ 1636 <4 RK_PC1 3 &pcfg_pull_none>, 1637 /* pciusb_debug6 */ 1638 <4 RK_PC2 3 &pcfg_pull_none>, 1639 /* pciusb_debug7 */ 1640 <4 RK_PC3 3 &pcfg_pull_none>; 1641 }; 1642 }; 1643 1644 pdm { 1645 pdm_clk: pdm-clk { 1646 rockchip,pins = 1647 /* pdm_clk0 */ 1648 <3 RK_PB0 2 &pcfg_pull_none>; 1649 }; 1650 1651 pdm_sdi3: pdm-sdi3 { 1652 rockchip,pins = 1653 <3 RK_PA5 2 &pcfg_pull_none>; 1654 }; 1655 1656 pdm_sdi2: pdm-sdi2 { 1657 rockchip,pins = 1658 <3 RK_PA6 2 &pcfg_pull_none>; 1659 }; 1660 1661 pdm_sdi1: pdm-sdi1 { 1662 rockchip,pins = 1663 <3 RK_PA7 2 &pcfg_pull_none>; 1664 }; 1665 1666 pdm_clk1: pdm-clk1 { 1667 rockchip,pins = 1668 <3 RK_PB1 2 &pcfg_pull_none>; 1669 }; 1670 1671 pdm_sdi0: pdm-sdi0 { 1672 rockchip,pins = 1673 <3 RK_PC1 2 &pcfg_pull_none>; 1674 }; 1675 }; 1676 1677 pwm0 { 1678 pwm0_pin: pwm0-pin { 1679 rockchip,pins = 1680 <0 RK_PB7 1 &pcfg_pull_none>; 1681 }; 1682 }; 1683 1684 pwm1 { 1685 pwm1_pin: pwm1-pin { 1686 rockchip,pins = 1687 <0 RK_PC3 1 &pcfg_pull_none>; 1688 }; 1689 }; 1690 1691 pwm2 { 1692 pwm2_pin: pwm2-pin { 1693 rockchip,pins = 1694 <0 RK_PC5 1 &pcfg_pull_none>; 1695 }; 1696 }; 1697 1698 pwm3 { 1699 pwm3_pin: pwm3-pin { 1700 rockchip,pins = 1701 <0 RK_PC4 1 &pcfg_pull_none>; 1702 }; 1703 }; 1704 1705 pwm4 { 1706 pwm4_pin: pwm4-pin { 1707 rockchip,pins = 1708 <1 RK_PB6 2 &pcfg_pull_none>; 1709 }; 1710 }; 1711 1712 pwm5 { 1713 pwm5_pin: pwm5-pin { 1714 rockchip,pins = 1715 <1 RK_PB7 2 &pcfg_pull_none>; 1716 }; 1717 }; 1718 pwm6 { 1719 pwm6_pin: pwm6-pin { 1720 rockchip,pins = 1721 <3 RK_PA1 2 &pcfg_pull_none>; 1722 }; 1723 }; 1724 1725 pwm7 { 1726 pwm7_pin: pwm7-pin { 1727 rockchip,pins = 1728 <3 RK_PA2 2 &pcfg_pull_none>; 1729 }; 1730 }; 1731 1732 pwm8 { 1733 pwm8_pin: pwm8-pin { 1734 rockchip,pins = 1735 <3 RK_PD0 2 &pcfg_pull_none>; 1736 }; 1737 }; 1738 1739 pwm9 { 1740 pwm9_pin: pwm9-pin { 1741 rockchip,pins = 1742 <3 RK_PD1 2 &pcfg_pull_none>; 1743 }; 1744 }; 1745 1746 pwm10 { 1747 pwm10_pin: pwm10-pin { 1748 rockchip,pins = 1749 <3 RK_PD2 2 &pcfg_pull_none>; 1750 }; 1751 }; 1752 1753 pwm11 { 1754 pwm11_pin: pwm11-pin { 1755 rockchip,pins = 1756 <3 RK_PD3 2 &pcfg_pull_none>; 1757 }; 1758 }; 1759 1760 sdmmc0 { 1761 sdmmc0_bus4: sdmmc0-bus4 { 1762 rockchip,pins = 1763 /* sdmmc0_d0 */ 1764 <4 RK_PA2 1 &pcfg_pull_none>, 1765 /* sdmmc0_d1 */ 1766 <4 RK_PA3 1 &pcfg_pull_none>, 1767 /* sdmmc0_d2 */ 1768 <4 RK_PA4 1 &pcfg_pull_none>, 1769 /* sdmmc0_d3 */ 1770 <4 RK_PA5 1 &pcfg_pull_none>; 1771 }; 1772 sdmmc0_cmd: sdmmc0-cmd { 1773 rockchip,pins = 1774 <4 RK_PA0 1 &pcfg_pull_none>; 1775 }; 1776 sdmmc0_clk: sdmmc0-clk { 1777 rockchip,pins = 1778 <4 RK_PA1 1 &pcfg_pull_none>; 1779 }; 1780 }; 1781 1782 sdmmc1 { 1783 sdmmc1_bus4: sdmmc1-bus4 { 1784 rockchip,pins = 1785 /* sdmmc1_d0 */ 1786 <4 RK_PB0 1 &pcfg_pull_none>, 1787 /* sdmmc1_d1 */ 1788 <4 RK_PB1 1 &pcfg_pull_none>, 1789 /* sdmmc1_d2 */ 1790 <4 RK_PB2 1 &pcfg_pull_none>, 1791 /* sdmmc1_d3 */ 1792 <4 RK_PB3 1 &pcfg_pull_none>; 1793 }; 1794 1795 sdmmc1_cmd: sdmmc1-cmd { 1796 rockchip,pins = 1797 <4 RK_PA6 1 &pcfg_pull_none>; 1798 }; 1799 1800 sdmmc1_clk: sdmmc1-clk { 1801 rockchip,pins = 1802 <4 RK_PA7 1 &pcfg_pull_none>; 1803 }; 1804 }; 1805 1806 spi0 { 1807 spi0_mosi: spi0-mosi { 1808 rockchip,pins = 1809 <1 RK_PB4 1 &pcfg_pull_up_4ma>; 1810 }; 1811 1812 spi0_miso: spi0-miso { 1813 rockchip,pins = 1814 <1 RK_PB5 1 &pcfg_pull_up_4ma>; 1815 }; 1816 1817 spi0_csn: spi0-csn { 1818 rockchip,pins = 1819 <1 RK_PB6 1 &pcfg_pull_up_4ma>; 1820 }; 1821 1822 spi0_clk: spi0-clk { 1823 rockchip,pins = 1824 <1 RK_PB7 1 &pcfg_pull_up_4ma>; 1825 }; 1826 1827 spi0_mosi_hs: spi0-mosi-hs { 1828 rockchip,pins = 1829 <1 RK_PB4 1 &pcfg_pull_up_8ma>; 1830 }; 1831 1832 spi0_miso_hs: spi0-miso-hs { 1833 rockchip,pins = 1834 <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1835 }; 1836 1837 spi0_csn_hs: spi0-csn-hs { 1838 rockchip,pins = 1839 <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1840 }; 1841 1842 spi0_clk_hs: spi0-clk-hs { 1843 rockchip,pins = 1844 <1 RK_PB7 1 &pcfg_pull_up_8ma>; 1845 }; 1846 }; 1847 1848 spi1 { 1849 spi1_clk: spi1-clk { 1850 rockchip,pins = 1851 <4 RK_PB4 2 &pcfg_pull_up_4ma>; 1852 }; 1853 1854 spi1_mosi: spi1-mosi { 1855 rockchip,pins = 1856 <4 RK_PB5 2 &pcfg_pull_up_4ma>; 1857 }; 1858 1859 spi1_csn0: spi1-csn0 { 1860 rockchip,pins = 1861 <4 RK_PB6 2 &pcfg_pull_up_4ma>; 1862 }; 1863 1864 spi1_miso: spi1-miso { 1865 rockchip,pins = 1866 <4 RK_PB7 2 &pcfg_pull_up_4ma>; 1867 }; 1868 1869 spi1_csn1: spi1-csn1 { 1870 rockchip,pins = 1871 <4 RK_PC0 2 &pcfg_pull_up_4ma>; 1872 }; 1873 1874 spi1_clk_hs: spi1-clk-hs { 1875 rockchip,pins = 1876 <4 RK_PB4 2 &pcfg_pull_up_8ma>; 1877 }; 1878 1879 spi1_mosi_hs: spi1-mosi-hs { 1880 rockchip,pins = 1881 <4 RK_PB5 2 &pcfg_pull_up_8ma>; 1882 }; 1883 1884 spi1_csn0_hs: spi1-csn0-hs { 1885 rockchip,pins = 1886 <4 RK_PB6 2 &pcfg_pull_up_8ma>; 1887 }; 1888 1889 spi1_miso_hs: spi1-miso-hs { 1890 rockchip,pins = 1891 <4 RK_PB7 2 &pcfg_pull_up_8ma>; 1892 }; 1893 1894 spi1_csn1_hs: spi1-csn1-hs { 1895 rockchip,pins = 1896 <4 RK_PC0 2 &pcfg_pull_up_8ma>; 1897 }; 1898 }; 1899 1900 spi1m1 { 1901 spi1m1_clk: spi1m1-clk { 1902 rockchip,pins = 1903 <3 RK_PC7 3 &pcfg_pull_up_4ma>; 1904 }; 1905 1906 spi1m1_mosi: spi1m1-mosi { 1907 rockchip,pins = 1908 <3 RK_PD0 3 &pcfg_pull_up_4ma>; 1909 }; 1910 1911 spi1m1_csn0: spi1m1-csn0 { 1912 rockchip,pins = 1913 <3 RK_PD1 3 &pcfg_pull_up_4ma>; 1914 }; 1915 1916 spi1m1_miso: spi1m1-miso { 1917 rockchip,pins = 1918 <3 RK_PD2 3 &pcfg_pull_up_4ma>; 1919 }; 1920 1921 spi1m1_csn1: spi1m1-csn1 { 1922 rockchip,pins = 1923 <3 RK_PD3 3 &pcfg_pull_up_4ma>; 1924 }; 1925 1926 spi1m1_clk_hs: spi1m1-clk-hs { 1927 rockchip,pins = 1928 <3 RK_PC7 3 &pcfg_pull_up_8ma>; 1929 }; 1930 1931 spi1m1_mosi_hs: spi1m1-mosi-hs { 1932 rockchip,pins = 1933 <3 RK_PD0 3 &pcfg_pull_up_8ma>; 1934 }; 1935 1936 spi1m1_csn0_hs: spi1m1-csn0-hs { 1937 rockchip,pins = 1938 <3 RK_PD1 3 &pcfg_pull_up_8ma>; 1939 }; 1940 1941 spi1m1_miso_hs: spi1m1-miso-hs { 1942 rockchip,pins = 1943 <3 RK_PD2 3 &pcfg_pull_up_8ma>; 1944 }; 1945 1946 spi1m1_csn1_hs: spi1m1-csn1-hs { 1947 rockchip,pins = 1948 <3 RK_PD3 3 &pcfg_pull_up_8ma>; 1949 }; 1950 }; 1951 1952 spi2m0 { 1953 spi2m0_miso: spi2m0-miso { 1954 rockchip,pins = 1955 <1 RK_PA6 2 &pcfg_pull_up_4ma>; 1956 }; 1957 1958 spi2m0_clk: spi2m0-clk { 1959 rockchip,pins = 1960 <1 RK_PA7 2 &pcfg_pull_up_4ma>; 1961 }; 1962 1963 spi2m0_mosi: spi2m0-mosi { 1964 rockchip,pins = 1965 <1 RK_PB0 2 &pcfg_pull_up_4ma>; 1966 }; 1967 1968 spi2m0_csn: spi2m0-csn { 1969 rockchip,pins = 1970 <1 RK_PB1 2 &pcfg_pull_up_4ma>; 1971 }; 1972 1973 spi2m0_miso_hs: spi2m0-miso-hs { 1974 rockchip,pins = 1975 <1 RK_PA6 2 &pcfg_pull_none>; 1976 }; 1977 1978 spi2m0_clk_hs: spi2m0-clk-hs { 1979 rockchip,pins = 1980 <1 RK_PA7 2 &pcfg_pull_none>; 1981 }; 1982 1983 spi2m0_mosi_hs: spi2m0-mosi-hs { 1984 rockchip,pins = 1985 <1 RK_PB0 2 &pcfg_pull_none>; 1986 }; 1987 1988 spi2m0_csn_hs: spi2m0-csn-hs { 1989 rockchip,pins = 1990 <1 RK_PB1 2 &pcfg_pull_none>; 1991 }; 1992 }; 1993 1994 spi2m1 { 1995 spi2m1_miso: spi2m1-miso { 1996 rockchip,pins = 1997 <2 RK_PA4 3 &pcfg_pull_up_4ma>; 1998 }; 1999 2000 spi2m1_clk: spi2m1-clk { 2001 rockchip,pins = 2002 <2 RK_PA5 3 &pcfg_pull_up_4ma>; 2003 }; 2004 2005 spi2m1_mosi: spi2m1-mosi { 2006 rockchip,pins = 2007 <2 RK_PA6 3 &pcfg_pull_up_4ma>; 2008 }; 2009 2010 spi2m1_csn: spi2m1-csn { 2011 rockchip,pins = 2012 <2 RK_PA7 3 &pcfg_pull_up_4ma>; 2013 }; 2014 2015 spi2m1_miso_hs: spi2m1-miso-hs { 2016 rockchip,pins = 2017 <2 RK_PA4 3 &pcfg_pull_up_8ma>; 2018 }; 2019 2020 spi2m1_clk_hs: spi2m1-clk-hs { 2021 rockchip,pins = 2022 <2 RK_PA5 3 &pcfg_pull_up_8ma>; 2023 }; 2024 2025 spi2m1_mosi_hs: spi2m1-mosi-hs { 2026 rockchip,pins = 2027 <2 RK_PA6 3 &pcfg_pull_up_8ma>; 2028 }; 2029 2030 spi2m1_csn_hs: spi2m1-csn-hs { 2031 rockchip,pins = 2032 <2 RK_PA7 3 &pcfg_pull_up_8ma>; 2033 }; 2034 }; 2035 2036 uart0 { 2037 uart0_xfer: uart0-xfer { 2038 rockchip,pins = 2039 /* uart0_rx */ 2040 <0 RK_PB3 1 &pcfg_pull_none>, 2041 /* uart0_tx */ 2042 <0 RK_PB2 1 &pcfg_pull_none>; 2043 }; 2044 2045 uart0_cts: uart0-cts { 2046 rockchip,pins = 2047 <0 RK_PB4 1 &pcfg_pull_none>; 2048 }; 2049 2050 uart0_rts: uart0-rts { 2051 rockchip,pins = 2052 <0 RK_PB5 1 &pcfg_pull_none>; 2053 }; 2054 }; 2055 2056 uart1 { 2057 uart1m0_xfer: uart1m0-xfer { 2058 rockchip,pins = 2059 /* uart1_rxm0 */ 2060 <4 RK_PB0 2 &pcfg_pull_none>, 2061 /* uart1_txm0 */ 2062 <4 RK_PB1 2 &pcfg_pull_none>; 2063 }; 2064 2065 uart1m1_xfer: uart1m1-xfer { 2066 rockchip,pins = 2067 /* uart1_rxm1 */ 2068 <1 RK_PB4 3 &pcfg_pull_none>, 2069 /* uart1_txm1 */ 2070 <1 RK_PB5 3 &pcfg_pull_none>; 2071 }; 2072 2073 uart1_cts: uart1-cts { 2074 rockchip,pins = 2075 <4 RK_PB2 2 &pcfg_pull_none>; 2076 }; 2077 2078 uart1_rts: uart1-rts { 2079 rockchip,pins = 2080 <4 RK_PB3 2 &pcfg_pull_none>; 2081 }; 2082 }; 2083 2084 uart2 { 2085 uart2m0_xfer: uart2m0-xfer { 2086 rockchip,pins = 2087 /* uart2_rxm0 */ 2088 <4 RK_PA3 2 &pcfg_pull_none>, 2089 /* uart2_txm0 */ 2090 <4 RK_PA2 2 &pcfg_pull_none>; 2091 }; 2092 2093 uart2m1_xfer: uart2m1-xfer { 2094 rockchip,pins = 2095 /* uart2_rxm1 */ 2096 <2 RK_PD1 2 &pcfg_pull_none>, 2097 /* uart2_txm1 */ 2098 <2 RK_PD0 2 &pcfg_pull_none>; 2099 }; 2100 2101 uart2m2_xfer: uart2m2-xfer { 2102 rockchip,pins = 2103 /* uart2_rxm2 */ 2104 <3 RK_PA4 2 &pcfg_pull_none>, 2105 /* uart2_txm2 */ 2106 <3 RK_PA3 2 &pcfg_pull_none>; 2107 }; 2108 }; 2109 2110 uart3 { 2111 uart3m0_xfer: uart3m0-xfer { 2112 rockchip,pins = 2113 /* uart3_rxm0 */ 2114 <0 RK_PC5 2 &pcfg_pull_none>, 2115 /* uart3_txm0 */ 2116 <0 RK_PC4 2 &pcfg_pull_none>; 2117 }; 2118 2119 uart3_ctsm0: uart3-ctsm0 { 2120 rockchip,pins = 2121 <0 RK_PC7 2 &pcfg_pull_none>; 2122 }; 2123 2124 uart3_rtsm0: uart3-rtsm0 { 2125 rockchip,pins = 2126 <0 RK_PD0 2 &pcfg_pull_none>; 2127 }; 2128 }; 2129 2130 uart4 { 2131 uart4_xfer: uart4-xfer { 2132 rockchip,pins = 2133 /* uart4_rx */ 2134 <4 RK_PB4 1 &pcfg_pull_none>, 2135 /* uart4_tx */ 2136 <4 RK_PB5 1 &pcfg_pull_none>; 2137 }; 2138 2139 uart4_cts: uart4-cts { 2140 rockchip,pins = 2141 <4 RK_PB6 1 &pcfg_pull_none>; 2142 }; 2143 2144 uart4_rts: uart4-rts { 2145 rockchip,pins = 2146 <4 RK_PB7 1 &pcfg_pull_none>; 2147 }; 2148 }; 2149 2150 uart5 { 2151 uart5_xfer: uart5-xfer { 2152 rockchip,pins = 2153 /* uart5_rx */ 2154 <3 RK_PC3 1 &pcfg_pull_none>, 2155 /* uart5_tx */ 2156 <3 RK_PC2 1 &pcfg_pull_none>; 2157 }; 2158 }; 2159 2160 uart6 { 2161 uart6_xfer: uart6-xfer { 2162 rockchip,pins = 2163 /* uart6_rx */ 2164 <3 RK_PC5 1 &pcfg_pull_none>, 2165 /* uart6_tx */ 2166 <3 RK_PC4 1 &pcfg_pull_none>; 2167 }; 2168 }; 2169 2170 uart7 { 2171 uart7_xfer: uart7-xfer { 2172 rockchip,pins = 2173 /* uart7_rx */ 2174 <3 RK_PC7 1 &pcfg_pull_none>, 2175 /* uart7_tx */ 2176 <3 RK_PC6 1 &pcfg_pull_none>; 2177 }; 2178 }; 2179 2180 tsadc { 2181 tsadc_otp_gpio: tsadc-otp-gpio { 2182 rockchip,pins = 2183 <0 RK_PA6 0 &pcfg_pull_none>; 2184 }; 2185 2186 tsadc_otp_out: tsadc-otp-out { 2187 rockchip,pins = 2188 <0 RK_PA6 2 &pcfg_pull_none>; 2189 }; 2190 }; 2191 }; 2192}; 2193