1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 3 4#include <dt-bindings/clock/rk1808-cru.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8 9/ { 10 compatible = "rockchip,rk1808"; 11 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 i2c0 = &i2c0; 18 i2c1 = &i2c1; 19 i2c2 = &i2c2; 20 i2c3 = &i2c3; 21 i2c4 = &i2c4; 22 i2c5 = &i2c5; 23 serial2 = &uart2; 24 spi0 = &spi0; 25 spi1 = &spi1; 26 spi2 = &spi2; 27 }; 28 29 cpus { 30 #address-cells = <2>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a35", "arm,armv8"; 36 reg = <0x0 0x0>; 37 clocks = <&cru ARMCLK>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35", "arm,armv8"; 43 reg = <0x0 0x1>; 44 clocks = <&cru ARMCLK>; 45 }; 46 }; 47 48 arm-pmu { 49 compatible = "arm,cortex-a53-pmu"; 50 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 52 interrupt-affinity = <&cpu0>, <&cpu1>; 53 }; 54 55 gmac_clkin: external-gmac-clock { 56 compatible = "fixed-clock"; 57 clock-frequency = <125000000>; 58 clock-output-names = "gmac_clkin"; 59 #clock-cells = <0>; 60 }; 61 62 timer { 63 compatible = "arm,armv8-timer"; 64 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 65 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 66 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 67 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 68 arm,no-tick-in-suspend; 69 }; 70 71 xin24m: xin24m { 72 compatible = "fixed-clock"; 73 clock-frequency = <24000000>; 74 clock-output-names = "xin24m"; 75 #clock-cells = <0>; 76 }; 77 78 xin32k: xin32k { 79 compatible = "fixed-clock"; 80 clock-frequency = <32768>; 81 clock-output-names = "xin32k"; 82 #clock-cells = <0>; 83 }; 84 85 grf: syscon@fe000000 { 86 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; 87 reg = <0x0 0xfe000000 0x0 0x1000>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 }; 91 92 pmugrf: syscon@fe410000 { 93 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; 94 reg = <0x0 0xfe410000 0x0 0x1000>; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 }; 98 99 gic: interrupt-controller@ff100000 { 100 compatible = "arm,gic-v3"; 101 #interrupt-cells = <3>; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges; 105 interrupt-controller; 106 107 reg = <0x0 0xff100000 0 0x10000>, /* GICD */ 108 <0x0 0xff140000 0 0xc0000>, /* GICR */ 109 <0x0 0xff300000 0 0x10000>, /* GICC */ 110 <0x0 0xff310000 0 0x10000>, /* GICH */ 111 <0x0 0xff320000 0 0x10000>; /* GICV */ 112 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 113 its: interrupt-controller@ff120000 { 114 compatible = "arm,gic-v3-its"; 115 msi-controller; 116 reg = <0x0 0xff120000 0x0 0x20000>; 117 }; 118 }; 119 120 dmc: dmc { 121 compatible = "rockchip,rk1808-dmc"; 122 }; 123 124 cru: clock-controller@ff350000 { 125 compatible = "rockchip,rk1808-cru"; 126 reg = <0x0 0xff350000 0x0 0x5000>; 127 rockchip,grf = <&grf>; 128 #clock-cells = <1>; 129 #reset-cells = <1>; 130 131 assigned-clocks = 132 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 133 <&cru PLL_PPLL>, <&cru ARMCLK>, 134 <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 135 <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 136 <&cru LSCLK_BUS_PRE>; 137 assigned-clock-rates = 138 <1200000000>, <1000000000>, 139 <416000000>, <816000000>, 140 <200000000>, <100000000>, 141 <300000000>, <200000000>, 142 <100000000>; 143 }; 144 145 tsadc: tsadc@ff3a0000 { 146 compatible = "rockchip,rk1808-tsadc"; 147 reg = <0x0 0xff3a0000 0x0 0x100>; 148 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 149 rockchip,grf = <&grf>; 150 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 151 clock-names = "tsadc", "apb_pclk"; 152 assigned-clocks = <&cru SCLK_TSADC>; 153 assigned-clock-rates = <50000>; 154 resets = <&cru SRST_TSADC>; 155 reset-names = "tsadc-apb"; 156 #thermal-sensor-cells = <1>; 157 rockchip,hw-tshut-temp = <120000>; 158 status = "disabled"; 159 }; 160 161 pwm0: pwm@ff3d0000 { 162 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 163 reg = <0x0 0xff3d0000 0x0 0x10>; 164 #pwm-cells = <3>; 165 pinctrl-names = "active"; 166 pinctrl-0 = <&pwm0_pin>; 167 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 168 clock-names = "pwm", "pclk"; 169 status = "disabled"; 170 }; 171 172 pwm1: pwm@ff3d0010 { 173 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 174 reg = <0x0 0xff3d0010 0x0 0x10>; 175 #pwm-cells = <3>; 176 pinctrl-names = "active"; 177 pinctrl-0 = <&pwm1_pin>; 178 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 179 clock-names = "pwm", "pclk"; 180 status = "disabled"; 181 }; 182 183 pwm2: pwm@ff3d0020 { 184 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 185 reg = <0x0 0xff3d0020 0x0 0x10>; 186 #pwm-cells = <3>; 187 pinctrl-names = "active"; 188 pinctrl-0 = <&pwm2_pin>; 189 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 190 clock-names = "pwm", "pclk"; 191 status = "disabled"; 192 }; 193 194 pwm3: pwm@ff3d0030 { 195 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 196 reg = <0x0 0xff3d0030 0x0 0x10>; 197 #pwm-cells = <3>; 198 pinctrl-names = "active"; 199 pinctrl-0 = <&pwm3_pin>; 200 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 201 clock-names = "pwm", "pclk"; 202 status = "disabled"; 203 }; 204 205 pwm4: pwm@ff3d8000 { 206 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 207 reg = <0x0 0xff3d8000 0x0 0x10>; 208 #pwm-cells = <3>; 209 pinctrl-names = "active"; 210 pinctrl-0 = <&pwm4_pin>; 211 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 212 clock-names = "pwm", "pclk"; 213 status = "disabled"; 214 }; 215 216 pwm5: pwm@ff3d8010 { 217 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 218 reg = <0x0 0xff3d8010 0x0 0x10>; 219 #pwm-cells = <3>; 220 pinctrl-names = "active"; 221 pinctrl-0 = <&pwm5_pin>; 222 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 223 clock-names = "pwm", "pclk"; 224 status = "disabled"; 225 }; 226 227 pwm6: pwm@ff3d8020 { 228 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 229 reg = <0x0 0xff3d8020 0x0 0x10>; 230 #pwm-cells = <3>; 231 pinctrl-names = "active"; 232 pinctrl-0 = <&pwm6_pin>; 233 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 234 clock-names = "pwm", "pclk"; 235 status = "disabled"; 236 }; 237 238 pwm7: pwm@ff3d8030 { 239 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 240 reg = <0x0 0xff3d8030 0x0 0x10>; 241 #pwm-cells = <3>; 242 pinctrl-names = "active"; 243 pinctrl-0 = <&pwm7_pin>; 244 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 245 clock-names = "pwm", "pclk"; 246 status = "disabled"; 247 }; 248 249 i2c0: i2c@ff410000 { 250 compatible = "rockchip,rk3399-i2c"; 251 reg = <0x0 0xff410000 0x0 0x1000>; 252 clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; 253 clock-names = "i2c", "pclk"; 254 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&i2c0_xfer>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 status = "disabled"; 260 }; 261 262 amba { 263 compatible = "simple-bus"; 264 #address-cells = <2>; 265 #size-cells = <2>; 266 ranges; 267 268 dmac: dmac@ff4e0000 { 269 compatible = "arm,pl330", "arm,primecell"; 270 reg = <0x0 0xff4e0000 0x0 0x4000>; 271 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 272 //clocks = <&cru ACLK_DMAC>; 273 //clock-names = "apb_pclk"; 274 #dma-cells = <1>; 275 peripherals-req-type-burst; 276 }; 277 }; 278 279 i2c1: i2c@ff500000 { 280 compatible = "rockchip,rk3399-i2c"; 281 reg = <0x0 0xff500000 0x0 0x1000>; 282 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 283 clock-names = "i2c", "pclk"; 284 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&i2c1_xfer>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 status = "disabled"; 290 }; 291 292 i2c2: i2c@ff504000 { 293 compatible = "rockchip,rk3399-i2c"; 294 reg = <0x0 0xff504000 0x0 0x1000>; 295 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 296 clock-names = "i2c", "pclk"; 297 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&i2c2m0_xfer>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 status = "disabled"; 303 }; 304 305 i2c3: i2c@ff508000 { 306 compatible = "rockchip,rk3399-i2c"; 307 reg = <0x0 0xff508000 0x0 0x1000>; 308 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 309 clock-names = "i2c", "pclk"; 310 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&i2c3_xfer>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 }; 317 318 i2c4: i2c@ff50c000 { 319 compatible = "rockchip,rk3399-i2c"; 320 reg = <0x0 0xff50c000 0x0 0x1000>; 321 clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; 322 clock-names = "i2c", "pclk"; 323 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c4_xfer>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 i2c5: i2c@ff510000 { 332 compatible = "rockchip,rk3399-i2c"; 333 reg = <0x0 0xff100000 0x0 0x1000>; 334 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 335 clock-names = "i2c", "pclk"; 336 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&i2c5_xfer>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 spi0: spi@ff520000 { 345 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 346 reg = <0x0 0xff520000 0x0 0x1000>; 347 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 351 clock-names = "spiclk", "apb_pclk"; 352 dmas = <&dmac 10>, <&dmac 11>; 353 dma-names = "tx", "rx"; 354 pinctrl-names = "default", "high_speed"; 355 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 356 pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; 357 status = "disabled"; 358 }; 359 360 spi1: spi@ff530000 { 361 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 362 reg = <0x0 0xff530000 0x0 0x1000>; 363 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 367 clock-names = "spiclk", "apb_pclk"; 368 dmas = <&dmac 12>, <&dmac 13>; 369 dma-names = "tx", "rx"; 370 pinctrl-names = "default", "high_speed"; 371 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 372 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; 373 status = "disabled"; 374 }; 375 376 spi2: spi@ff580000 { 377 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 378 reg = <0x0 0xff580000 0x0 0x1000>; 379 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 383 clock-names = "spiclk", "apb_pclk"; 384 dmas = <&dmac 14>, <&dmac 15>; 385 dma-names = "tx", "rx"; 386 pinctrl-names = "default", "high_speed"; 387 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; 388 pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; 389 status = "disabled"; 390 }; 391 392 uart2: serial@ff550000 { 393 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 394 reg = <0x0 0xff550000 0x0 0x100>; 395 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 396 reg-shift = <2>; 397 reg-io-width = <4>; 398 status = "disabled"; 399 }; 400 401 pwm8: pwm@ff5d0000 { 402 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 403 reg = <0x0 0xff5d0000 0x0 0x10>; 404 #pwm-cells = <3>; 405 pinctrl-names = "active"; 406 pinctrl-0 = <&pwm8_pin>; 407 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 408 clock-names = "pwm", "pclk"; 409 status = "disabled"; 410 }; 411 412 pwm9: pwm@fff5d0010 { 413 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 414 reg = <0x0 0xff5d0010 0x0 0x10>; 415 #pwm-cells = <3>; 416 pinctrl-names = "active"; 417 pinctrl-0 = <&pwm9_pin>; 418 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 419 clock-names = "pwm", "pclk"; 420 status = "disabled"; 421 }; 422 423 pwm10: pwm@ff5d0020 { 424 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 425 reg = <0x0 0xff5d0020 0x0 0x10>; 426 #pwm-cells = <3>; 427 pinctrl-names = "active"; 428 pinctrl-0 = <&pwm10_pin>; 429 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 430 clock-names = "pwm", "pclk"; 431 status = "disabled"; 432 }; 433 434 pwm11: pwm@ff5d0030 { 435 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 436 reg = <0x0 0xff5d0030 0x0 0x10>; 437 #pwm-cells = <3>; 438 pinctrl-names = "active"; 439 pinctrl-0 = <&pwm11_pin>; 440 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 441 clock-names = "pwm", "pclk"; 442 status = "disabled"; 443 }; 444 445 sdmmc: dwmmc@ffcf0000 { 446 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 447 reg = <0x0 0xffcf0000 0x0 0x4000>; 448 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 449 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 450 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 451 max-frequency = <150000000>; 452 fifo-depth = <0x100>; 453 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd>; 456 status = "disabled"; 457 }; 458 459 emmc: dwmmc@ffd00000 { 460 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 461 reg = <0x0 0xffd00000 0x0 0x4000>; 462 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 463 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 464 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 465 max-frequency = <150000000>; 466 fifo-depth = <0x100>; 467 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 468 status = "disabled"; 469 }; 470 471 gmac: ethernet@ffdd0000 { 472 compatible = "rockchip,rk1808-gmac"; 473 reg = <0x0 0xffdd0000 0x0 0x10000>; 474 rockchip,grf = <&grf>; 475 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 476 interrupt-names = "macirq"; 477 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 478 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, 479 <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, 480 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; 481 clock-names = "stmmaceth", "mac_clk_rx", 482 "mac_clk_tx", "clk_mac_ref", 483 "clk_mac_refout", "aclk_mac", 484 "pclk_mac", "clk_mac_speed"; 485 phy-mode = "rgmii"; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&rgmii_pins>; 488 resets = <&cru SRST_GAMC_A>; 489 reset-names = "stmmaceth"; 490 /* power-domains = <&power RK1808_PD_GMAC>; */ 491 status = "disabled"; 492 }; 493 494 pinctrl: pinctrl { 495 compatible = "rockchip,rk1808-pinctrl"; 496 rockchip,grf = <&grf>; 497 rockchip,pmu = <&pmugrf>; 498 #address-cells = <2>; 499 #size-cells = <2>; 500 ranges; 501 502 gpio0: gpio0@ff4c0000 { 503 compatible = "rockchip,gpio-bank"; 504 reg = <0x0 0xff4c0000 0x0 0x100>; 505 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cru SCLK_PMU_GPIO0>, <&cru PCLK_GPIO0_PMU>; 507 gpio-controller; 508 #gpio-cells = <2>; 509 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 }; 513 514 gpio1: gpio1@ff690000 { 515 compatible = "rockchip,gpio-bank"; 516 reg = <0x0 0xff690000 0x0 0x100>; 517 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cru SCLK_GPIO1>, <&cru PCLK_GPIO1>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 }; 525 526 gpio2: gpio2@ff6a0000 { 527 compatible = "rockchip,gpio-bank"; 528 reg = <0x0 0xff6a0000 0x0 0x100>; 529 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cru SCLK_GPIO2>, <&cru PCLK_GPIO2>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 538 gpio3: gpio3@ff6b0000 { 539 compatible = "rockchip,gpio-bank"; 540 reg = <0x0 0xff6b0000 0x0 0x100>; 541 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cru SCLK_GPIO3>, <&cru PCLK_GPIO3>; 543 gpio-controller; 544 #gpio-cells = <2>; 545 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 550 gpio4: gpio4@ff6c0000 { 551 compatible = "rockchip,gpio-bank"; 552 reg = <0x0 0xff6c0000 0x0 0x100>; 553 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&cru SCLK_GPIO4>, <&cru PCLK_GPIO4>; 555 gpio-controller; 556 #gpio-cells = <2>; 557 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 }; 561 562 pcfg_pull_up: pcfg-pull-up { 563 bias-pull-up; 564 }; 565 566 pcfg_pull_down: pcfg-pull-down { 567 bias-pull-down; 568 }; 569 570 pcfg_pull_none: pcfg-pull-none { 571 bias-disable; 572 }; 573 574 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 575 bias-disable; 576 drive-strength = <2>; 577 }; 578 579 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 580 bias-pull-up; 581 drive-strength = <2>; 582 }; 583 584 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 585 bias-pull-up; 586 drive-strength = <4>; 587 }; 588 589 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 590 bias-disable; 591 drive-strength = <4>; 592 }; 593 594 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 595 bias-pull-down; 596 drive-strength = <4>; 597 }; 598 599 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 600 bias-disable; 601 drive-strength = <8>; 602 }; 603 604 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 605 bias-pull-up; 606 drive-strength = <8>; 607 }; 608 609 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 610 bias-disable; 611 drive-strength = <12>; 612 }; 613 614 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 615 bias-pull-up; 616 drive-strength = <12>; 617 }; 618 619 pcfg_pull_none_smt: pcfg-pull-none-smt { 620 bias-disable; 621 input-schmitt-enable; 622 }; 623 624 pcfg_output_high: pcfg-output-high { 625 output-high; 626 }; 627 628 pcfg_output_low: pcfg-output-low { 629 output-low; 630 }; 631 632 pcfg_input_high: pcfg-input-high { 633 bias-pull-up; 634 input-enable; 635 }; 636 637 pcfg_input: pcfg-input { 638 input-enable; 639 }; 640 641 emmc { 642 emmc_clk: emmc-clk { 643 rockchip,pins = 644 /* emmc_clkout */ 645 <1 9 1 &pcfg_pull_none>; 646 }; 647 648 emmc_rstnout: emmc-rstnout { 649 rockchip,pins = 650 /* emmc_rstn */ 651 <1 11 1 &pcfg_pull_none>; 652 }; 653 654 emmc_bus8: emmc-bus8 { 655 rockchip,pins = 656 /* emmc_d0 */ 657 <1 RK_PA0 1 &pcfg_pull_none>, 658 /* emmc_d1 */ 659 <1 RK_PA1 1 &pcfg_pull_none>, 660 /* emmc_d2 */ 661 <1 RK_PA2 1 &pcfg_pull_none>, 662 /* emmc_d3 */ 663 <1 RK_PA3 1 &pcfg_pull_none>, 664 /* emmc_d4 */ 665 <1 RK_PA4 1 &pcfg_pull_none>, 666 /* emmc_d5 */ 667 <1 RK_PA5 1 &pcfg_pull_none>, 668 /* emmc_d6 */ 669 <1 RK_PA6 1 &pcfg_pull_none>, 670 /* emmc_d7 */ 671 <1 RK_PA7 1 &pcfg_pull_none>; 672 }; 673 674 emmc_pwren: emmc-pwren { 675 rockchip,pins = 676 <1 RK_PB0 1 &pcfg_pull_none>; 677 }; 678 679 emmc_cmd: emmc-cmd { 680 rockchip,pins = 681 <1 RK_PB2 1 &pcfg_pull_none>; 682 }; 683 }; 684 685 gmac { 686 rgmii_pins: rgmii-pins { 687 rockchip,pins = 688 /* rgmii_txen */ 689 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 690 /* rgmii_txd1 */ 691 <2 RK_PA2 2 &pcfg_pull_none_12ma>, 692 /* rgmii_txd0 */ 693 <2 RK_PA3 2 &pcfg_pull_none_12ma>, 694 /* rgmii_rxd0 */ 695 <2 RK_PA4 2 &pcfg_pull_none>, 696 /* rgmii_rxd1 */ 697 <2 RK_PA5 2 &pcfg_pull_none>, 698 /* rgmii_rxdv */ 699 <2 RK_PA7 2 &pcfg_pull_none>, 700 /* rgmii_mdio */ 701 <2 RK_PB0 2 &pcfg_pull_none>, 702 /* rgmii_mdc */ 703 <2 RK_PB2 2 &pcfg_pull_none>, 704 /* rgmii_txd3 */ 705 <2 RK_PB3 2 &pcfg_pull_none_12ma>, 706 /* rgmii_txd2 */ 707 <2 RK_PB4 2 &pcfg_pull_none_12ma>, 708 /* rgmii_rxd2 */ 709 <2 RK_PB5 2 &pcfg_pull_none>, 710 /* rgmii_rxd3 */ 711 <2 RK_PB6 2 &pcfg_pull_none>, 712 /* rgmii_clk */ 713 <2 RK_PB7 2 &pcfg_pull_none>, 714 /* rgmii_txclk */ 715 <2 RK_PC1 2 &pcfg_pull_none_12ma>, 716 /* rgmii_rxclk */ 717 <2 RK_PC2 2 &pcfg_pull_none>; 718 }; 719 720 rmii_pins: rmii-pins { 721 rockchip,pins = 722 /* rmii_txen */ 723 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 724 /* rmii_txd1 */ 725 <2 RK_PA2 2 &pcfg_pull_none_12ma>, 726 /* rmii_txd0 */ 727 <2 RK_PA3 2 &pcfg_pull_none_12ma>, 728 /* rmii_rxd0 */ 729 <2 RK_PA4 2 &pcfg_pull_none>, 730 /* rmii_rxd1 */ 731 <2 RK_PA5 2 &pcfg_pull_none>, 732 /* rmii_rxer */ 733 <2 RK_PA6 2 &pcfg_pull_none>, 734 /* rmii_rxdv */ 735 <2 RK_PA7 2 &pcfg_pull_none>, 736 /* rmii_mdio */ 737 <2 RK_PB0 2 &pcfg_pull_none>, 738 /* rmii_mdc */ 739 <2 RK_PB2 2 &pcfg_pull_none>, 740 /* rmii_clk */ 741 <2 RK_PB7 2 &pcfg_pull_none>; 742 }; 743 }; 744 745 i2c0 { 746 i2c0_xfer: i2c0-xfer { 747 rockchip,pins = 748 /* i2c0_sda */ 749 <0 RK_PB1 1 &pcfg_pull_none_smt>, 750 /* i2c0_scl */ 751 <0 RK_PB0 1 &pcfg_pull_none_smt>; 752 }; 753 }; 754 755 i2c1 { 756 i2c1_xfer: i2c1-xfer { 757 rockchip,pins = 758 /* i2c1_sda */ 759 <0 RK_PC1 1 &pcfg_pull_none_smt>, 760 /* i2c1_scl */ 761 <0 RK_PC0 1 &pcfg_pull_none_smt>; 762 }; 763 }; 764 765 i2c2m0 { 766 i2c2m0_xfer: i2c2m0-xfer { 767 rockchip,pins = 768 /* i2c2m0_sda */ 769 <3 RK_PB4 2 &pcfg_pull_none_smt>, 770 /* i2c2m0_scl */ 771 <3 RK_PB3 2 &pcfg_pull_none_smt>; 772 }; 773 }; 774 775 i2c3 { 776 i2c3_xfer: i2c3-xfer { 777 rockchip,pins = 778 /* i2c3_sda */ 779 <2 RK_PD1 1 &pcfg_pull_none_smt>, 780 /* i2c3_scl */ 781 <2 RK_PD0 1 &pcfg_pull_none_smt>; 782 }; 783 }; 784 785 i2c4 { 786 i2c4_xfer: i2c4-xfer { 787 rockchip,pins = 788 /* i2c4_sda */ 789 <3 RK_PC3 3 &pcfg_pull_none_smt>, 790 /* i2c4_scl */ 791 <3 RK_PC2 3 &pcfg_pull_none_smt>; 792 }; 793 }; 794 795 i2c5 { 796 i2c5_xfer: i2c5-xfer { 797 rockchip,pins = 798 /* i2c5_sda */ 799 <4 RK_PC2 1 &pcfg_pull_none_smt>, 800 /* i2c5_scl */ 801 <4 RK_PC1 1 &pcfg_pull_none_smt>; 802 }; 803 }; 804 805 i2s1 { 806 i2s1_2ch_lrck: i2s1-2ch-lrck { 807 rockchip,pins = 808 <3 RK_PA0 1 &pcfg_pull_none>; 809 }; 810 i2s1_2ch_sclk: i2s1-2ch-sclk { 811 rockchip,pins = 812 <3 RK_PA1 1 &pcfg_pull_none>; 813 }; 814 i2s1_2ch_mclk: i2s1-2ch-mclk { 815 rockchip,pins = 816 <3 RK_PA2 1 &pcfg_pull_none>; 817 }; 818 i2s1_2ch_sdo: i2s1-2ch-sdo { 819 rockchip,pins = 820 <3 RK_PA3 1 &pcfg_pull_none>; 821 }; 822 i2s1_2ch_sdi: i2s1-2ch-sdi { 823 rockchip,pins = 824 <3 RK_PA4 1 &pcfg_pull_none>; 825 }; 826 }; 827 828 i2s0 { 829 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 830 rockchip,pins = 831 <3 RK_PA5 1 &pcfg_pull_none>; 832 }; 833 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 834 rockchip,pins = 835 <3 RK_PA6 1 &pcfg_pull_none>; 836 }; 837 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 838 rockchip,pins = 839 <3 RK_PA7 1 &pcfg_pull_none>; 840 }; 841 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 842 rockchip,pins = 843 <3 RK_PB0 1 &pcfg_pull_none>; 844 }; 845 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 846 rockchip,pins = 847 <3 RK_PB1 1 &pcfg_pull_none>; 848 }; 849 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 850 rockchip,pins = 851 <3 RK_PB2 1 &pcfg_pull_none>; 852 }; 853 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 854 rockchip,pins = 855 <3 RK_PB3 1 &pcfg_pull_none>; 856 }; 857 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 858 rockchip,pins = 859 <3 RK_PB4 1 &pcfg_pull_none>; 860 }; 861 i2s0_8ch_mclk: i2s0-8ch-mclk { 862 rockchip,pins = 863 <3 RK_PB5 1 &pcfg_pull_none>; 864 }; 865 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 866 rockchip,pins = 867 <3 RK_PB6 1 &pcfg_pull_none>; 868 }; 869 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 870 rockchip,pins = 871 <3 RK_PB7 1 &pcfg_pull_none>; 872 }; 873 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 874 rockchip,pins = 875 <3 RK_PC0 1 &pcfg_pull_none>; 876 }; 877 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 878 rockchip,pins = 879 <3 RK_PC1 1 &pcfg_pull_none>; 880 }; 881 }; 882 883 pciusb { 884 pciusb_pins: pciusb-pins { 885 rockchip,pins = 886 /* pciusb_debug0 */ 887 <4 RK_PB4 3 &pcfg_pull_none>, 888 /* pciusb_debug1 */ 889 <4 RK_PB5 3 &pcfg_pull_none>, 890 /* pciusb_debug2 */ 891 <4 RK_PB6 3 &pcfg_pull_none>, 892 /* pciusb_debug3 */ 893 <4 RK_PB7 3 &pcfg_pull_none>, 894 /* pciusb_debug4 */ 895 <4 RK_PC0 3 &pcfg_pull_none>, 896 /* pciusb_debug5 */ 897 <4 RK_PC1 3 &pcfg_pull_none>, 898 /* pciusb_debug6 */ 899 <4 RK_PC2 3 &pcfg_pull_none>, 900 /* pciusb_debug7 */ 901 <4 RK_PC3 3 &pcfg_pull_none>; 902 }; 903 }; 904 905 pdm { 906 pdm_clk: pdm-clk { 907 rockchip,pins = 908 /* pdm_clk0 */ 909 <3 RK_PB0 2 &pcfg_pull_none>; 910 }; 911 912 pdm_sdi3: pdm-sdi3 { 913 rockchip,pins = 914 <3 RK_PA5 2 &pcfg_pull_none>; 915 }; 916 917 pdm_sdi2: pdm-sdi2 { 918 rockchip,pins = 919 <3 RK_PA6 2 &pcfg_pull_none>; 920 }; 921 922 pdm_sdi1: pdm-sdi1 { 923 rockchip,pins = 924 <3 RK_PA7 2 &pcfg_pull_none>; 925 }; 926 927 pdm_clk1: pdm-clk1 { 928 rockchip,pins = 929 <3 RK_PB1 2 &pcfg_pull_none>; 930 }; 931 932 pdm_sdi0: pdm-sdi0 { 933 rockchip,pins = 934 <3 RK_PC1 2 &pcfg_pull_none>; 935 }; 936 }; 937 938 pwm0 { 939 pwm0_pin: pwm0-pin { 940 rockchip,pins = 941 <0 RK_PB7 1 &pcfg_pull_none>; 942 }; 943 }; 944 945 pwm1 { 946 pwm1_pin: pwm1-pin { 947 rockchip,pins = 948 <0 RK_PC3 1 &pcfg_pull_none>; 949 }; 950 }; 951 952 pwm2 { 953 pwm2_pin: pwm2-pin { 954 rockchip,pins = 955 <0 RK_PC5 1 &pcfg_pull_none>; 956 }; 957 }; 958 959 pwm3 { 960 pwm3_pin: pwm3-pin { 961 rockchip,pins = 962 <0 RK_PC4 1 &pcfg_pull_none>; 963 }; 964 }; 965 966 pwm4 { 967 pwm4_pin: pwm4-pin { 968 rockchip,pins = 969 <1 RK_PB6 2 &pcfg_pull_none>; 970 }; 971 }; 972 973 pwm5 { 974 pwm5_pin: pwm5-pin { 975 rockchip,pins = 976 <1 RK_PB7 2 &pcfg_pull_none>; 977 }; 978 }; 979 pwm6 { 980 pwm6_pin: pwm6-pin { 981 rockchip,pins = 982 <3 RK_PA1 2 &pcfg_pull_none>; 983 }; 984 }; 985 986 pwm7 { 987 pwm7_pin: pwm7-pin { 988 rockchip,pins = 989 <3 RK_PA2 2 &pcfg_pull_none>; 990 }; 991 }; 992 993 pwm8 { 994 pwm8_pin: pwm8-pin { 995 rockchip,pins = 996 <3 RK_PD0 2 &pcfg_pull_none>; 997 }; 998 }; 999 1000 pwm9 { 1001 pwm9_pin: pwm9-pin { 1002 rockchip,pins = 1003 <3 RK_PD1 2 &pcfg_pull_none>; 1004 }; 1005 }; 1006 1007 pwm10 { 1008 pwm10_pin: pwm10-pin { 1009 rockchip,pins = 1010 <3 RK_PD2 2 &pcfg_pull_none>; 1011 }; 1012 }; 1013 1014 pwm11 { 1015 pwm11_pin: pwm11-pin { 1016 rockchip,pins = 1017 <3 RK_PD3 2 &pcfg_pull_none>; 1018 }; 1019 }; 1020 1021 sdmmc0 { 1022 sdmmc0_bus4: sdmmc0-bus4 { 1023 rockchip,pins = 1024 /* sdmmc0_d0 */ 1025 <4 RK_PA2 1 &pcfg_pull_none>, 1026 /* sdmmc0_d1 */ 1027 <4 RK_PA3 1 &pcfg_pull_none>, 1028 /* sdmmc0_d2 */ 1029 <4 RK_PA4 1 &pcfg_pull_none>, 1030 /* sdmmc0_d3 */ 1031 <4 RK_PA5 1 &pcfg_pull_none>; 1032 }; 1033 sdmmc0_cmd: sdmmc0-cmd { 1034 rockchip,pins = 1035 <4 RK_PA0 1 &pcfg_pull_none>; 1036 }; 1037 sdmmc0_clk: sdmmc0-clk { 1038 rockchip,pins = 1039 <4 RK_PA1 1 &pcfg_pull_none>; 1040 }; 1041 }; 1042 1043 sdmmc1 { 1044 sdmmc1_bus4: sdmmc1-bus4 { 1045 rockchip,pins = 1046 /* sdmmc1_d0 */ 1047 <4 RK_PB0 1 &pcfg_pull_none>, 1048 /* sdmmc1_d1 */ 1049 <4 RK_PB1 1 &pcfg_pull_none>, 1050 /* sdmmc1_d2 */ 1051 <4 RK_PB2 1 &pcfg_pull_none>, 1052 /* sdmmc1_d3 */ 1053 <4 RK_PB3 1 &pcfg_pull_none>; 1054 }; 1055 1056 sdmmc1_cmd: sdmmc1-cmd { 1057 rockchip,pins = 1058 <4 RK_PA6 1 &pcfg_pull_none>; 1059 }; 1060 1061 sdmmc1_clk: sdmmc1-clk { 1062 rockchip,pins = 1063 <4 RK_PB1 1 &pcfg_pull_none>; 1064 }; 1065 }; 1066 1067 spi0 { 1068 spi0_mosi: spi0-mosi { 1069 rockchip,pins = 1070 <1 RK_PB4 1 &pcfg_pull_up_4ma>; 1071 }; 1072 1073 spi0_miso: spi0-miso { 1074 rockchip,pins = 1075 <1 RK_PB5 1 &pcfg_pull_up_4ma>; 1076 }; 1077 1078 spi0_csn: spi0-csn { 1079 rockchip,pins = 1080 <1 RK_PB6 1 &pcfg_pull_up_4ma>; 1081 }; 1082 1083 spi0_clk: spi0-clk { 1084 rockchip,pins = 1085 <1 RK_PB7 1 &pcfg_pull_up_4ma>; 1086 }; 1087 1088 spi0_mosi_hs: spi0-mosi-hs { 1089 rockchip,pins = 1090 <1 RK_PB4 1 &pcfg_pull_up_8ma>; 1091 }; 1092 1093 spi0_miso_hs: spi0-miso-hs { 1094 rockchip,pins = 1095 <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1096 }; 1097 1098 spi0_csn_hs: spi0-csn-hs { 1099 rockchip,pins = 1100 <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1101 }; 1102 1103 spi0_clk_hs: spi0-clk-hs { 1104 rockchip,pins = 1105 <1 RK_PB7 1 &pcfg_pull_up_8ma>; 1106 }; 1107 }; 1108 1109 spi1 { 1110 spi1_clk: spi1-clk { 1111 rockchip,pins = 1112 <4 RK_PB4 2 &pcfg_pull_up_4ma>; 1113 }; 1114 1115 spi1_mosi: spi1-mosi { 1116 rockchip,pins = 1117 <4 RK_PB5 2 &pcfg_pull_up_4ma>; 1118 }; 1119 1120 spi1_csn0: spi1-csn0 { 1121 rockchip,pins = 1122 <4 RK_PB6 2 &pcfg_pull_up_4ma>; 1123 }; 1124 1125 spi1_miso: spi1-miso { 1126 rockchip,pins = 1127 <4 RK_PB7 2 &pcfg_pull_up_4ma>; 1128 }; 1129 1130 spi1_csn1: spi1-csn1 { 1131 rockchip,pins = 1132 <4 RK_PC0 2 &pcfg_pull_up_4ma>; 1133 }; 1134 1135 spi1_clk_hs: spi1-clk-hs { 1136 rockchip,pins = 1137 <4 RK_PB4 2 &pcfg_pull_up_8ma>; 1138 }; 1139 1140 spi1_mosi_hs: spi1-mosi-hs { 1141 rockchip,pins = 1142 <4 RK_PB5 2 &pcfg_pull_up_8ma>; 1143 }; 1144 1145 spi1_csn0_hs: spi1-csn0-hs { 1146 rockchip,pins = 1147 <4 RK_PB6 2 &pcfg_pull_up_8ma>; 1148 }; 1149 1150 spi1_miso_hs: spi1-miso-hs { 1151 rockchip,pins = 1152 <4 RK_PB7 2 &pcfg_pull_up_8ma>; 1153 }; 1154 1155 spi1_csn1_hs: spi1-csn1-hs { 1156 rockchip,pins = 1157 <4 RK_PC0 2 &pcfg_pull_up_8ma>; 1158 }; 1159 }; 1160 1161 spi1m1 { 1162 spi1m1_clk: spi1m1-clk { 1163 rockchip,pins = 1164 <3 RK_PC7 3 &pcfg_pull_up_4ma>; 1165 }; 1166 1167 spi1m1_mosi: spi1m1-mosi { 1168 rockchip,pins = 1169 <3 RK_PD0 3 &pcfg_pull_up_4ma>; 1170 }; 1171 1172 spi1m1_csn0: spi1m1-csn0 { 1173 rockchip,pins = 1174 <3 RK_PD1 3 &pcfg_pull_up_4ma>; 1175 }; 1176 1177 spi1m1_miso: spi1m1-miso { 1178 rockchip,pins = 1179 <3 RK_PD2 3 &pcfg_pull_up_4ma>; 1180 }; 1181 1182 spi1m1_csn1: spi1m1-csn1 { 1183 rockchip,pins = 1184 <3 RK_PD3 3 &pcfg_pull_up_4ma>; 1185 }; 1186 1187 spi1m1_clk_hs: spi1m1-clk-hs { 1188 rockchip,pins = 1189 <3 RK_PC7 3 &pcfg_pull_none>; 1190 }; 1191 1192 spi1m1_mosi_hs: spi1m1-mosi-hs { 1193 rockchip,pins = 1194 <3 RK_PD0 3 &pcfg_pull_none>; 1195 }; 1196 1197 spi1m1_csn0_hs: spi1m1-csn0-hs { 1198 rockchip,pins = 1199 <3 RK_PD1 3 &pcfg_pull_none>; 1200 }; 1201 1202 spi1m1_miso_hs: spi1m1-miso-hs { 1203 rockchip,pins = 1204 <3 RK_PD2 3 &pcfg_pull_none>; 1205 }; 1206 1207 spi1m1_csn1_hs: spi1m1-csn1-hs { 1208 rockchip,pins = 1209 <3 RK_PD3 3 &pcfg_pull_none>; 1210 }; 1211 }; 1212 1213 spi2m0 { 1214 spi2m0_miso: spi2m0-miso { 1215 rockchip,pins = 1216 <1 RK_PA6 2 &pcfg_pull_up_4ma>; 1217 }; 1218 1219 spi2m0_clk: spi2m0-clk { 1220 rockchip,pins = 1221 <1 RK_PA7 2 &pcfg_pull_up_4ma>; 1222 }; 1223 1224 spi2m0_mosi: spi2m0-mosi { 1225 rockchip,pins = 1226 <1 RK_PB0 2 &pcfg_pull_up_4ma>; 1227 }; 1228 1229 spi2m0_csn: spi2m0-csn { 1230 rockchip,pins = 1231 <1 RK_PB1 2 &pcfg_pull_up_4ma>; 1232 }; 1233 1234 spi2m0_miso_hs: spi2m0-miso-hs { 1235 rockchip,pins = 1236 <1 RK_PA6 2 &pcfg_pull_none>; 1237 }; 1238 1239 spi2m0_clk_hs: spi2m0-clk-hs { 1240 rockchip,pins = 1241 <1 RK_PA7 2 &pcfg_pull_none>; 1242 }; 1243 1244 spi2m0_mosi_hs: spi2m0-mosi-hs { 1245 rockchip,pins = 1246 <1 RK_PB0 2 &pcfg_pull_none>; 1247 }; 1248 1249 spi2m0_csn_hs: spi2m0-csn-hs { 1250 rockchip,pins = 1251 <1 RK_PB1 2 &pcfg_pull_none>; 1252 }; 1253 }; 1254 1255 spi2m1 { 1256 spi2m1_miso: spi2m1-miso { 1257 rockchip,pins = 1258 <2 RK_PA4 3 &pcfg_pull_up_4ma>; 1259 }; 1260 1261 spi2m1_clk: spi2m1-clk { 1262 rockchip,pins = 1263 <2 RK_PA5 3 &pcfg_pull_up_4ma>; 1264 }; 1265 1266 spi2m1_mosi: spi2m1-mosi { 1267 rockchip,pins = 1268 <2 RK_PA6 3 &pcfg_pull_up_4ma>; 1269 }; 1270 1271 spi2m1_csn: spi2m1-csn { 1272 rockchip,pins = 1273 <2 RK_PA7 3 &pcfg_pull_up_4ma>; 1274 }; 1275 1276 spi2m1_miso_hs: spi2m1-miso-hs { 1277 rockchip,pins = 1278 <2 RK_PA4 3 &pcfg_pull_none>; 1279 }; 1280 1281 spi2m1_clk_hs: spi2m1-clk-hs { 1282 rockchip,pins = 1283 <2 RK_PA5 3 &pcfg_pull_none>; 1284 }; 1285 1286 spi2m1_mosi_hs: spi2m1-mosi-hs { 1287 rockchip,pins = 1288 <2 RK_PA6 3 &pcfg_pull_none>; 1289 }; 1290 1291 spi2m1_csn_hs: spi2m1-csn-hs { 1292 rockchip,pins = 1293 <2 RK_PA7 3 &pcfg_pull_none>; 1294 }; 1295 }; 1296 1297 uart2m0 { 1298 uart2m0_xfer: uart2m0-xfer { 1299 rockchip,pins = 1300 /* uart2_rxm0 */ 1301 <4 RK_PA3 2 &pcfg_pull_none>, 1302 /* uart2_txm0 */ 1303 <4 RK_PA2 2 &pcfg_pull_none>; 1304 }; 1305 }; 1306 1307 uart2m1 { 1308 uart2m1_xfer: uart2m1-xfer { 1309 rockchip,pins = 1310 /* uart2_rxm1 */ 1311 <2 RK_PD1 2 &pcfg_pull_none>, 1312 /* uart2_txm1 */ 1313 <2 RK_PD0 2 &pcfg_pull_none>; 1314 }; 1315 }; 1316 1317 uart2m2 { 1318 uart2m2_xfer: uart2m2-xfer { 1319 rockchip,pins = 1320 /* uart2_rxm2 */ 1321 <3 RK_PA4 2 &pcfg_pull_none>, 1322 /* uart2_txm2 */ 1323 <3 RK_PA3 2 &pcfg_pull_none>; 1324 }; 1325 }; 1326 tsadc { 1327 tsadc_otp_gpio: tsadc-otp-gpio { 1328 rockchip,pins = 1329 <0 RK_PA6 0 &pcfg_pull_none>; 1330 }; 1331 1332 tsadc_otp_out: tsadc-otp-out { 1333 rockchip,pins = 1334 <0 RK_PA6 2 &pcfg_pull_none>; 1335 }; 1336 }; 1337 }; 1338}; 1339