1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 dmc: dmc { 73 compatible = "rockchip,px30-dmc", "syscon"; 74 reg = <0x0 0xff2a0000 0x0 0x1000>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vopb_out>, <&vopl_out>; 80 status = "disabled"; 81 }; 82 83 firmware { 84 optee { 85 compatible = "linaro,optee-tz"; 86 method = "smc"; 87 }; 88 }; 89 90 gmac_clkin: external-gmac-clock { 91 compatible = "fixed-clock"; 92 clock-frequency = <50000000>; 93 clock-output-names = "gmac_clkin"; 94 #clock-cells = <0>; 95 }; 96 97 psci { 98 compatible = "arm,psci-1.0"; 99 method = "smc"; 100 }; 101 102 timer { 103 compatible = "arm,armv8-timer"; 104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 108 }; 109 110 xin24m: xin24m { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <24000000>; 114 clock-output-names = "xin24m"; 115 }; 116 117 pmu: power-management@ff000000 { 118 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 119 reg = <0x0 0xff000000 0x0 0x1000>; 120 121 power: power-controller { 122 compatible = "rockchip,px30-power-controller"; 123 #power-domain-cells = <1>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* These power domains are grouped by VD_LOGIC */ 129 pd_usb@PX30_PD_USB { 130 reg = <PX30_PD_USB>; 131 clocks = <&cru HCLK_HOST>, 132 <&cru HCLK_OTG>, 133 <&cru SCLK_OTG_ADP>; 134 }; 135 pd_sdcard@PX30_PD_SDCARD { 136 reg = <PX30_PD_SDCARD>; 137 clocks = <&cru HCLK_SDMMC>, 138 <&cru SCLK_SDMMC>; 139 }; 140 pd_gmac@PX30_PD_GMAC { 141 reg = <PX30_PD_GMAC>; 142 clocks = <&cru ACLK_GMAC>, 143 <&cru PCLK_GMAC>, 144 <&cru SCLK_MAC_REF>, 145 <&cru SCLK_GMAC_RX_TX>; 146 }; 147 pd_mmc_nand@PX30_PD_MMC_NAND { 148 reg = <PX30_PD_MMC_NAND>; 149 clocks = <&cru HCLK_NANDC>, 150 <&cru HCLK_EMMC>, 151 <&cru HCLK_SDIO>, 152 <&cru HCLK_SFC>, 153 <&cru SCLK_EMMC>, 154 <&cru SCLK_NANDC>, 155 <&cru SCLK_SDIO>, 156 <&cru SCLK_SFC>; 157 }; 158 pd_vpu@PX30_PD_VPU { 159 reg = <PX30_PD_VPU>; 160 clocks = <&cru ACLK_VPU>, 161 <&cru HCLK_VPU>, 162 <&cru SCLK_CORE_VPU>; 163 }; 164 pd_vo@PX30_PD_VO { 165 reg = <PX30_PD_VO>; 166 clocks = <&cru ACLK_RGA>, 167 <&cru ACLK_VOPB>, 168 <&cru ACLK_VOPL>, 169 <&cru DCLK_VOPB>, 170 <&cru DCLK_VOPL>, 171 <&cru HCLK_RGA>, 172 <&cru HCLK_VOPB>, 173 <&cru HCLK_VOPL>, 174 <&cru PCLK_MIPI_DSI>, 175 <&cru SCLK_RGA_CORE>, 176 <&cru SCLK_VOPB_PWM>; 177 }; 178 pd_vi@PX30_PD_VI { 179 reg = <PX30_PD_VI>; 180 clocks = <&cru ACLK_CIF>, 181 <&cru ACLK_ISP>, 182 <&cru HCLK_CIF>, 183 <&cru HCLK_ISP>, 184 <&cru SCLK_ISP>; 185 }; 186 pd_gpu@PX30_PD_GPU { 187 reg = <PX30_PD_GPU>; 188 clocks = <&cru ACLK_GPU>; 189 }; 190 }; 191 }; 192 193 pmugrf: syscon@ff010000 { 194 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 195 reg = <0x0 0xff010000 0x0 0x1000>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 199 pmu_io_domains: io-domains { 200 compatible = "rockchip,px30-pmu-io-voltage-domain"; 201 status = "disabled"; 202 }; 203 204 reboot-mode { 205 compatible = "syscon-reboot-mode"; 206 offset = <0x200>; 207 mode-bootloader = <BOOT_BL_DOWNLOAD>; 208 mode-charge = <BOOT_CHARGING>; 209 mode-fastboot = <BOOT_FASTBOOT>; 210 mode-loader = <BOOT_BL_DOWNLOAD>; 211 mode-normal = <BOOT_NORMAL>; 212 mode-recovery = <BOOT_RECOVERY>; 213 mode-ums = <BOOT_UMS>; 214 }; 215 216 pmu_pvtm: pmu-pvtm { 217 compatible = "rockchip,px30-pmu-pvtm"; 218 clocks = <&pmucru SCLK_PVTM_PMU>; 219 clock-names = "pmu"; 220 status = "disabled"; 221 }; 222 }; 223 224 uart0: serial@ff030000 { 225 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 226 reg = <0x0 0xff030000 0x0 0x100>; 227 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 229 clock-names = "baudclk", "apb_pclk"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 dmas = <&dmac 0>, <&dmac 1>; 233 #dma-cells = <2>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 236 status = "disabled"; 237 }; 238 239 i2s0_8ch: i2s@ff060000 { 240 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 241 reg = <0x0 0xff060000 0x0 0x1000>; 242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 244 clock-names = "i2s_clk", "i2s_hclk"; 245 dmas = <&dmac 16>, <&dmac 17>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 i2s1_2ch: i2s@ff070000 { 251 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 252 reg = <0x0 0xff070000 0x0 0x1000>; 253 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 255 clock-names = "i2s_clk", "i2s_hclk"; 256 dmas = <&dmac 18>, <&dmac 19>; 257 dma-names = "tx", "rx"; 258 status = "disabled"; 259 }; 260 261 i2s2_2ch: i2s@ff080000 { 262 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 263 reg = <0x0 0xff080000 0x0 0x1000>; 264 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 266 clock-names = "i2s_clk", "i2s_hclk"; 267 dmas = <&dmac 20>, <&dmac 21>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 pdm: pdm@ff0a0000 { 273 compatible = "rockchip,pdm"; 274 reg = <0x0 0xff0a0000 0x0 0x1000>; 275 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 276 clock-names = "pdm_clk", "pdm_hclk"; 277 dmas = <&dmac 24>; 278 dma-names = "rx"; 279 status = "disabled"; 280 }; 281 282 crypto: crypto@ff0b0000 { 283 compatible = "rockchip,px30-crypto"; 284 reg = <0x0 0xff0b0000 0x0 0x4000>; 285 clock-names = "sclk_crypto", "apkclk_crypto"; 286 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 287 clock-frequency = <200000000>, <300000000>; 288 status = "disabled"; 289 }; 290 291 secure_otp: secure_otp@ff110000 { 292 compatible = "rockchip,px30-secure-otp"; 293 reg = <0x0 0xff110000 0x0 0x4000>; 294 secure_conf = <0xff11C008>; 295 mask_addr = <0xff2d0000>; 296 }; 297 298 gic: interrupt-controller@ff131000 { 299 compatible = "arm,gic-400"; 300 #interrupt-cells = <3>; 301 #address-cells = <0>; 302 interrupt-controller; 303 reg = <0x0 0xff131000 0 0x1000>, 304 <0x0 0xff132000 0 0x2000>, 305 <0x0 0xff134000 0 0x2000>, 306 <0x0 0xff136000 0 0x2000>; 307 interrupts = <GIC_PPI 9 308 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 309 }; 310 311 grf: syscon@ff140000 { 312 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 313 reg = <0x0 0xff140000 0x0 0x1000>; 314 #address-cells = <1>; 315 #size-cells = <1>; 316 317 io_domains: io-domains { 318 compatible = "rockchip,px30-io-voltage-domain"; 319 status = "disabled"; 320 }; 321 322 lvds: lvds { 323 compatible = "rockchip,px30-lvds"; 324 phys = <&video_phy>; 325 phy-names = "phy"; 326 status = "disabled"; 327 328 ports { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 332 port@0 { 333 reg = <0>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 lvds_in_vopb: endpoint@0 { 338 reg = <0>; 339 remote-endpoint = <&vopb_out_lvds>; 340 }; 341 342 lvds_in_vopl: endpoint@1 { 343 reg = <1>; 344 remote-endpoint = <&vopl_out_lvds>; 345 }; 346 }; 347 }; 348 }; 349 350 rgb: rgb { 351 compatible = "rockchip,px30-rgb"; 352 pinctrl-names = "default", "sleep"; 353 pinctrl-0 = <&lcdc_m0_rgb_pins>; 354 pinctrl-1 = <&lcdc_m0_sleep_pins>; 355 status = "disabled"; 356 357 ports { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 port@0 { 362 reg = <0>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 366 rgb_in_vopb: endpoint@0 { 367 reg = <0>; 368 remote-endpoint = <&vopb_out_rgb>; 369 }; 370 371 rgb_in_vopl: endpoint@1 { 372 reg = <1>; 373 remote-endpoint = <&vopl_out_rgb>; 374 }; 375 }; 376 }; 377 }; 378 }; 379 380 core_grf: syscon@ff148000 { 381 compatible = "syscon", "simple-mfd"; 382 reg = <0x0 0xff148000 0x0 0x1000>; 383 #address-cells = <1>; 384 #size-cells = <1>; 385 386 pvtm: pvtm { 387 compatible = "rockchip,px30-pvtm"; 388 clocks = <&cru SCLK_PVTM>; 389 clock-names = "core"; 390 status = "disabled"; 391 }; 392 }; 393 394 uart1: serial@ff158000 { 395 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 396 reg = <0x0 0xff158000 0x0 0x100>; 397 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 399 clock-names = "sclk_uart", "pclk_uart"; 400 reg-shift = <2>; 401 reg-io-width = <4>; 402 dmas = <&dmac 2>, <&dmac 3>; 403 #dma-cells = <2>; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 406 status = "disabled"; 407 }; 408 409 uart2: serial@ff160000 { 410 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 411 reg = <0x0 0xff160000 0x0 0x100>; 412 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 414 clock-names = "baudclk", "apb_pclk"; 415 reg-shift = <2>; 416 reg-io-width = <4>; 417 dmas = <&dmac 4>, <&dmac 5>; 418 #dma-cells = <2>; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&uart2m0_xfer>; 421 status = "disabled"; 422 }; 423 424 uart3: serial@ff168000 { 425 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 426 reg = <0x0 0xff168000 0x0 0x100>; 427 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 429 clock-names = "baudclk", "apb_pclk"; 430 reg-shift = <2>; 431 reg-io-width = <4>; 432 dmas = <&dmac 6>, <&dmac 7>; 433 #dma-cells = <2>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 436 status = "disabled"; 437 }; 438 439 uart4: serial@ff170000 { 440 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 441 reg = <0x0 0xff170000 0x0 0x100>; 442 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 444 clock-names = "baudclk", "apb_pclk"; 445 reg-shift = <2>; 446 reg-io-width = <4>; 447 dmas = <&dmac 8>, <&dmac 9>; 448 #dma-cells = <2>; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 451 status = "disabled"; 452 }; 453 454 uart5: serial@ff178000 { 455 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 456 reg = <0x0 0xff178000 0x0 0x100>; 457 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 459 clock-names = "baudclk", "apb_pclk"; 460 reg-shift = <2>; 461 reg-io-width = <4>; 462 dmas = <&dmac 10>, <&dmac 11>; 463 #dma-cells = <2>; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 466 status = "disabled"; 467 }; 468 469 i2c0: i2c@ff180000 { 470 compatible = "rockchip,rk3399-i2c"; 471 reg = <0x0 0xff180000 0x0 0x1000>; 472 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 473 clock-names = "i2c", "pclk"; 474 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&i2c0_xfer>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 i2c1: i2c@ff190000 { 483 compatible = "rockchip,rk3399-i2c"; 484 reg = <0x0 0xff190000 0x0 0x1000>; 485 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 486 clock-names = "i2c", "pclk"; 487 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&i2c1_xfer>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 status = "disabled"; 493 }; 494 495 i2c2: i2c@ff1a0000 { 496 compatible = "rockchip,rk3399-i2c"; 497 reg = <0x0 0xff1a0000 0x0 0x1000>; 498 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 499 clock-names = "i2c", "pclk"; 500 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&i2c2_xfer>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 }; 507 508 i2c3: i2c@ff1b0000 { 509 compatible = "rockchip,rk3399-i2c"; 510 reg = <0x0 0xff1b0000 0x0 0x1000>; 511 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 512 clock-names = "i2c", "pclk"; 513 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&i2c3_xfer>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 status = "disabled"; 519 }; 520 521 spi0: spi@ff1d0000 { 522 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 523 reg = <0x0 0xff1d0000 0x0 0x1000>; 524 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 528 clock-names = "spiclk", "apb_pclk"; 529 dmas = <&dmac 12>, <&dmac 13>; 530 #dma-cells = <2>; 531 dma-names = "tx", "rx"; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 534 status = "disabled"; 535 }; 536 537 spi1: spi@ff1d8000 { 538 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 539 reg = <0x0 0xff1d8000 0x0 0x1000>; 540 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 544 clock-names = "spiclk", "apb_pclk"; 545 dmas = <&dmac 14>, <&dmac 15>; 546 #dma-cells = <2>; 547 dma-names = "tx", "rx"; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 550 status = "disabled"; 551 }; 552 553 wdt: watchdog@ff1e0000 { 554 compatible = "snps,dw-wdt"; 555 reg = <0x0 0xff1e0000 0x0 0x100>; 556 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 557 status = "disabled"; 558 }; 559 560 pwm0: pwm@ff200000 { 561 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 562 reg = <0x0 0xff200000 0x0 0x10>; 563 #pwm-cells = <3>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&pwm0_pin>; 566 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 567 clock-names = "pwm", "pclk"; 568 status = "disabled"; 569 }; 570 571 pwm1: pwm@ff200010 { 572 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 573 reg = <0x0 0xff200010 0x0 0x10>; 574 #pwm-cells = <3>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&pwm1_pin>; 577 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 578 clock-names = "pwm", "pclk"; 579 status = "disabled"; 580 }; 581 582 pwm2: pwm@ff200020 { 583 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 584 reg = <0x0 0xff200020 0x0 0x10>; 585 #pwm-cells = <3>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pwm2_pin>; 588 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 589 clock-names = "pwm", "pclk"; 590 status = "disabled"; 591 }; 592 593 pwm3: pwm@ff200030 { 594 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 595 reg = <0x0 0xff200030 0x0 0x10>; 596 #pwm-cells = <3>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&pwm3_pin>; 599 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 600 clock-names = "pwm", "pclk"; 601 status = "disabled"; 602 }; 603 604 pwm4: pwm@ff208000 { 605 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 606 reg = <0x0 0xff208000 0x0 0x10>; 607 #pwm-cells = <3>; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&pwm4_pin>; 610 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 611 clock-names = "pwm", "pclk"; 612 status = "disabled"; 613 }; 614 615 pwm5: pwm@ff208010 { 616 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 617 reg = <0x0 0xff208010 0x0 0x10>; 618 #pwm-cells = <3>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pwm5_pin>; 621 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 622 clock-names = "pwm", "pclk"; 623 status = "disabled"; 624 }; 625 626 pwm6: pwm@ff208020 { 627 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 628 reg = <0x0 0xff208020 0x0 0x10>; 629 #pwm-cells = <3>; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pwm6_pin>; 632 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 633 clock-names = "pwm", "pclk"; 634 status = "disabled"; 635 }; 636 637 pwm7: pwm@ff208030 { 638 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 639 reg = <0x0 0xff208030 0x0 0x10>; 640 #pwm-cells = <3>; 641 pinctrl-names = "default"; 642 pinctrl-0 = <&pwm7_pin>; 643 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 644 clock-names = "pwm", "pclk"; 645 status = "disabled"; 646 }; 647 648 amba { 649 compatible = "simple-bus"; 650 #address-cells = <2>; 651 #size-cells = <2>; 652 ranges; 653 654 dmac: dmac@ff240000 { 655 compatible = "arm,pl330", "arm,primecell"; 656 reg = <0x0 0xff240000 0x0 0x4000>; 657 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&cru ACLK_DMAC>; 660 clock-names = "apb_pclk"; 661 #dma-cells = <1>; 662 peripherals-req-type-burst; 663 }; 664 }; 665 666 tsadc: tsadc@ff280000 { 667 compatible = "rockchip,px30-tsadc"; 668 reg = <0x0 0xff280000 0x0 0x100>; 669 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 670 rockchip,grf = <&grf>; 671 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 672 clock-names = "tsadc", "apb_pclk"; 673 assigned-clocks = <&cru SCLK_TSADC>; 674 assigned-clock-rates = <50000>; 675 resets = <&cru SRST_TSADC_P>; 676 reset-names = "tsadc-apb"; 677 pinctrl-names = "init", "default", "sleep"; 678 pinctrl-0 = <&tsadc_otp_gpio>; 679 pinctrl-1 = <&tsadc_otp_out>; 680 pinctrl-2 = <&tsadc_otp_gpio>; 681 #thermal-sensor-cells = <1>; 682 rockchip,hw-tshut-temp = <100000>; 683 status = "disabled"; 684 }; 685 686 saradc: saradc@ff288000 { 687 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 688 reg = <0x0 0xff288000 0x0 0x100>; 689 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 690 #io-channel-cells = <1>; 691 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 692 clock-names = "saradc", "apb_pclk"; 693 resets = <&cru SRST_SARADC_P>; 694 reset-names = "saradc-apb"; 695 status = "disabled"; 696 }; 697 698 cru: clock-controller@ff2b0000 { 699 compatible = "rockchip,px30-cru"; 700 reg = <0x0 0xff2b0000 0x0 0x9000>; 701 rockchip,grf = <&grf>; 702 #clock-cells = <1>; 703 #reset-cells = <1>; 704 705 assigned-clocks = 706 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 707 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 708 <&cru ARMCLK>; 709 assigned-clock-rates = 710 <1608000000>, <1416000000>, 711 <1188000000>, <1188000000>, 712 <816000000>; 713 }; 714 715 pmucru: pmu-clock-controller@ff2bc000 { 716 compatible = "rockchip,px30-pmucru"; 717 reg = <0x0 0xff2bc000 0x0 0x1000>; 718 rockchip,grf = <&grf>; 719 #clock-cells = <1>; 720 #reset-cells = <1>; 721 722 assigned-clocks = 723 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 724 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 725 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 726 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 727 assigned-clock-rates = 728 <1200000000>, <100000000>, 729 <26000000>, <300000000>, 730 <300000000>, <150000000>, 731 <150000000>, <75000000>; 732 }; 733 734 usb2phy_grf: syscon@ff2c0000 { 735 compatible = "rockchip,px30-usb2phy-grf", "syscon", 736 "simple-mfd"; 737 reg = <0x0 0xff2c0000 0x0 0x10000>; 738 #address-cells = <1>; 739 #size-cells = <1>; 740 741 u2phy: usb2-phy@100 { 742 compatible = "rockchip,px30-usb2phy", 743 "rockchip,rk3328-usb2phy"; 744 reg = <0x100 0x10>; 745 clocks = <&pmucru SCLK_USBPHY_REF>; 746 clock-names = "phyclk"; 747 #clock-cells = <0>; 748 assigned-clocks = <&cru USB480M>; 749 assigned-clock-parents = <&u2phy>; 750 clock-output-names = "usb480m_phy"; 751 status = "disabled"; 752 753 u2phy_host: host-port { 754 #phy-cells = <0>; 755 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 756 interrupt-names = "linestate"; 757 status = "disabled"; 758 }; 759 760 u2phy_otg: otg-port { 761 #phy-cells = <0>; 762 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-names = "otg-bvalid", "otg-id", 766 "linestate"; 767 status = "disabled"; 768 }; 769 }; 770 }; 771 772 video_phy: video-phy@ff2e0000 { 773 compatible = "rockchip,px30-video-phy"; 774 reg = <0x0 0xff2e0000 0x0 0x10000>, 775 <0x0 0xff450000 0x0 0x10000>; 776 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, 777 <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 778 clock-names = "ref", "pclk_phy", "pclk_host"; 779 #clock-cells = <0>; 780 resets = <&cru SRST_MIPIDSIPHY_P>; 781 reset-names = "rst"; 782 power-domains = <&power PX30_PD_VO>; 783 #phy-cells = <0>; 784 status = "disabled"; 785 }; 786 787 usb20_otg: usb@ff300000 { 788 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 789 "snps,dwc2"; 790 reg = <0x0 0xff300000 0x0 0x40000>; 791 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cru HCLK_OTG>; 793 clock-names = "otg"; 794 dr_mode = "otg"; 795 g-np-tx-fifo-size = <16>; 796 g-rx-fifo-size = <275>; 797 g-tx-fifo-size = <256 128 128 64 64 32>; 798 g-use-dma; 799 phys = <&u2phy_otg>; 800 phy-names = "usb2-phy"; 801 status = "disabled"; 802 }; 803 804 usb_host0_ehci: usb@ff340000 { 805 compatible = "generic-ehci"; 806 reg = <0x0 0xff340000 0x0 0x10000>; 807 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 809 <&u2phy>; 810 clock-names = "usbhost", "arbiter", "utmi"; 811 phys = <&u2phy_host>; 812 phy-names = "usb"; 813 status = "disabled"; 814 }; 815 816 usb_host0_ohci: usb@ff350000 { 817 compatible = "generic-ohci"; 818 reg = <0x0 0xff350000 0x0 0x10000>; 819 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 821 <&u2phy>; 822 clock-names = "usbhost", "arbiter", "utmi"; 823 phys = <&u2phy_host>; 824 phy-names = "usb"; 825 }; 826 827 gmac: ethernet@ff360000 { 828 compatible = "rockchip,px30-gmac"; 829 reg = <0x0 0xff360000 0x0 0x10000>; 830 rockchip,grf = <&grf>; 831 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "macirq"; 833 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 834 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 835 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 836 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 837 clock-names = "stmmaceth", "mac_clk_rx", 838 "mac_clk_tx", "clk_mac_ref", 839 "clk_mac_refout", "aclk_mac", 840 "pclk_mac", "clk_mac_speed"; 841 phy-mode = "rmii"; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 844 resets = <&cru SRST_GMAC_A>; 845 reset-names = "stmmaceth"; 846 power-domains = <&power PX30_PD_GMAC>; 847 status = "disabled"; 848 }; 849 850 sdmmc: dwmmc@ff370000 { 851 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 852 reg = <0x0 0xff370000 0x0 0x4000>; 853 max-frequency = <150000000>; 854 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 855 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 856 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 857 fifo-depth = <0x100>; 858 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 859 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 862 status = "disabled"; 863 }; 864 865 sdio: dwmmc@ff380000 { 866 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 867 reg = <0x0 0xff380000 0x0 0x4000>; 868 max-frequency = <150000000>; 869 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 870 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 871 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 872 fifo-depth = <0x100>; 873 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 874 status = "disabled"; 875 }; 876 877 emmc: dwmmc@ff390000 { 878 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 879 reg = <0x0 0xff390000 0x0 0x4000>; 880 max-frequency = <150000000>; 881 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 882 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 883 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 884 fifo-depth = <0x100>; 885 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 886 status = "disabled"; 887 }; 888 889 sfc: sfc@ff3a0000 { 890 compatible = "rockchip,rksfc","rockchip,sfc"; 891 reg = <0x0 0xff3a0000 0x0 0x4000>; 892 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 894 clock-names = "clk_sfc", "hclk_sfc"; 895 status = "disabled"; 896 }; 897 898 nandc0: nandc@ff3b0000 { 899 compatible = "rockchip,rk-nandc"; 900 reg = <0x0 0xff3b0000 0x0 0x4000>; 901 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 902 nandc_id = <0>; 903 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 904 clock-names = "clk_nandc", "hclk_nandc"; 905 status = "disabled"; 906 }; 907 908 gpu: gpu@ff400000 { 909 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 910 reg = <0x0 0xff400000 0x0 0x4000>; 911 912 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "GPU", "MMU", "JOB"; 916 917 clocks = <&cru ACLK_GPU>; 918 clock-names = "clk_mali"; 919 920 status = "disabled"; 921 }; 922 923 hevc: hevc_service@ff440000 { 924 compatible = "rockchip,hevc_sub"; 925 iommu_enabled = <1>; 926 reg = <0x0 0xff440000 0x0 0x400>; 927 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 928 interrupt-names = "irq_dec"; 929 dev_mode = <1>; 930 iommus = <&hevc_mmu>; 931 name = "hevc_service"; 932 allocator = <1>; 933 }; 934 935 vpu: vpu_service@ff442000 { 936 compatible = "rockchip,vpu_sub"; 937 iommu_enabled = <1>; 938 reg = <0x0 0xff442000 0x0 0x800>; 939 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-names = "irq_enc", "irq_dec"; 942 dev_mode = <0>; 943 iommus = <&vpu_mmu>; 944 name = "vpu_service"; 945 allocator = <1>; 946 }; 947 948 vpu_combo: vpu_combo { 949 compatible = "rockchip,vpu_combo"; 950 subcnt = <2>; 951 rockchip,grf = <&grf>; 952 rockchip,sub = <&vpu>, <&hevc>; 953 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 954 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 955 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 956 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 957 <&cru SRST_VPU_CORE>; 958 reset-names = "video_a", "video_h", "niu_a", "niu_h", 959 "video_core"; 960 mode_bit = <15>; 961 mode_ctrl = <0x410>; 962 name = "vpu_combo"; 963 status = "disabled"; 964 }; 965 966 hevc_mmu: iommu@ff440440 { 967 compatible = "rockchip,iommu"; 968 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 969 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 970 interrupt-names = "hevc_mmu"; 971 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 972 clock-names = "aclk", "hclk"; 973 #iommu-cells = <0>; 974 }; 975 976 vpu_mmu: iommu@ff442800 { 977 compatible = "rockchip,iommu"; 978 reg = <0x0 0xff442800 0x0 0x100>; 979 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 980 interrupt-names = "vpu_mmu"; 981 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 982 clock-names = "aclk", "hclk"; 983 #iommu-cells = <0>; 984 }; 985 986 dsi: dsi@ff450000 { 987 compatible = "rockchip,px30-mipi-dsi"; 988 reg = <0x0 0xff450000 0x0 0x10000>; 989 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&cru PCLK_MIPI_DSI>, <&video_phy>; 991 clock-names = "pclk", "hs_clk"; 992 resets = <&cru SRST_MIPIDSI_HOST_P>; 993 reset-names = "apb"; 994 phys = <&video_phy>; 995 phy-names = "mipi_dphy"; 996 power-domains = <&power PX30_PD_VO>; 997 rockchip,grf = <&grf>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 1002 ports { 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 1006 port@0 { 1007 reg = <0>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 1011 dsi_in_vopl: endpoint@0 { 1012 reg = <0>; 1013 remote-endpoint = <&vopl_out_dsi>; 1014 }; 1015 1016 dsi_in_vopb: endpoint@1 { 1017 reg = <1>; 1018 remote-endpoint = <&vopb_out_dsi>; 1019 }; 1020 }; 1021 }; 1022 }; 1023 1024 vopb: vop@ff460000 { 1025 compatible = "rockchip,px30-vop-big"; 1026 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 1027 reg-names = "regs", "gamma_lut"; 1028 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1030 <&cru HCLK_VOPB>; 1031 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1032 iommus = <&vopb_mmu>; 1033 status = "disabled"; 1034 1035 vopb_out: port { 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 1039 vopb_out_lvds: endpoint@0 { 1040 reg = <0>; 1041 remote-endpoint = <&lvds_in_vopb>; 1042 }; 1043 1044 vopb_out_dsi: endpoint@1 { 1045 reg = <1>; 1046 remote-endpoint = <&dsi_in_vopb>; 1047 }; 1048 1049 vopb_out_rgb: endpoint@2 { 1050 reg = <2>; 1051 remote-endpoint = <&rgb_in_vopb>; 1052 }; 1053 }; 1054 }; 1055 1056 vopb_mmu: iommu@ff460f00 { 1057 compatible = "rockchip,iommu"; 1058 reg = <0x0 0xff460f00 0x0 0x100>; 1059 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1060 interrupt-names = "vopb_mmu"; 1061 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1062 clock-names = "aclk", "hclk"; 1063 #iommu-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 vopl: vop@ff470000 { 1068 compatible = "rockchip,px30-vop-lit"; 1069 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 1070 reg-names = "regs", "gamma_lut"; 1071 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1073 <&cru HCLK_VOPL>; 1074 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1075 iommus = <&vopl_mmu>; 1076 status = "disabled"; 1077 1078 vopl_out: port { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 vopl_out_lvds: endpoint@0 { 1083 reg = <0>; 1084 remote-endpoint = <&lvds_in_vopl>; 1085 }; 1086 1087 vopl_out_dsi: endpoint@1 { 1088 reg = <1>; 1089 remote-endpoint = <&dsi_in_vopl>; 1090 }; 1091 1092 vopl_out_rgb: endpoint@2 { 1093 reg = <2>; 1094 remote-endpoint = <&rgb_in_vopl>; 1095 }; 1096 }; 1097 }; 1098 1099 vopl_mmu: iommu@ff470f00 { 1100 compatible = "rockchip,iommu"; 1101 reg = <0x0 0xff470f00 0x0 0x100>; 1102 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1103 interrupt-names = "vopl_mmu"; 1104 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1105 clock-names = "aclk", "hclk"; 1106 #iommu-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 rk_rga: rk_rga@ff480000 { 1111 compatible = "rockchip,rga2"; 1112 //dev_mode = <1>; 1113 reg = <0x0 0xff480000 0x0 0x1000>; 1114 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1116 clock-names = "aclk_rga", "hclk_rga"; 1117 dma-coherent; 1118 status = "disabled"; 1119 }; 1120 1121 cif: cif@ff490000 { 1122 compatible = "rockchip,cif"; 1123 reg = <0x0 0xff490000 0x0 0x200>; 1124 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1126 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1127 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1128 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1129 pinctrl-names = "cif_pin_all"; 1130 pinctrl-0 = <&dvp_d2d9_m0>; 1131 status = "disabled"; 1132 }; 1133 1134 vip_mmu: iommu@ff490800{ 1135 compatible = "rockchip,iommu"; 1136 reg = <0x0 0xff490800 0x0 0x100>; 1137 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1138 interrupt-names = "vip_mmu"; 1139 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1140 clock-names = "aclk", "hclk"; 1141 rk_iommu,disable_reset_quirk; 1142 #iommu-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 1146 rk_isp: rk_isp@ff4a0000 { 1147 compatible = "rockchip,px30-isp", "rockchip,isp"; 1148 reg = <0x0 0xff4a0000 0x0 0x4000>; 1149 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1151 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1152 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1153 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1154 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1155 reset-names = "rst_isp", "rst_mipicsiphy"; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&cif_clkout_m0>; 1158 rockchip,isp,mipiphy = <0>; 1159 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1160 rockchip,grf = <&grf>; 1161 rockchip,cru = <&cru>; 1162 rockchip,isp,iommu-enable = <1>; 1163 iommus = <&isp_mmu>; 1164 status = "disabled"; 1165 }; 1166 1167 isp_mmu: iommu@ff4a8000 { 1168 compatible = "rockchip,iommu"; 1169 reg = <0x0 0xff4a8000 0x0 0x100>; 1170 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "isp_mmu"; 1172 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1173 clock-names = "aclk", "hclk"; 1174 rk_iommu,disable_reset_quirk; 1175 #iommu-cells = <0>; 1176 status = "disabled"; 1177 }; 1178 1179 qos_gmac: qos@ff518000 { 1180 compatible = "syscon"; 1181 reg = <0x0 0xff518000 0x0 0x20>; 1182 }; 1183 1184 qos_gpu: qos@ff520000 { 1185 compatible = "syscon"; 1186 reg = <0x0 0xff520000 0x0 0x20>; 1187 }; 1188 1189 qos_sdmmc: qos@ff52c000 { 1190 compatible = "syscon"; 1191 reg = <0x0 0xff52c000 0x0 0x20>; 1192 }; 1193 1194 qos_emmc: qos@ff538000 { 1195 compatible = "syscon"; 1196 reg = <0x0 0xff538000 0x0 0x20>; 1197 }; 1198 1199 qos_nand: qos@ff538080 { 1200 compatible = "syscon"; 1201 reg = <0x0 0xff538080 0x0 0x20>; 1202 }; 1203 1204 qos_sdio: qos@ff538100 { 1205 compatible = "syscon"; 1206 reg = <0x0 0xff538100 0x0 0x20>; 1207 }; 1208 1209 qos_sfc: qos@ff538180 { 1210 compatible = "syscon"; 1211 reg = <0x0 0xff538180 0x0 0x20>; 1212 }; 1213 1214 qos_usb_host: qos@ff540000 { 1215 compatible = "syscon"; 1216 reg = <0x0 0xff540000 0x0 0x20>; 1217 }; 1218 1219 qos_usb_otg: qos@ff540080 { 1220 compatible = "syscon"; 1221 reg = <0x0 0xff540080 0x0 0x20>; 1222 }; 1223 1224 qos_isp_128: qos@ff548000 { 1225 compatible = "syscon"; 1226 reg = <0x0 0xff548000 0x0 0x20>; 1227 }; 1228 1229 qos_isp_rd: qos@ff548080 { 1230 compatible = "syscon"; 1231 reg = <0x0 0xff548080 0x0 0x20>; 1232 }; 1233 1234 qos_isp_wr: qos@ff548100 { 1235 compatible = "syscon"; 1236 reg = <0x0 0xff548100 0x0 0x20>; 1237 }; 1238 1239 qos_isp_m1: qos@ff548180 { 1240 compatible = "syscon"; 1241 reg = <0x0 0xff548180 0x0 0x20>; 1242 }; 1243 1244 qos_vip: qos@ff548200 { 1245 compatible = "syscon"; 1246 reg = <0x0 0xff548200 0x0 0x20>; 1247 }; 1248 1249 qos_rga_rd: qos@ff550000 { 1250 compatible = "syscon"; 1251 reg = <0x0 0xff550000 0x0 0x20>; 1252 }; 1253 1254 qos_rga_wr: qos@ff550080 { 1255 compatible = "syscon"; 1256 reg = <0x0 0xff550080 0x0 0x20>; 1257 }; 1258 1259 qos_vop_m0: qos@ff550100 { 1260 compatible = "syscon"; 1261 reg = <0x0 0xff550100 0x0 0x20>; 1262 }; 1263 1264 qos_vop_m1: qos@ff550180 { 1265 compatible = "syscon"; 1266 reg = <0x0 0xff550180 0x0 0x20>; 1267 }; 1268 1269 qos_vpu: qos@ff558000 { 1270 compatible = "syscon"; 1271 reg = <0x0 0xff558000 0x0 0x20>; 1272 }; 1273 1274 qos_vpu_r128: qos@ff558080 { 1275 compatible = "syscon"; 1276 reg = <0x0 0xff558080 0x0 0x20>; 1277 }; 1278 1279 pinctrl: pinctrl { 1280 compatible = "rockchip,px30-pinctrl"; 1281 rockchip,grf = <&grf>; 1282 rockchip,pmu = <&pmugrf>; 1283 #address-cells = <2>; 1284 #size-cells = <2>; 1285 ranges; 1286 1287 gpio0: gpio0@ff040000 { 1288 compatible = "rockchip,gpio-bank"; 1289 reg = <0x0 0xff040000 0x0 0x100>; 1290 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1291 clocks = <&cru PCLK_GPIO0_PMU>; 1292 gpio-controller; 1293 #gpio-cells = <2>; 1294 1295 interrupt-controller; 1296 #interrupt-cells = <2>; 1297 }; 1298 1299 gpio1: gpio1@ff250000 { 1300 compatible = "rockchip,gpio-bank"; 1301 reg = <0x0 0xff250000 0x0 0x100>; 1302 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&cru PCLK_GPIO1>; 1304 gpio-controller; 1305 #gpio-cells = <2>; 1306 1307 interrupt-controller; 1308 #interrupt-cells = <2>; 1309 }; 1310 1311 gpio2: gpio2@ff260000 { 1312 compatible = "rockchip,gpio-bank"; 1313 reg = <0x0 0xff260000 0x0 0x100>; 1314 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1315 clocks = <&cru PCLK_GPIO2>; 1316 gpio-controller; 1317 #gpio-cells = <2>; 1318 1319 interrupt-controller; 1320 #interrupt-cells = <2>; 1321 }; 1322 1323 gpio3: gpio3@ff270000 { 1324 compatible = "rockchip,gpio-bank"; 1325 reg = <0x0 0xff270000 0x0 0x100>; 1326 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1327 clocks = <&cru PCLK_GPIO3>; 1328 gpio-controller; 1329 #gpio-cells = <2>; 1330 1331 interrupt-controller; 1332 #interrupt-cells = <2>; 1333 }; 1334 1335 pcfg_pull_up: pcfg-pull-up { 1336 bias-pull-up; 1337 }; 1338 1339 pcfg_pull_down: pcfg-pull-down { 1340 bias-pull-down; 1341 }; 1342 1343 pcfg_pull_none: pcfg-pull-none { 1344 bias-disable; 1345 }; 1346 1347 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1348 bias-disable; 1349 drive-strength = <2>; 1350 }; 1351 1352 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1353 bias-pull-up; 1354 drive-strength = <2>; 1355 }; 1356 1357 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1358 bias-pull-up; 1359 drive-strength = <4>; 1360 }; 1361 1362 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1363 bias-disable; 1364 drive-strength = <4>; 1365 }; 1366 1367 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1368 bias-pull-down; 1369 drive-strength = <4>; 1370 }; 1371 1372 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1373 bias-disable; 1374 drive-strength = <8>; 1375 }; 1376 1377 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1378 bias-pull-up; 1379 drive-strength = <8>; 1380 }; 1381 1382 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1383 bias-disable; 1384 drive-strength = <12>; 1385 }; 1386 1387 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1388 bias-pull-up; 1389 drive-strength = <12>; 1390 }; 1391 1392 pcfg_pull_none_smt: pcfg-pull-none-smt { 1393 bias-disable; 1394 input-schmitt-enable; 1395 }; 1396 1397 pcfg_output_high: pcfg-output-high { 1398 output-high; 1399 }; 1400 1401 pcfg_output_low: pcfg-output-low { 1402 output-low; 1403 }; 1404 1405 pcfg_input_high: pcfg-input-high { 1406 bias-pull-up; 1407 input-enable; 1408 }; 1409 1410 pcfg_input: pcfg-input { 1411 input-enable; 1412 }; 1413 1414 i2c0 { 1415 i2c0_xfer: i2c0-xfer { 1416 rockchip,pins = 1417 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1418 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1419 }; 1420 }; 1421 1422 i2c1 { 1423 i2c1_xfer: i2c1-xfer { 1424 rockchip,pins = 1425 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1426 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1427 }; 1428 }; 1429 1430 i2c2 { 1431 i2c2_xfer: i2c2-xfer { 1432 rockchip,pins = 1433 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1434 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1435 }; 1436 }; 1437 1438 i2c3 { 1439 i2c3_xfer: i2c3-xfer { 1440 rockchip,pins = 1441 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1442 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1443 }; 1444 }; 1445 1446 tsadc { 1447 tsadc_otp_gpio: tsadc-otp-gpio { 1448 rockchip,pins = 1449 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1450 }; 1451 1452 tsadc_otp_out: tsadc-otp-out { 1453 rockchip,pins = 1454 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1455 }; 1456 }; 1457 1458 uart0 { 1459 uart0_xfer: uart0-xfer { 1460 rockchip,pins = 1461 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1462 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1463 }; 1464 1465 uart0_cts: uart0-cts { 1466 rockchip,pins = 1467 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1468 }; 1469 1470 uart0_rts: uart0-rts { 1471 rockchip,pins = 1472 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1473 }; 1474 1475 uart0_rts_gpio: uart0-rts-gpio { 1476 rockchip,pins = 1477 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1478 }; 1479 }; 1480 1481 uart1 { 1482 uart1_xfer: uart1-xfer { 1483 rockchip,pins = 1484 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1485 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1486 }; 1487 1488 uart1_cts: uart1-cts { 1489 rockchip,pins = 1490 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1491 }; 1492 1493 uart1_rts: uart1-rts { 1494 rockchip,pins = 1495 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1496 }; 1497 1498 uart1_rts_gpio: uart1-rts-gpio { 1499 rockchip,pins = 1500 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1501 }; 1502 }; 1503 1504 uart2-m0 { 1505 uart2m0_xfer: uart2m0-xfer { 1506 rockchip,pins = 1507 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1508 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1509 }; 1510 }; 1511 1512 uart2-m1 { 1513 uart2m1_xfer: uart2m1-xfer { 1514 rockchip,pins = 1515 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1516 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1517 }; 1518 }; 1519 1520 uart3-m0 { 1521 uart3m0_xfer: uart3m0-xfer { 1522 rockchip,pins = 1523 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1524 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1525 }; 1526 1527 uart3m0_cts: uart3m0-cts { 1528 rockchip,pins = 1529 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1530 }; 1531 1532 uart3m0_rts: uart3m0-rts { 1533 rockchip,pins = 1534 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1535 }; 1536 1537 uart3m0_rts_gpio: uart3m0-rts-gpio { 1538 rockchip,pins = 1539 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1540 }; 1541 }; 1542 1543 uart3-m1 { 1544 uart3m1_xfer: uart3m1-xfer { 1545 rockchip,pins = 1546 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1547 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1548 }; 1549 1550 uart3m1_cts: uart3m1-cts { 1551 rockchip,pins = 1552 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1553 }; 1554 1555 uart3m1_rts: uart3m1-rts { 1556 rockchip,pins = 1557 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1558 }; 1559 1560 uart3m1_rts_gpio: uart3m1-rts-gpio { 1561 rockchip,pins = 1562 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1563 }; 1564 }; 1565 1566 uart4 { 1567 1568 uart4_xfer: uart4-xfer { 1569 rockchip,pins = 1570 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1571 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1572 }; 1573 1574 uart4_cts: uart4-cts { 1575 rockchip,pins = 1576 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1577 1578 }; 1579 1580 uart4_rts: uart4-rts { 1581 rockchip,pins = 1582 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1583 }; 1584 }; 1585 1586 uart5 { 1587 1588 uart5_xfer: uart5-xfer { 1589 rockchip,pins = 1590 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1591 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1592 }; 1593 1594 uart5_cts: uart5-cts { 1595 rockchip,pins = 1596 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1597 1598 }; 1599 1600 uart5_rts: uart5-rts { 1601 rockchip,pins = 1602 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1603 }; 1604 }; 1605 1606 spi0 { 1607 spi0_clk: spi0-clk { 1608 rockchip,pins = 1609 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1610 }; 1611 1612 spi0_csn: spi0-csn { 1613 rockchip,pins = 1614 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1615 }; 1616 1617 spi0_miso: spi0-miso { 1618 rockchip,pins = 1619 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1620 }; 1621 1622 spi0_mosi: spi0-mosi { 1623 rockchip,pins = 1624 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1625 }; 1626 }; 1627 1628 spi1 { 1629 spi1_clk: spi1-clk { 1630 rockchip,pins = 1631 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1632 }; 1633 1634 spi1_csn: spi1-csn { 1635 rockchip,pins = 1636 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1637 }; 1638 1639 spi1_miso: spi1-miso { 1640 rockchip,pins = 1641 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1642 }; 1643 1644 spi1_mosi: spi1-mosi { 1645 rockchip,pins = 1646 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1647 }; 1648 }; 1649 1650 pdm { 1651 pdm_clk0m0: pdm-clk0m0 { 1652 rockchip,pins = 1653 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1654 }; 1655 1656 pdm_clk0m1: pdm-clk0m1 { 1657 rockchip,pins = 1658 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1659 }; 1660 1661 pdm_clk1: pdm-clk1 { 1662 rockchip,pins = 1663 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1664 }; 1665 1666 pdm_sdi0m0: pdm-sdi0m0 { 1667 rockchip,pins = 1668 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1669 }; 1670 1671 pdm_sdi0m1: pdm-sdi0m1 { 1672 rockchip,pins = 1673 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1674 }; 1675 1676 pdm_sdi1: pdm-sdi1 { 1677 rockchip,pins = 1678 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1679 }; 1680 1681 pdm_sdi2: pdm-sdi2 { 1682 rockchip,pins = 1683 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1684 }; 1685 1686 pdm_sdi3: pdm-sdi3 { 1687 rockchip,pins = 1688 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1689 }; 1690 1691 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1692 rockchip,pins = 1693 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1694 }; 1695 1696 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1697 rockchip,pins = 1698 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1699 }; 1700 1701 pdm_clk1_sleep: pdm-clk1-sleep { 1702 rockchip,pins = 1703 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1704 }; 1705 1706 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1707 rockchip,pins = 1708 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1709 }; 1710 1711 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1712 rockchip,pins = 1713 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1714 }; 1715 1716 pdm_sdi1_sleep: pdm-sdi1-sleep { 1717 rockchip,pins = 1718 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1719 }; 1720 1721 pdm_sdi2_sleep: pdm-sdi2-sleep { 1722 rockchip,pins = 1723 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1724 }; 1725 1726 pdm_sdi3_sleep: pdm-sdi3-sleep { 1727 rockchip,pins = 1728 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1729 }; 1730 }; 1731 1732 i2s0 { 1733 i2s0_8ch_mclk: i2s0-8ch-mclk { 1734 rockchip,pins = 1735 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1736 }; 1737 1738 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1739 rockchip,pins = 1740 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1741 }; 1742 1743 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1744 rockchip,pins = 1745 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1746 }; 1747 1748 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1749 rockchip,pins = 1750 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1751 }; 1752 1753 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1754 rockchip,pins = 1755 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1756 }; 1757 1758 i2s0_8ch_sdo: i2s0-8ch-sdo { 1759 rockchip,pins = 1760 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1761 }; 1762 1763 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1764 rockchip,pins = 1765 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1766 }; 1767 1768 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1769 rockchip,pins = 1770 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1771 }; 1772 1773 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1774 rockchip,pins = 1775 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1776 }; 1777 1778 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1779 rockchip,pins = 1780 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1781 }; 1782 1783 i2s0_8ch_sdi: i2s0-8ch-sdi { 1784 rockchip,pins = 1785 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1786 }; 1787 1788 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1789 rockchip,pins = 1790 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1791 }; 1792 1793 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1794 rockchip,pins = 1795 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1796 }; 1797 1798 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1799 rockchip,pins = 1800 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1801 }; 1802 1803 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1804 rockchip,pins = 1805 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1806 }; 1807 }; 1808 1809 i2s1 { 1810 i2s1_2ch_mclk: i2s1-2ch-mclk { 1811 rockchip,pins = 1812 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1813 }; 1814 1815 i2s1_2ch_sclk: i2s1-2ch-sclk { 1816 rockchip,pins = 1817 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1818 }; 1819 1820 i2s1_2ch_lrck: i2s1-2ch-lrck { 1821 rockchip,pins = 1822 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1823 }; 1824 1825 i2s1_2ch_sdi: i2s1-2ch-sdi { 1826 rockchip,pins = 1827 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1828 }; 1829 1830 i2s1_2ch_sdo: i2s1-2ch-sdo { 1831 rockchip,pins = 1832 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1833 }; 1834 }; 1835 1836 i2s2 { 1837 i2s2_2ch_mclk: i2s2-2ch-mclk { 1838 rockchip,pins = 1839 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1840 }; 1841 1842 i2s2_2ch_sclk: i2s2-2ch-sclk { 1843 rockchip,pins = 1844 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1845 }; 1846 1847 i2s2_2ch_lrck: i2s2-2ch-lrck { 1848 rockchip,pins = 1849 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1850 }; 1851 1852 i2s2_2ch_sdi: i2s2-2ch-sdi { 1853 rockchip,pins = 1854 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1855 }; 1856 1857 i2s2_2ch_sdo: i2s2-2ch-sdo { 1858 rockchip,pins = 1859 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1860 }; 1861 }; 1862 1863 sdmmc { 1864 sdmmc_clk: sdmmc-clk { 1865 rockchip,pins = 1866 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_8ma>; 1867 }; 1868 1869 sdmmc_cmd: sdmmc-cmd { 1870 rockchip,pins = 1871 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_8ma>; 1872 }; 1873 1874 sdmmc_det: sdmmc-det { 1875 rockchip,pins = 1876 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>; 1877 }; 1878 1879 sdmmc_bus1: sdmmc-bus1 { 1880 rockchip,pins = 1881 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>; 1882 }; 1883 1884 sdmmc_bus4: sdmmc-bus4 { 1885 rockchip,pins = 1886 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>, 1887 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_8ma>, 1888 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_8ma>, 1889 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_8ma>; 1890 }; 1891 1892 sdmmc_gpio: sdmmc-gpio { 1893 rockchip,pins = 1894 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1895 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1896 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1897 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1898 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1899 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1900 }; 1901 }; 1902 1903 sdio { 1904 sdio_clk: sdio-clk { 1905 rockchip,pins = 1906 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1907 }; 1908 1909 sdio_cmd: sdio-cmd { 1910 rockchip,pins = 1911 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1912 }; 1913 1914 sdio_bus4: sdio-bus4 { 1915 rockchip,pins = 1916 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1917 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>, 1918 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>, 1919 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>; 1920 }; 1921 1922 sdio_gpio: sdio-gpio { 1923 rockchip,pins = 1924 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 1925 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, 1926 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, 1927 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, 1928 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, 1929 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 1930 }; 1931 }; 1932 1933 emmc { 1934 emmc_clk: emmc-clk { 1935 rockchip,pins = 1936 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1937 }; 1938 1939 emmc_cmd: emmc-cmd { 1940 rockchip,pins = 1941 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1942 }; 1943 1944 emmc_pwren: emmc-pwren { 1945 rockchip,pins = 1946 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1947 }; 1948 1949 emmc_rstnout: emmc-rstnout { 1950 rockchip,pins = 1951 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1952 }; 1953 1954 emmc_bus1: emmc-bus1 { 1955 rockchip,pins = 1956 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1957 }; 1958 1959 emmc_bus4: emmc-bus4 { 1960 rockchip,pins = 1961 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1962 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1963 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1964 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1965 }; 1966 1967 emmc_bus8: emmc-bus8 { 1968 rockchip,pins = 1969 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1970 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1971 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1972 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1973 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1974 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1975 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1976 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1977 }; 1978 }; 1979 1980 flash { 1981 flash_cs0: flash-cs0 { 1982 rockchip,pins = 1983 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1984 }; 1985 1986 flash_rdy: flash-rdy { 1987 rockchip,pins = 1988 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1989 }; 1990 1991 flash_dqs: flash-dqs { 1992 rockchip,pins = 1993 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1994 }; 1995 1996 flash_ale: flash-ale { 1997 rockchip,pins = 1998 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1999 }; 2000 2001 flash_cle: flash-cle { 2002 rockchip,pins = 2003 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 2004 }; 2005 2006 flash_wrn: flash-wrn { 2007 rockchip,pins = 2008 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2009 }; 2010 2011 flash_csl: flash-csl { 2012 rockchip,pins = 2013 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2014 }; 2015 2016 flash_rdn: flash-rdn { 2017 rockchip,pins = 2018 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2019 }; 2020 2021 flash_bus8: flash-bus8 { 2022 rockchip,pins = 2023 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 2024 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 2025 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 2026 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 2027 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 2028 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 2029 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 2030 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 2031 }; 2032 }; 2033 2034 lcdc { 2035 lcdc_m0_rgb_pins: lcdc-m0-rgb-pins { 2036 rockchip,pins = 2037 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 2038 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_HSYNC */ 2039 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_VSYNC */ 2040 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DEN */ 2041 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 2042 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D1 */ 2043 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 2044 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D3 */ 2045 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D4 */ 2046 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D5 */ 2047 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 2048 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 2049 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D8 */ 2050 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 2051 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D10 */ 2052 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D11 */ 2053 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 2054 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 2055 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 2056 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 2057 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 2058 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 2059 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 2060 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 2061 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 2062 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 2063 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 2064 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ 2065 }; 2066 2067 lcdc_m0_sleep_pins: lcdc-m0-sleep-pins { 2068 rockchip,pins = 2069 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 2070 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ 2071 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ 2072 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ 2073 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 2074 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D1 */ 2075 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 2076 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D3 */ 2077 <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D4 */ 2078 <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D5 */ 2079 <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 2080 <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 2081 <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D8 */ 2082 <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 2083 <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ 2084 <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ 2085 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 2086 <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 2087 <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 2088 <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 2089 <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 2090 <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 2091 <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 2092 <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 2093 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 2094 <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 2095 <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 2096 <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ 2097 }; 2098 }; 2099 2100 pwm0 { 2101 pwm0_pin: pwm0-pin { 2102 rockchip,pins = 2103 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2104 }; 2105 }; 2106 2107 pwm1 { 2108 pwm1_pin: pwm1-pin { 2109 rockchip,pins = 2110 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2111 }; 2112 }; 2113 2114 pwm2 { 2115 pwm2_pin: pwm2-pin { 2116 rockchip,pins = 2117 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2118 }; 2119 }; 2120 2121 pwm3 { 2122 pwm3_pin: pwm3-pin { 2123 rockchip,pins = 2124 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2125 }; 2126 }; 2127 2128 pwm4 { 2129 pwm4_pin: pwm4-pin { 2130 rockchip,pins = 2131 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2132 }; 2133 }; 2134 2135 pwm5 { 2136 pwm5_pin: pwm5-pin { 2137 rockchip,pins = 2138 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2139 }; 2140 }; 2141 2142 pwm6 { 2143 pwm6_pin: pwm6-pin { 2144 rockchip,pins = 2145 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2146 }; 2147 }; 2148 2149 pwm7 { 2150 pwm7_pin: pwm7-pin { 2151 rockchip,pins = 2152 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2153 }; 2154 }; 2155 2156 gmac { 2157 rmii_pins: rmii-pins { 2158 rockchip,pins = 2159 /* mac_txen */ 2160 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2161 /* mac_txd1 */ 2162 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2163 /* mac_txd0 */ 2164 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2165 /* mac_rxd0 */ 2166 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2167 /* mac_rxd1 */ 2168 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2169 /* mac_rxer */ 2170 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2171 /* mac_rxdv */ 2172 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2173 /* mac_mdio */ 2174 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2175 /* mac_mdc */ 2176 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2177 }; 2178 2179 mac_refclk_12ma: mac-refclk-12ma { 2180 rockchip,pins = 2181 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none_12ma>; 2182 }; 2183 2184 mac_refclk: mac-refclk { 2185 rockchip,pins = 2186 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2187 }; 2188 }; 2189 2190 cif-m0 { 2191 cif_clkout_m0: cif-clkout-m0 { 2192 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2193 }; 2194 2195 dvp_d2d9_m0: dvp-d2d9-m0 { 2196 rockchip,pins = 2197 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2198 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2199 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2200 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2201 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2202 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2203 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2204 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2205 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2206 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2207 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2208 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2209 }; 2210 2211 dvp_d0d1_m0: dvp-d0d1-m0 { 2212 rockchip,pins = 2213 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2214 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2215 }; 2216 2217 dvp_d10d11_m0:d10-d11-m0 { 2218 rockchip,pins = 2219 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2220 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2221 }; 2222 }; 2223 2224 cif-m1 { 2225 cif_clkout_m1: cif-clkout-m1 { 2226 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2227 }; 2228 2229 dvp_d2d9_m1: dvp-d2d9-m1 { 2230 rockchip,pins = 2231 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2232 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2233 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2234 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2235 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2236 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2237 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2238 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2239 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2240 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2241 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2242 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2243 }; 2244 2245 dvp_d0d1_m1: dvp-d0d1-m1 { 2246 rockchip,pins = 2247 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2248 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2249 }; 2250 2251 dvp_d10d11_m1:d10-d11-m1 { 2252 rockchip,pins = 2253 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2254 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2255 }; 2256 }; 2257 2258 isp { 2259 isp_prelight: isp-prelight { 2260 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2261 }; 2262 }; 2263 }; 2264}; 2265