1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 dmc: dmc { 73 compatible = "rockchip,px30-dmc", "syscon"; 74 reg = <0x0 0xff2a0000 0x0 0x1000>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vopb_out>, <&vopl_out>; 80 status = "disabled"; 81 }; 82 83 firmware { 84 optee { 85 compatible = "linaro,optee-tz"; 86 method = "smc"; 87 }; 88 }; 89 90 gmac_clkin: external-gmac-clock { 91 compatible = "fixed-clock"; 92 clock-frequency = <50000000>; 93 clock-output-names = "gmac_clkin"; 94 #clock-cells = <0>; 95 }; 96 97 psci { 98 compatible = "arm,psci-1.0"; 99 method = "smc"; 100 }; 101 102 timer { 103 compatible = "arm,armv8-timer"; 104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 108 }; 109 110 xin24m: xin24m { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <24000000>; 114 clock-output-names = "xin24m"; 115 }; 116 117 pmu: power-management@ff000000 { 118 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 119 reg = <0x0 0xff000000 0x0 0x1000>; 120 121 power: power-controller { 122 compatible = "rockchip,px30-power-controller"; 123 #power-domain-cells = <1>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* These power domains are grouped by VD_LOGIC */ 129 pd_usb@PX30_PD_USB { 130 reg = <PX30_PD_USB>; 131 clocks = <&cru HCLK_HOST>, 132 <&cru HCLK_OTG>, 133 <&cru SCLK_OTG_ADP>; 134 }; 135 pd_sdcard@PX30_PD_SDCARD { 136 reg = <PX30_PD_SDCARD>; 137 clocks = <&cru HCLK_SDMMC>, 138 <&cru SCLK_SDMMC>; 139 }; 140 pd_gmac@PX30_PD_GMAC { 141 reg = <PX30_PD_GMAC>; 142 clocks = <&cru ACLK_GMAC>, 143 <&cru PCLK_GMAC>, 144 <&cru SCLK_MAC_REF>, 145 <&cru SCLK_GMAC_RX_TX>; 146 }; 147 pd_mmc_nand@PX30_PD_MMC_NAND { 148 reg = <PX30_PD_MMC_NAND>; 149 clocks = <&cru HCLK_NANDC>, 150 <&cru HCLK_EMMC>, 151 <&cru HCLK_SDIO>, 152 <&cru HCLK_SFC>, 153 <&cru SCLK_EMMC>, 154 <&cru SCLK_NANDC>, 155 <&cru SCLK_SDIO>, 156 <&cru SCLK_SFC>; 157 }; 158 pd_vpu@PX30_PD_VPU { 159 reg = <PX30_PD_VPU>; 160 clocks = <&cru ACLK_VPU>, 161 <&cru HCLK_VPU>, 162 <&cru SCLK_CORE_VPU>; 163 }; 164 pd_vo@PX30_PD_VO { 165 reg = <PX30_PD_VO>; 166 clocks = <&cru ACLK_RGA>, 167 <&cru ACLK_VOPB>, 168 <&cru ACLK_VOPL>, 169 <&cru DCLK_VOPB>, 170 <&cru DCLK_VOPL>, 171 <&cru HCLK_RGA>, 172 <&cru HCLK_VOPB>, 173 <&cru HCLK_VOPL>, 174 <&cru PCLK_MIPI_DSI>, 175 <&cru SCLK_RGA_CORE>, 176 <&cru SCLK_VOPB_PWM>; 177 }; 178 pd_vi@PX30_PD_VI { 179 reg = <PX30_PD_VI>; 180 clocks = <&cru ACLK_CIF>, 181 <&cru ACLK_ISP>, 182 <&cru HCLK_CIF>, 183 <&cru HCLK_ISP>, 184 <&cru SCLK_ISP>; 185 }; 186 pd_gpu@PX30_PD_GPU { 187 reg = <PX30_PD_GPU>; 188 clocks = <&cru ACLK_GPU>; 189 }; 190 }; 191 }; 192 193 pmugrf: syscon@ff010000 { 194 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 195 reg = <0x0 0xff010000 0x0 0x1000>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 199 pmu_io_domains: io-domains { 200 compatible = "rockchip,px30-pmu-io-voltage-domain"; 201 status = "disabled"; 202 }; 203 204 reboot-mode { 205 compatible = "syscon-reboot-mode"; 206 offset = <0x200>; 207 mode-bootloader = <BOOT_BL_DOWNLOAD>; 208 mode-charge = <BOOT_CHARGING>; 209 mode-fastboot = <BOOT_FASTBOOT>; 210 mode-loader = <BOOT_BL_DOWNLOAD>; 211 mode-normal = <BOOT_NORMAL>; 212 mode-recovery = <BOOT_RECOVERY>; 213 mode-ums = <BOOT_UMS>; 214 }; 215 216 pmu_pvtm: pmu-pvtm { 217 compatible = "rockchip,px30-pmu-pvtm"; 218 clocks = <&pmucru SCLK_PVTM_PMU>; 219 clock-names = "pmu"; 220 status = "disabled"; 221 }; 222 }; 223 224 uart0: serial@ff030000 { 225 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 226 reg = <0x0 0xff030000 0x0 0x100>; 227 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 229 clock-names = "baudclk", "apb_pclk"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 dmas = <&dmac 0>, <&dmac 1>; 233 #dma-cells = <2>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 236 status = "disabled"; 237 }; 238 239 i2s0_8ch: i2s@ff060000 { 240 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 241 reg = <0x0 0xff060000 0x0 0x1000>; 242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 244 clock-names = "i2s_clk", "i2s_hclk"; 245 dmas = <&dmac 16>, <&dmac 17>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 i2s1_2ch: i2s@ff070000 { 251 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 252 reg = <0x0 0xff070000 0x0 0x1000>; 253 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 255 clock-names = "i2s_clk", "i2s_hclk"; 256 dmas = <&dmac 18>, <&dmac 19>; 257 dma-names = "tx", "rx"; 258 status = "disabled"; 259 }; 260 261 i2s2_2ch: i2s@ff080000 { 262 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 263 reg = <0x0 0xff080000 0x0 0x1000>; 264 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 266 clock-names = "i2s_clk", "i2s_hclk"; 267 dmas = <&dmac 20>, <&dmac 21>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 pdm: pdm@ff0a0000 { 273 compatible = "rockchip,pdm"; 274 reg = <0x0 0xff0a0000 0x0 0x1000>; 275 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 276 clock-names = "pdm_clk", "pdm_hclk"; 277 dmas = <&dmac 24>; 278 dma-names = "rx"; 279 status = "disabled"; 280 }; 281 282 gic: interrupt-controller@ff131000 { 283 compatible = "arm,gic-400"; 284 #interrupt-cells = <3>; 285 #address-cells = <0>; 286 interrupt-controller; 287 reg = <0x0 0xff131000 0 0x1000>, 288 <0x0 0xff132000 0 0x2000>, 289 <0x0 0xff134000 0 0x2000>, 290 <0x0 0xff136000 0 0x2000>; 291 interrupts = <GIC_PPI 9 292 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 293 }; 294 295 grf: syscon@ff140000 { 296 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 297 reg = <0x0 0xff140000 0x0 0x1000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 301 io_domains: io-domains { 302 compatible = "rockchip,px30-io-voltage-domain"; 303 status = "disabled"; 304 }; 305 }; 306 307 core_grf: syscon@ff148000 { 308 compatible = "syscon", "simple-mfd"; 309 reg = <0x0 0xff148000 0x0 0x1000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 313 pvtm: pvtm { 314 compatible = "rockchip,px30-pvtm"; 315 clocks = <&cru SCLK_PVTM>; 316 clock-names = "core"; 317 status = "disabled"; 318 }; 319 }; 320 321 uart1: serial@ff158000 { 322 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 323 reg = <0x0 0xff158000 0x0 0x100>; 324 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 326 clock-names = "sclk_uart", "pclk_uart"; 327 reg-shift = <2>; 328 reg-io-width = <4>; 329 dmas = <&dmac 2>, <&dmac 3>; 330 #dma-cells = <2>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 333 status = "disabled"; 334 }; 335 336 uart2: serial@ff160000 { 337 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 338 reg = <0x0 0xff160000 0x0 0x100>; 339 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 341 clock-names = "baudclk", "apb_pclk"; 342 reg-shift = <2>; 343 reg-io-width = <4>; 344 dmas = <&dmac 4>, <&dmac 5>; 345 #dma-cells = <2>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&uart2m0_xfer>; 348 status = "disabled"; 349 }; 350 351 uart3: serial@ff168000 { 352 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 353 reg = <0x0 0xff168000 0x0 0x100>; 354 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 356 clock-names = "baudclk", "apb_pclk"; 357 reg-shift = <2>; 358 reg-io-width = <4>; 359 dmas = <&dmac 6>, <&dmac 7>; 360 #dma-cells = <2>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 363 status = "disabled"; 364 }; 365 366 uart4: serial@ff170000 { 367 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 368 reg = <0x0 0xff170000 0x0 0x100>; 369 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 371 clock-names = "baudclk", "apb_pclk"; 372 reg-shift = <2>; 373 reg-io-width = <4>; 374 dmas = <&dmac 8>, <&dmac 9>; 375 #dma-cells = <2>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 378 status = "disabled"; 379 }; 380 381 uart5: serial@ff178000 { 382 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 383 reg = <0x0 0xff178000 0x0 0x100>; 384 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 386 clock-names = "baudclk", "apb_pclk"; 387 reg-shift = <2>; 388 reg-io-width = <4>; 389 dmas = <&dmac 10>, <&dmac 11>; 390 #dma-cells = <2>; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 393 status = "disabled"; 394 }; 395 396 i2c0: i2c@ff180000 { 397 compatible = "rockchip,rk3399-i2c"; 398 reg = <0x0 0xff180000 0x0 0x1000>; 399 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 400 clock-names = "i2c", "pclk"; 401 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&i2c0_xfer>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 status = "disabled"; 407 }; 408 409 i2c1: i2c@ff190000 { 410 compatible = "rockchip,rk3399-i2c"; 411 reg = <0x0 0xff190000 0x0 0x1000>; 412 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 413 clock-names = "i2c", "pclk"; 414 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&i2c1_xfer>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 status = "disabled"; 420 }; 421 422 i2c2: i2c@ff1a0000 { 423 compatible = "rockchip,rk3399-i2c"; 424 reg = <0x0 0xff1a0000 0x0 0x1000>; 425 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 426 clock-names = "i2c", "pclk"; 427 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&i2c2_xfer>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 status = "disabled"; 433 }; 434 435 i2c3: i2c@ff1b0000 { 436 compatible = "rockchip,rk3399-i2c"; 437 reg = <0x0 0xff1b0000 0x0 0x1000>; 438 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 439 clock-names = "i2c", "pclk"; 440 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&i2c3_xfer>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 spi0: spi@ff1d0000 { 449 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 450 reg = <0x0 0xff1d0000 0x0 0x1000>; 451 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 455 clock-names = "spiclk", "apb_pclk"; 456 dmas = <&dmac 12>, <&dmac 13>; 457 #dma-cells = <2>; 458 dma-names = "tx", "rx"; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 461 status = "disabled"; 462 }; 463 464 spi1: spi@ff1d8000 { 465 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 466 reg = <0x0 0xff1d8000 0x0 0x1000>; 467 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 471 clock-names = "spiclk", "apb_pclk"; 472 dmas = <&dmac 14>, <&dmac 15>; 473 #dma-cells = <2>; 474 dma-names = "tx", "rx"; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 477 status = "disabled"; 478 }; 479 480 wdt: watchdog@ff1e0000 { 481 compatible = "snps,dw-wdt"; 482 reg = <0x0 0xff1e0000 0x0 0x100>; 483 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 484 status = "disabled"; 485 }; 486 487 pwm0: pwm@ff200000 { 488 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 489 reg = <0x0 0xff200000 0x0 0x10>; 490 #pwm-cells = <3>; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&pwm0_pin>; 493 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 494 clock-names = "pwm", "pclk"; 495 status = "disabled"; 496 }; 497 498 pwm1: pwm@ff200010 { 499 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 500 reg = <0x0 0xff200010 0x0 0x10>; 501 #pwm-cells = <3>; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pwm1_pin>; 504 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 505 clock-names = "pwm", "pclk"; 506 status = "disabled"; 507 }; 508 509 pwm2: pwm@ff200020 { 510 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 511 reg = <0x0 0xff200020 0x0 0x10>; 512 #pwm-cells = <3>; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&pwm2_pin>; 515 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 516 clock-names = "pwm", "pclk"; 517 status = "disabled"; 518 }; 519 520 pwm3: pwm@ff200030 { 521 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 522 reg = <0x0 0xff200030 0x0 0x10>; 523 #pwm-cells = <3>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pwm3_pin>; 526 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 527 clock-names = "pwm", "pclk"; 528 status = "disabled"; 529 }; 530 531 pwm4: pwm@ff208000 { 532 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 533 reg = <0x0 0xff208000 0x0 0x10>; 534 #pwm-cells = <3>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pwm4_pin>; 537 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 538 clock-names = "pwm", "pclk"; 539 status = "disabled"; 540 }; 541 542 pwm5: pwm@ff208010 { 543 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 544 reg = <0x0 0xff208010 0x0 0x10>; 545 #pwm-cells = <3>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pwm5_pin>; 548 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 549 clock-names = "pwm", "pclk"; 550 status = "disabled"; 551 }; 552 553 pwm6: pwm@ff208020 { 554 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 555 reg = <0x0 0xff208020 0x0 0x10>; 556 #pwm-cells = <3>; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pwm6_pin>; 559 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 560 clock-names = "pwm", "pclk"; 561 status = "disabled"; 562 }; 563 564 pwm7: pwm@ff208030 { 565 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 566 reg = <0x0 0xff208030 0x0 0x10>; 567 #pwm-cells = <3>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pwm7_pin>; 570 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 571 clock-names = "pwm", "pclk"; 572 status = "disabled"; 573 }; 574 575 amba { 576 compatible = "simple-bus"; 577 #address-cells = <2>; 578 #size-cells = <2>; 579 ranges; 580 581 dmac: dmac@ff240000 { 582 compatible = "arm,pl330", "arm,primecell"; 583 reg = <0x0 0xff240000 0x0 0x4000>; 584 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&cru ACLK_DMAC>; 587 clock-names = "apb_pclk"; 588 #dma-cells = <1>; 589 peripherals-req-type-burst; 590 }; 591 }; 592 593 tsadc: tsadc@ff280000 { 594 compatible = "rockchip,px30-tsadc"; 595 reg = <0x0 0xff280000 0x0 0x100>; 596 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 597 rockchip,grf = <&grf>; 598 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 599 clock-names = "tsadc", "apb_pclk"; 600 assigned-clocks = <&cru SCLK_TSADC>; 601 assigned-clock-rates = <50000>; 602 resets = <&cru SRST_TSADC_P>; 603 reset-names = "tsadc-apb"; 604 pinctrl-names = "init", "default", "sleep"; 605 pinctrl-0 = <&tsadc_otp_gpio>; 606 pinctrl-1 = <&tsadc_otp_out>; 607 pinctrl-2 = <&tsadc_otp_gpio>; 608 #thermal-sensor-cells = <1>; 609 rockchip,hw-tshut-temp = <100000>; 610 status = "disabled"; 611 }; 612 613 saradc: saradc@ff288000 { 614 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 615 reg = <0x0 0xff288000 0x0 0x100>; 616 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 617 #io-channel-cells = <1>; 618 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 619 clock-names = "saradc", "apb_pclk"; 620 resets = <&cru SRST_SARADC_P>; 621 reset-names = "saradc-apb"; 622 status = "disabled"; 623 }; 624 625 cru: clock-controller@ff2b0000 { 626 compatible = "rockchip,px30-cru"; 627 reg = <0x0 0xff2b0000 0x0 0x9000>; 628 rockchip,grf = <&grf>; 629 #clock-cells = <1>; 630 #reset-cells = <1>; 631 632 assigned-clocks = 633 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 634 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 635 <&cru ARMCLK>; 636 assigned-clock-rates = 637 <1608000000>, <1416000000>, 638 <1188000000>, <1188000000>, 639 <816000000>; 640 }; 641 642 pmucru: pmu-clock-controller@ff2bc000 { 643 compatible = "rockchip,px30-pmucru"; 644 reg = <0x0 0xff2bc000 0x0 0x1000>; 645 rockchip,grf = <&grf>; 646 #clock-cells = <1>; 647 #reset-cells = <1>; 648 649 assigned-clocks = 650 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 651 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 652 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 653 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 654 assigned-clock-rates = 655 <1200000000>, <100000000>, 656 <26000000>, <300000000>, 657 <300000000>, <150000000>, 658 <150000000>, <75000000>; 659 }; 660 661 usb2phy_grf: syscon@ff2c0000 { 662 compatible = "rockchip,px30-usb2phy-grf", "syscon", 663 "simple-mfd"; 664 reg = <0x0 0xff2c0000 0x0 0x10000>; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 668 u2phy: usb2-phy@100 { 669 compatible = "rockchip,px30-usb2phy", 670 "rockchip,rk3328-usb2phy"; 671 reg = <0x100 0x10>; 672 clocks = <&pmucru SCLK_USBPHY_REF>; 673 clock-names = "phyclk"; 674 #clock-cells = <0>; 675 assigned-clocks = <&cru USB480M>; 676 assigned-clock-parents = <&u2phy>; 677 clock-output-names = "usb480m_phy"; 678 status = "disabled"; 679 680 u2phy_host: host-port { 681 #phy-cells = <0>; 682 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 683 interrupt-names = "linestate"; 684 status = "disabled"; 685 }; 686 687 u2phy_otg: otg-port { 688 #phy-cells = <0>; 689 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-names = "otg-bvalid", "otg-id", 693 "linestate"; 694 status = "disabled"; 695 }; 696 }; 697 }; 698 699 mipi_dphy: mipi-dphy@ff2e0000 { 700 compatible = "rockchip,px30-mipi-dphy"; 701 reg = <0x0 0xff2e0000 0x0 0x10000>; 702 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 703 clock-names = "ref", "pclk"; 704 clock-output-names = "mipi_dphy_pll"; 705 #clock-cells = <0>; 706 resets = <&cru SRST_MIPIDSIPHY_P>; 707 reset-names = "apb"; 708 power-domains = <&power PX30_PD_VO>; 709 #phy-cells = <0>; 710 rockchip,grf = <&grf>; 711 status = "disabled"; 712 }; 713 714 lvds: lvds@ff2e0000 { 715 compatible = "rockchip,px30-lvds"; 716 reg = <0x0 0xff2e0000 0x0 0x100>, <0x0 0xff2e0100 0x0 0x100>; 717 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 718 clocks = <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 719 clock-names = "pclk_lvds", "pclk_lvds_ctl"; 720 power-domains = <&power PX30_PD_VO>; 721 rockchip,grf = <&grf>; 722 status = "disabled"; 723 724 ports { 725 #address-cells = <1>; 726 #size-cells = <0>; 727 728 port@0 { 729 reg = <0>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 733 lvds_in_vopl: endpoint@0 { 734 reg = <0>; 735 remote-endpoint = <&vopl_out_lvds>; 736 }; 737 738 lvds_in_vopb: endpoint@1 { 739 reg = <1>; 740 remote-endpoint = <&vopb_out_lvds>; 741 }; 742 }; 743 }; 744 }; 745 746 usb20_otg: usb@ff300000 { 747 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 748 "snps,dwc2"; 749 reg = <0x0 0xff300000 0x0 0x40000>; 750 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&cru HCLK_OTG>; 752 clock-names = "otg"; 753 dr_mode = "otg"; 754 g-np-tx-fifo-size = <16>; 755 g-rx-fifo-size = <275>; 756 g-tx-fifo-size = <256 128 128 64 64 32>; 757 g-use-dma; 758 phys = <&u2phy_otg>; 759 phy-names = "usb2-phy"; 760 status = "disabled"; 761 }; 762 763 usb_host0_ehci: usb@ff340000 { 764 compatible = "generic-ehci"; 765 reg = <0x0 0xff340000 0x0 0x10000>; 766 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 768 <&u2phy>; 769 clock-names = "usbhost", "arbiter", "utmi"; 770 phys = <&u2phy_host>; 771 phy-names = "usb"; 772 status = "disabled"; 773 }; 774 775 usb_host0_ohci: usb@ff350000 { 776 compatible = "generic-ohci"; 777 reg = <0x0 0xff350000 0x0 0x10000>; 778 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 780 <&u2phy>; 781 clock-names = "usbhost", "arbiter", "utmi"; 782 phys = <&u2phy_host>; 783 phy-names = "usb"; 784 }; 785 786 gmac: ethernet@ff360000 { 787 compatible = "rockchip,px30-gmac"; 788 reg = <0x0 0xff360000 0x0 0x10000>; 789 rockchip,grf = <&grf>; 790 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 791 interrupt-names = "macirq"; 792 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 793 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 794 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 795 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 796 clock-names = "stmmaceth", "mac_clk_rx", 797 "mac_clk_tx", "clk_mac_ref", 798 "clk_mac_refout", "aclk_mac", 799 "pclk_mac", "clk_mac_speed"; 800 phy-mode = "rmii"; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 803 resets = <&cru SRST_GMAC_A>; 804 reset-names = "stmmaceth"; 805 power-domains = <&power PX30_PD_GMAC>; 806 status = "disabled"; 807 }; 808 809 sdmmc: dwmmc@ff370000 { 810 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 811 reg = <0x0 0xff370000 0x0 0x4000>; 812 max-frequency = <150000000>; 813 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 814 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 815 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 816 fifo-depth = <0x100>; 817 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 818 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 821 status = "disabled"; 822 }; 823 824 sdio: dwmmc@ff380000 { 825 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 826 reg = <0x0 0xff380000 0x0 0x4000>; 827 max-frequency = <150000000>; 828 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 829 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 830 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 831 fifo-depth = <0x100>; 832 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 833 status = "disabled"; 834 }; 835 836 emmc: dwmmc@ff390000 { 837 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 838 reg = <0x0 0xff390000 0x0 0x4000>; 839 max-frequency = <150000000>; 840 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 841 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 842 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 843 fifo-depth = <0x100>; 844 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 845 status = "disabled"; 846 }; 847 848 nandc0: nandc@ff3b0000 { 849 compatible = "rockchip,rk-nandc"; 850 reg = <0x0 0xff3b0000 0x0 0x4000>; 851 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 852 nandc_id = <0>; 853 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 854 clock-names = "clk_nandc", "hclk_nandc"; 855 status = "disabled"; 856 }; 857 858 gpu: gpu@ff400000 { 859 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 860 reg = <0x0 0xff400000 0x0 0x4000>; 861 862 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 865 interrupt-names = "GPU", "MMU", "JOB"; 866 867 clocks = <&cru ACLK_GPU>; 868 clock-names = "clk_mali"; 869 870 status = "disabled"; 871 }; 872 873 hevc: hevc_service@ff440000 { 874 compatible = "rockchip,hevc_sub"; 875 iommu_enabled = <1>; 876 reg = <0x0 0xff440000 0x0 0x400>; 877 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 878 interrupt-names = "irq_dec"; 879 dev_mode = <1>; 880 iommus = <&hevc_mmu>; 881 name = "hevc_service"; 882 allocator = <1>; 883 }; 884 885 vpu: vpu_service@ff442000 { 886 compatible = "rockchip,vpu_sub"; 887 iommu_enabled = <1>; 888 reg = <0x0 0xff442000 0x0 0x800>; 889 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "irq_enc", "irq_dec"; 892 dev_mode = <0>; 893 iommus = <&vpu_mmu>; 894 name = "vpu_service"; 895 allocator = <1>; 896 }; 897 898 vpu_combo: vpu_combo { 899 compatible = "rockchip,vpu_combo"; 900 subcnt = <2>; 901 rockchip,grf = <&grf>; 902 rockchip,sub = <&vpu>, <&hevc>; 903 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 904 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 905 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 906 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 907 <&cru SRST_VPU_CORE>; 908 reset-names = "video_a", "video_h", "niu_a", "niu_h", 909 "video_core"; 910 mode_bit = <15>; 911 mode_ctrl = <0x410>; 912 name = "vpu_combo"; 913 status = "disabled"; 914 }; 915 916 hevc_mmu: iommu@ff440440 { 917 compatible = "rockchip,iommu"; 918 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 919 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 920 interrupt-names = "hevc_mmu"; 921 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 922 clock-names = "aclk", "hclk"; 923 #iommu-cells = <0>; 924 }; 925 926 vpu_mmu: iommu@ff442800 { 927 compatible = "rockchip,iommu"; 928 reg = <0x0 0xff442800 0x0 0x100>; 929 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "vpu_mmu"; 931 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 932 clock-names = "aclk", "hclk"; 933 #iommu-cells = <0>; 934 }; 935 936 dsi: dsi@ff450000 { 937 compatible = "rockchip,px30-mipi-dsi"; 938 reg = <0x0 0xff450000 0x0 0x10000>; 939 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&cru PCLK_MIPI_DSI>, <&mipi_dphy>; 941 clock-names = "pclk", "hs_clk"; 942 resets = <&cru SRST_MIPIDSI_HOST_P>; 943 reset-names = "apb"; 944 phys = <&mipi_dphy>; 945 phy-names = "mipi_dphy"; 946 power-domains = <&power PX30_PD_VO>; 947 rockchip,grf = <&grf>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 952 ports { 953 port { 954 #address-cells = <1>; 955 #size-cells = <0>; 956 957 dsi_in_vopl: endpoint@0 { 958 reg = <0>; 959 remote-endpoint = <&vopl_out_dsi>; 960 }; 961 962 dsi_in_vopb: endpoint@1 { 963 reg = <1>; 964 remote-endpoint = <&vopb_out_dsi>; 965 }; 966 }; 967 }; 968 }; 969 970 vopb: vop@ff460000 { 971 compatible = "rockchip,px30-vop-big"; 972 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 973 reg-names = "regs", "gamma_lut"; 974 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 976 <&cru HCLK_VOPB>; 977 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 978 iommus = <&vopb_mmu>; 979 status = "disabled"; 980 981 vopb_out: port { 982 #address-cells = <1>; 983 #size-cells = <0>; 984 985 vopb_out_lvds: endpoint@0 { 986 reg = <0>; 987 remote-endpoint = <&lvds_in_vopb>; 988 }; 989 990 vopb_out_dsi: endpoint@1 { 991 reg = <1>; 992 remote-endpoint = <&dsi_in_vopb>; 993 }; 994 }; 995 }; 996 997 vopb_mmu: iommu@ff460f00 { 998 compatible = "rockchip,iommu"; 999 reg = <0x0 0xff460f00 0x0 0x100>; 1000 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1001 interrupt-names = "vopb_mmu"; 1002 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1003 clock-names = "aclk", "hclk"; 1004 #iommu-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 1008 vopl: vop@ff470000 { 1009 compatible = "rockchip,px30-vop-lit"; 1010 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 1011 reg-names = "regs", "gamma_lut"; 1012 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1014 <&cru HCLK_VOPL>; 1015 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1016 iommus = <&vopl_mmu>; 1017 status = "disabled"; 1018 1019 vopl_out: port { 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 1023 vopl_out_lvds: endpoint@0 { 1024 reg = <0>; 1025 remote-endpoint = <&lvds_in_vopl>; 1026 }; 1027 1028 vopl_out_dsi: endpoint@1 { 1029 reg = <1>; 1030 remote-endpoint = <&dsi_in_vopl>; 1031 }; 1032 }; 1033 }; 1034 1035 vopl_mmu: iommu@ff470f00 { 1036 compatible = "rockchip,iommu"; 1037 reg = <0x0 0xff470f00 0x0 0x100>; 1038 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1039 interrupt-names = "vopl_mmu"; 1040 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1041 clock-names = "aclk", "hclk"; 1042 #iommu-cells = <0>; 1043 status = "disabled"; 1044 }; 1045 1046 rk_rga: rk_rga@ff480000 { 1047 compatible = "rockchip,rga2"; 1048 //dev_mode = <1>; 1049 reg = <0x0 0xff480000 0x0 0x1000>; 1050 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1052 clock-names = "aclk_rga", "hclk_rga"; 1053 dma-coherent; 1054 status = "disabled"; 1055 }; 1056 1057 cif: cif@ff490000 { 1058 compatible = "rockchip,cif"; 1059 reg = <0x0 0xff490000 0x0 0x200>; 1060 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1062 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1063 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1064 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1065 pinctrl-names = "cif_pin_all"; 1066 pinctrl-0 = <&dvp_d2d9_m0>; 1067 status = "disabled"; 1068 }; 1069 1070 vip_mmu: iommu@ff490800{ 1071 compatible = "rockchip,iommu"; 1072 reg = <0x0 0xff490800 0x0 0x100>; 1073 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1074 interrupt-names = "vip_mmu"; 1075 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1076 clock-names = "aclk", "hclk"; 1077 rk_iommu,disable_reset_quirk; 1078 #iommu-cells = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 rk_isp: rk_isp@ff4a0000 { 1083 compatible = "rockchip,px30-isp", "rockchip,isp"; 1084 reg = <0x0 0xff4a0000 0x0 0x4000>; 1085 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1087 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1088 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1089 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1090 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1091 reset-names = "rst_isp", "rst_mipicsiphy"; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&cif_clkout_m0>; 1094 rockchip,isp,mipiphy = <0>; 1095 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1096 rockchip,grf = <&grf>; 1097 rockchip,cru = <&cru>; 1098 rockchip,isp,iommu-enable = <1>; 1099 iommus = <&isp_mmu>; 1100 status = "disabled"; 1101 }; 1102 1103 isp_mmu: iommu@ff4a8000 { 1104 compatible = "rockchip,iommu"; 1105 reg = <0x0 0xff4a8000 0x0 0x100>; 1106 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1107 interrupt-names = "isp_mmu"; 1108 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1109 clock-names = "aclk", "hclk"; 1110 rk_iommu,disable_reset_quirk; 1111 #iommu-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 qos_gmac: qos@ff518000 { 1116 compatible = "syscon"; 1117 reg = <0x0 0xff518000 0x0 0x20>; 1118 }; 1119 1120 qos_gpu: qos@ff520000 { 1121 compatible = "syscon"; 1122 reg = <0x0 0xff520000 0x0 0x20>; 1123 }; 1124 1125 qos_sdmmc: qos@ff52c000 { 1126 compatible = "syscon"; 1127 reg = <0x0 0xff52c000 0x0 0x20>; 1128 }; 1129 1130 qos_emmc: qos@ff538000 { 1131 compatible = "syscon"; 1132 reg = <0x0 0xff538000 0x0 0x20>; 1133 }; 1134 1135 qos_nand: qos@ff538080 { 1136 compatible = "syscon"; 1137 reg = <0x0 0xff538080 0x0 0x20>; 1138 }; 1139 1140 qos_sdio: qos@ff538100 { 1141 compatible = "syscon"; 1142 reg = <0x0 0xff538100 0x0 0x20>; 1143 }; 1144 1145 qos_sfc: qos@ff538180 { 1146 compatible = "syscon"; 1147 reg = <0x0 0xff538180 0x0 0x20>; 1148 }; 1149 1150 qos_usb_host: qos@ff540000 { 1151 compatible = "syscon"; 1152 reg = <0x0 0xff540000 0x0 0x20>; 1153 }; 1154 1155 qos_usb_otg: qos@ff540080 { 1156 compatible = "syscon"; 1157 reg = <0x0 0xff540080 0x0 0x20>; 1158 }; 1159 1160 qos_isp_128: qos@ff548000 { 1161 compatible = "syscon"; 1162 reg = <0x0 0xff548000 0x0 0x20>; 1163 }; 1164 1165 qos_isp_rd: qos@ff548080 { 1166 compatible = "syscon"; 1167 reg = <0x0 0xff548080 0x0 0x20>; 1168 }; 1169 1170 qos_isp_wr: qos@ff548100 { 1171 compatible = "syscon"; 1172 reg = <0x0 0xff548100 0x0 0x20>; 1173 }; 1174 1175 qos_isp_m1: qos@ff548180 { 1176 compatible = "syscon"; 1177 reg = <0x0 0xff548180 0x0 0x20>; 1178 }; 1179 1180 qos_vip: qos@ff548200 { 1181 compatible = "syscon"; 1182 reg = <0x0 0xff548200 0x0 0x20>; 1183 }; 1184 1185 qos_rga_rd: qos@ff550000 { 1186 compatible = "syscon"; 1187 reg = <0x0 0xff550000 0x0 0x20>; 1188 }; 1189 1190 qos_rga_wr: qos@ff550080 { 1191 compatible = "syscon"; 1192 reg = <0x0 0xff550080 0x0 0x20>; 1193 }; 1194 1195 qos_vop_m0: qos@ff550100 { 1196 compatible = "syscon"; 1197 reg = <0x0 0xff550100 0x0 0x20>; 1198 }; 1199 1200 qos_vop_m1: qos@ff550180 { 1201 compatible = "syscon"; 1202 reg = <0x0 0xff550180 0x0 0x20>; 1203 }; 1204 1205 qos_vpu: qos@ff558000 { 1206 compatible = "syscon"; 1207 reg = <0x0 0xff558000 0x0 0x20>; 1208 }; 1209 1210 qos_vpu_r128: qos@ff558080 { 1211 compatible = "syscon"; 1212 reg = <0x0 0xff558080 0x0 0x20>; 1213 }; 1214 1215 pinctrl: pinctrl { 1216 compatible = "rockchip,px30-pinctrl"; 1217 rockchip,grf = <&grf>; 1218 rockchip,pmu = <&pmugrf>; 1219 #address-cells = <2>; 1220 #size-cells = <2>; 1221 ranges; 1222 1223 gpio0: gpio0@ff040000 { 1224 compatible = "rockchip,gpio-bank"; 1225 reg = <0x0 0xff040000 0x0 0x100>; 1226 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&cru PCLK_GPIO0_PMU>; 1228 gpio-controller; 1229 #gpio-cells = <2>; 1230 1231 interrupt-controller; 1232 #interrupt-cells = <2>; 1233 }; 1234 1235 gpio1: gpio1@ff250000 { 1236 compatible = "rockchip,gpio-bank"; 1237 reg = <0x0 0xff250000 0x0 0x100>; 1238 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&cru PCLK_GPIO1>; 1240 gpio-controller; 1241 #gpio-cells = <2>; 1242 1243 interrupt-controller; 1244 #interrupt-cells = <2>; 1245 }; 1246 1247 gpio2: gpio2@ff260000 { 1248 compatible = "rockchip,gpio-bank"; 1249 reg = <0x0 0xff260000 0x0 0x100>; 1250 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&cru PCLK_GPIO2>; 1252 gpio-controller; 1253 #gpio-cells = <2>; 1254 1255 interrupt-controller; 1256 #interrupt-cells = <2>; 1257 }; 1258 1259 gpio3: gpio3@ff270000 { 1260 compatible = "rockchip,gpio-bank"; 1261 reg = <0x0 0xff270000 0x0 0x100>; 1262 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&cru PCLK_GPIO3>; 1264 gpio-controller; 1265 #gpio-cells = <2>; 1266 1267 interrupt-controller; 1268 #interrupt-cells = <2>; 1269 }; 1270 1271 pcfg_pull_up: pcfg-pull-up { 1272 bias-pull-up; 1273 }; 1274 1275 pcfg_pull_down: pcfg-pull-down { 1276 bias-pull-down; 1277 }; 1278 1279 pcfg_pull_none: pcfg-pull-none { 1280 bias-disable; 1281 }; 1282 1283 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1284 bias-disable; 1285 drive-strength = <2>; 1286 }; 1287 1288 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1289 bias-pull-up; 1290 drive-strength = <2>; 1291 }; 1292 1293 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1294 bias-pull-up; 1295 drive-strength = <4>; 1296 }; 1297 1298 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1299 bias-disable; 1300 drive-strength = <4>; 1301 }; 1302 1303 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1304 bias-pull-down; 1305 drive-strength = <4>; 1306 }; 1307 1308 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1309 bias-disable; 1310 drive-strength = <8>; 1311 }; 1312 1313 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1314 bias-pull-up; 1315 drive-strength = <8>; 1316 }; 1317 1318 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1319 bias-disable; 1320 drive-strength = <12>; 1321 }; 1322 1323 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1324 bias-pull-up; 1325 drive-strength = <12>; 1326 }; 1327 1328 pcfg_pull_none_smt: pcfg-pull-none-smt { 1329 bias-disable; 1330 input-schmitt-enable; 1331 }; 1332 1333 pcfg_output_high: pcfg-output-high { 1334 output-high; 1335 }; 1336 1337 pcfg_output_low: pcfg-output-low { 1338 output-low; 1339 }; 1340 1341 pcfg_input_high: pcfg-input-high { 1342 bias-pull-up; 1343 input-enable; 1344 }; 1345 1346 pcfg_input: pcfg-input { 1347 input-enable; 1348 }; 1349 1350 i2c0 { 1351 i2c0_xfer: i2c0-xfer { 1352 rockchip,pins = 1353 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1354 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1355 }; 1356 }; 1357 1358 i2c1 { 1359 i2c1_xfer: i2c1-xfer { 1360 rockchip,pins = 1361 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1362 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1363 }; 1364 }; 1365 1366 i2c2 { 1367 i2c2_xfer: i2c2-xfer { 1368 rockchip,pins = 1369 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1370 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1371 }; 1372 }; 1373 1374 i2c3 { 1375 i2c3_xfer: i2c3-xfer { 1376 rockchip,pins = 1377 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1378 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1379 }; 1380 }; 1381 1382 tsadc { 1383 tsadc_otp_gpio: tsadc-otp-gpio { 1384 rockchip,pins = 1385 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1386 }; 1387 1388 tsadc_otp_out: tsadc-otp-out { 1389 rockchip,pins = 1390 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1391 }; 1392 }; 1393 1394 uart0 { 1395 uart0_xfer: uart0-xfer { 1396 rockchip,pins = 1397 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1398 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1399 }; 1400 1401 uart0_cts: uart0-cts { 1402 rockchip,pins = 1403 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1404 }; 1405 1406 uart0_rts: uart0-rts { 1407 rockchip,pins = 1408 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1409 }; 1410 1411 uart0_rts_gpio: uart0-rts-gpio { 1412 rockchip,pins = 1413 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1414 }; 1415 }; 1416 1417 uart1 { 1418 uart1_xfer: uart1-xfer { 1419 rockchip,pins = 1420 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1421 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1422 }; 1423 1424 uart1_cts: uart1-cts { 1425 rockchip,pins = 1426 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1427 }; 1428 1429 uart1_rts: uart1-rts { 1430 rockchip,pins = 1431 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1432 }; 1433 1434 uart1_rts_gpio: uart1-rts-gpio { 1435 rockchip,pins = 1436 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1437 }; 1438 }; 1439 1440 uart2-m0 { 1441 uart2m0_xfer: uart2m0-xfer { 1442 rockchip,pins = 1443 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1444 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1445 }; 1446 }; 1447 1448 uart2-m1 { 1449 uart2m1_xfer: uart2m1-xfer { 1450 rockchip,pins = 1451 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1452 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1453 }; 1454 }; 1455 1456 uart3-m0 { 1457 uart3m0_xfer: uart3m0-xfer { 1458 rockchip,pins = 1459 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1460 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1461 }; 1462 1463 uart3m0_cts: uart3m0-cts { 1464 rockchip,pins = 1465 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1466 }; 1467 1468 uart3m0_rts: uart3m0-rts { 1469 rockchip,pins = 1470 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1471 }; 1472 1473 uart3m0_rts_gpio: uart3m0-rts-gpio { 1474 rockchip,pins = 1475 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1476 }; 1477 }; 1478 1479 uart3-m1 { 1480 uart3m1_xfer: uart3m1-xfer { 1481 rockchip,pins = 1482 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1483 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1484 }; 1485 1486 uart3m1_cts: uart3m1-cts { 1487 rockchip,pins = 1488 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1489 }; 1490 1491 uart3m1_rts: uart3m1-rts { 1492 rockchip,pins = 1493 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1494 }; 1495 1496 uart3m1_rts_gpio: uart3m1-rts-gpio { 1497 rockchip,pins = 1498 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1499 }; 1500 }; 1501 1502 uart4 { 1503 1504 uart4_xfer: uart4-xfer { 1505 rockchip,pins = 1506 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1507 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1508 }; 1509 1510 uart4_cts: uart4-cts { 1511 rockchip,pins = 1512 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1513 1514 }; 1515 1516 uart4_rts: uart4-rts { 1517 rockchip,pins = 1518 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1519 }; 1520 }; 1521 1522 uart5 { 1523 1524 uart5_xfer: uart5-xfer { 1525 rockchip,pins = 1526 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1527 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1528 }; 1529 1530 uart5_cts: uart5-cts { 1531 rockchip,pins = 1532 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1533 1534 }; 1535 1536 uart5_rts: uart5-rts { 1537 rockchip,pins = 1538 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1539 }; 1540 }; 1541 1542 spi0 { 1543 spi0_clk: spi0-clk { 1544 rockchip,pins = 1545 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1546 }; 1547 1548 spi0_csn: spi0-csn { 1549 rockchip,pins = 1550 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1551 }; 1552 1553 spi0_miso: spi0-miso { 1554 rockchip,pins = 1555 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1556 }; 1557 1558 spi0_mosi: spi0-mosi { 1559 rockchip,pins = 1560 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1561 }; 1562 }; 1563 1564 spi1 { 1565 spi1_clk: spi1-clk { 1566 rockchip,pins = 1567 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1568 }; 1569 1570 spi1_csn: spi1-csn { 1571 rockchip,pins = 1572 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1573 }; 1574 1575 spi1_miso: spi1-miso { 1576 rockchip,pins = 1577 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1578 }; 1579 1580 spi1_mosi: spi1-mosi { 1581 rockchip,pins = 1582 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1583 }; 1584 }; 1585 1586 pdm { 1587 pdm_clk0m0: pdm-clk0m0 { 1588 rockchip,pins = 1589 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1590 }; 1591 1592 pdm_clk0m1: pdm-clk0m1 { 1593 rockchip,pins = 1594 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1595 }; 1596 1597 pdm_clk1: pdm-clk1 { 1598 rockchip,pins = 1599 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1600 }; 1601 1602 pdm_sdi0m0: pdm-sdi0m0 { 1603 rockchip,pins = 1604 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1605 }; 1606 1607 pdm_sdi0m1: pdm-sdi0m1 { 1608 rockchip,pins = 1609 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1610 }; 1611 1612 pdm_sdi1: pdm-sdi1 { 1613 rockchip,pins = 1614 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1615 }; 1616 1617 pdm_sdi2: pdm-sdi2 { 1618 rockchip,pins = 1619 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1620 }; 1621 1622 pdm_sdi3: pdm-sdi3 { 1623 rockchip,pins = 1624 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1625 }; 1626 1627 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1628 rockchip,pins = 1629 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1630 }; 1631 1632 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1633 rockchip,pins = 1634 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1635 }; 1636 1637 pdm_clk1_sleep: pdm-clk1-sleep { 1638 rockchip,pins = 1639 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1640 }; 1641 1642 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1643 rockchip,pins = 1644 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1645 }; 1646 1647 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1648 rockchip,pins = 1649 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1650 }; 1651 1652 pdm_sdi1_sleep: pdm-sdi1-sleep { 1653 rockchip,pins = 1654 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1655 }; 1656 1657 pdm_sdi2_sleep: pdm-sdi2-sleep { 1658 rockchip,pins = 1659 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1660 }; 1661 1662 pdm_sdi3_sleep: pdm-sdi3-sleep { 1663 rockchip,pins = 1664 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1665 }; 1666 }; 1667 1668 i2s0 { 1669 i2s0_8ch_mclk: i2s0-8ch-mclk { 1670 rockchip,pins = 1671 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1672 }; 1673 1674 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1675 rockchip,pins = 1676 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1677 }; 1678 1679 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1680 rockchip,pins = 1681 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1682 }; 1683 1684 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1685 rockchip,pins = 1686 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1687 }; 1688 1689 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1690 rockchip,pins = 1691 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1692 }; 1693 1694 i2s0_8ch_sdo: i2s0-8ch-sdo { 1695 rockchip,pins = 1696 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1697 }; 1698 1699 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1700 rockchip,pins = 1701 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1702 }; 1703 1704 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1705 rockchip,pins = 1706 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1707 }; 1708 1709 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1710 rockchip,pins = 1711 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1712 }; 1713 1714 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1715 rockchip,pins = 1716 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1717 }; 1718 1719 i2s0_8ch_sdi: i2s0-8ch-sdi { 1720 rockchip,pins = 1721 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1722 }; 1723 1724 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1725 rockchip,pins = 1726 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1727 }; 1728 1729 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1730 rockchip,pins = 1731 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1732 }; 1733 1734 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1735 rockchip,pins = 1736 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1737 }; 1738 1739 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1740 rockchip,pins = 1741 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1742 }; 1743 }; 1744 1745 i2s1 { 1746 i2s1_2ch_mclk: i2s1-2ch-mclk { 1747 rockchip,pins = 1748 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1749 }; 1750 1751 i2s1_2ch_sclk: i2s1-2ch-sclk { 1752 rockchip,pins = 1753 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1754 }; 1755 1756 i2s1_2ch_lrck: i2s1-2ch-lrck { 1757 rockchip,pins = 1758 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1759 }; 1760 1761 i2s1_2ch_sdi: i2s1-2ch-sdi { 1762 rockchip,pins = 1763 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1764 }; 1765 1766 i2s1_2ch_sdo: i2s1-2ch-sdo { 1767 rockchip,pins = 1768 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1769 }; 1770 }; 1771 1772 i2s2 { 1773 i2s2_2ch_mclk: i2s2-2ch-mclk { 1774 rockchip,pins = 1775 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1776 }; 1777 1778 i2s2_2ch_sclk: i2s2-2ch-sclk { 1779 rockchip,pins = 1780 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1781 }; 1782 1783 i2s2_2ch_lrck: i2s2-2ch-lrck { 1784 rockchip,pins = 1785 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1786 }; 1787 1788 i2s2_2ch_sdi: i2s2-2ch-sdi { 1789 rockchip,pins = 1790 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1791 }; 1792 1793 i2s2_2ch_sdo: i2s2-2ch-sdo { 1794 rockchip,pins = 1795 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1796 }; 1797 }; 1798 1799 sdmmc { 1800 sdmmc_clk: sdmmc-clk { 1801 rockchip,pins = 1802 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_8ma>; 1803 }; 1804 1805 sdmmc_cmd: sdmmc-cmd { 1806 rockchip,pins = 1807 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_8ma>; 1808 }; 1809 1810 sdmmc_det: sdmmc-det { 1811 rockchip,pins = 1812 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>; 1813 }; 1814 1815 sdmmc_bus1: sdmmc-bus1 { 1816 rockchip,pins = 1817 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>; 1818 }; 1819 1820 sdmmc_bus4: sdmmc-bus4 { 1821 rockchip,pins = 1822 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>, 1823 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_8ma>, 1824 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_8ma>, 1825 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_8ma>; 1826 }; 1827 1828 sdmmc_gpio: sdmmc-gpio { 1829 rockchip,pins = 1830 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1831 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1832 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1833 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1834 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1835 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1836 }; 1837 }; 1838 1839 sdio { 1840 sdio_clk: sdio-clk { 1841 rockchip,pins = 1842 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1843 }; 1844 1845 sdio_cmd: sdio-cmd { 1846 rockchip,pins = 1847 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1848 }; 1849 1850 sdio_bus4: sdio-bus4 { 1851 rockchip,pins = 1852 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1853 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>, 1854 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>, 1855 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>; 1856 }; 1857 1858 sdio_gpio: sdio-gpio { 1859 rockchip,pins = 1860 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 1861 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, 1862 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, 1863 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, 1864 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, 1865 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 1866 }; 1867 }; 1868 1869 emmc { 1870 emmc_clk: emmc-clk { 1871 rockchip,pins = 1872 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1873 }; 1874 1875 emmc_cmd: emmc-cmd { 1876 rockchip,pins = 1877 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1878 }; 1879 1880 emmc_pwren: emmc-pwren { 1881 rockchip,pins = 1882 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1883 }; 1884 1885 emmc_rstnout: emmc-rstnout { 1886 rockchip,pins = 1887 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1888 }; 1889 1890 emmc_bus1: emmc-bus1 { 1891 rockchip,pins = 1892 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1893 }; 1894 1895 emmc_bus4: emmc-bus4 { 1896 rockchip,pins = 1897 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1898 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1899 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1900 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1901 }; 1902 1903 emmc_bus8: emmc-bus8 { 1904 rockchip,pins = 1905 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1906 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1907 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1908 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1909 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1910 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1911 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1912 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1913 }; 1914 }; 1915 1916 flash { 1917 flash_cs0: flash-cs0 { 1918 rockchip,pins = 1919 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1920 }; 1921 1922 flash_rdy: flash-rdy { 1923 rockchip,pins = 1924 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1925 }; 1926 1927 flash_dqs: flash-dqs { 1928 rockchip,pins = 1929 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1930 }; 1931 1932 flash_ale: flash-ale { 1933 rockchip,pins = 1934 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1935 }; 1936 1937 flash_cle: flash-cle { 1938 rockchip,pins = 1939 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1940 }; 1941 1942 flash_wrn: flash-wrn { 1943 rockchip,pins = 1944 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1945 }; 1946 1947 flash_csl: flash-csl { 1948 rockchip,pins = 1949 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 1950 }; 1951 1952 flash_rdn: flash-rdn { 1953 rockchip,pins = 1954 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 1955 }; 1956 1957 flash_bus8: flash-bus8 { 1958 rockchip,pins = 1959 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 1960 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 1961 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 1962 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 1963 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 1964 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 1965 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 1966 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 1967 }; 1968 }; 1969 1970 lcdc { 1971 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1972 rockchip,pins = 1973 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1974 }; 1975 1976 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1977 rockchip,pins = 1978 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1979 }; 1980 1981 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1982 rockchip,pins = 1983 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>; 1984 }; 1985 1986 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1987 rockchip,pins = 1988 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 1989 }; 1990 1991 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1992 rockchip,pins = 1993 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 1994 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 1995 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 1996 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 1997 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 1998 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 1999 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2000 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2001 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2002 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2003 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2004 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2005 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2006 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2007 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2008 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2009 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 2010 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 2011 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2012 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2013 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2014 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2015 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2016 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2017 }; 2018 2019 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2020 rockchip,pins = 2021 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2022 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2023 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2024 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2025 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2026 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2027 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2028 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2029 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2030 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2031 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2032 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2033 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2034 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2035 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2036 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2037 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2038 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2039 }; 2040 2041 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2042 rockchip,pins = 2043 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2044 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2045 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2046 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2047 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2048 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2049 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2050 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2051 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2052 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2053 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2054 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2055 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2056 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2057 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2058 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2059 }; 2060 2061 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2062 rockchip,pins = 2063 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2064 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2065 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2066 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2067 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2068 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2069 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2070 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2071 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2072 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 2073 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 2074 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2075 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2076 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2077 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2078 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2079 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2080 }; 2081 2082 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2083 rockchip,pins = 2084 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2085 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2086 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2087 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2088 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2089 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2090 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2091 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2092 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2093 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2094 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2095 }; 2096 2097 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2098 rockchip,pins = 2099 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2100 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2101 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2102 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2103 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2104 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2105 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2106 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2107 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2108 }; 2109 }; 2110 2111 pwm0 { 2112 pwm0_pin: pwm0-pin { 2113 rockchip,pins = 2114 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2115 }; 2116 }; 2117 2118 pwm1 { 2119 pwm1_pin: pwm1-pin { 2120 rockchip,pins = 2121 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2122 }; 2123 }; 2124 2125 pwm2 { 2126 pwm2_pin: pwm2-pin { 2127 rockchip,pins = 2128 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2129 }; 2130 }; 2131 2132 pwm3 { 2133 pwm3_pin: pwm3-pin { 2134 rockchip,pins = 2135 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2136 }; 2137 }; 2138 2139 pwm4 { 2140 pwm4_pin: pwm4-pin { 2141 rockchip,pins = 2142 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2143 }; 2144 }; 2145 2146 pwm5 { 2147 pwm5_pin: pwm5-pin { 2148 rockchip,pins = 2149 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2150 }; 2151 }; 2152 2153 pwm6 { 2154 pwm6_pin: pwm6-pin { 2155 rockchip,pins = 2156 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2157 }; 2158 }; 2159 2160 pwm7 { 2161 pwm7_pin: pwm7-pin { 2162 rockchip,pins = 2163 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2164 }; 2165 }; 2166 2167 gmac { 2168 rmii_pins: rmii-pins { 2169 rockchip,pins = 2170 /* mac_txen */ 2171 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2172 /* mac_txd1 */ 2173 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2174 /* mac_txd0 */ 2175 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2176 /* mac_rxd0 */ 2177 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2178 /* mac_rxd1 */ 2179 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2180 /* mac_rxer */ 2181 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2182 /* mac_rxdv */ 2183 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2184 /* mac_mdio */ 2185 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2186 /* mac_mdc */ 2187 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2188 }; 2189 2190 mac_refclk_12ma: mac-refclk-12ma { 2191 rockchip,pins = 2192 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none_12ma>; 2193 }; 2194 2195 mac_refclk: mac-refclk { 2196 rockchip,pins = 2197 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2198 }; 2199 }; 2200 2201 cif-m0 { 2202 cif_clkout_m0: cif-clkout-m0 { 2203 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2204 }; 2205 2206 dvp_d2d9_m0: dvp-d2d9-m0 { 2207 rockchip,pins = 2208 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2209 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2210 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2211 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2212 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2213 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2214 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2215 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2216 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2217 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2218 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2219 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2220 }; 2221 2222 dvp_d0d1_m0: dvp-d0d1-m0 { 2223 rockchip,pins = 2224 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2225 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2226 }; 2227 2228 dvp_d10d11_m0:d10-d11-m0 { 2229 rockchip,pins = 2230 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2231 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2232 }; 2233 }; 2234 2235 cif-m1 { 2236 cif_clkout_m1: cif-clkout-m1 { 2237 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2238 }; 2239 2240 dvp_d2d9_m1: dvp-d2d9-m1 { 2241 rockchip,pins = 2242 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2243 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2244 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2245 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2246 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2247 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2248 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2249 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2250 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2251 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2252 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2253 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2254 }; 2255 2256 dvp_d0d1_m1: dvp-d0d1-m1 { 2257 rockchip,pins = 2258 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2259 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2260 }; 2261 2262 dvp_d10d11_m1:d10-d11-m1 { 2263 rockchip,pins = 2264 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2265 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2266 }; 2267 }; 2268 2269 isp { 2270 isp_prelight: isp-prelight { 2271 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2272 }; 2273 }; 2274 }; 2275}; 2276