1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 display_subsystem: display-subsystem { 73 compatible = "rockchip,display-subsystem"; 74 ports = <&vopb_out>, <&vopl_out>; 75 status = "disabled"; 76 }; 77 78 firmware { 79 optee { 80 compatible = "linaro,optee-tz"; 81 method = "smc"; 82 }; 83 }; 84 85 psci { 86 compatible = "arm,psci-1.0"; 87 method = "smc"; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 93 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 }; 97 98 xin24m: xin24m { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <24000000>; 102 clock-output-names = "xin24m"; 103 }; 104 105 pmu: power-management@ff000000 { 106 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 107 reg = <0x0 0xff000000 0x0 0x1000>; 108 109 power: power-controller { 110 compatible = "rockchip,px30-power-controller"; 111 #power-domain-cells = <1>; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 status = "disabled"; 115 116 /* These power domains are grouped by VD_LOGIC */ 117 pd_usb@PX30_PD_USB { 118 reg = <PX30_PD_USB>; 119 clocks = <&cru HCLK_HOST>, 120 <&cru HCLK_OTG>, 121 <&cru SCLK_OTG_ADP>; 122 }; 123 pd_sdcard@PX30_PD_SDCARD { 124 reg = <PX30_PD_SDCARD>; 125 clocks = <&cru HCLK_SDMMC>, 126 <&cru SCLK_SDMMC>; 127 }; 128 pd_gmac@PX30_PD_GMAC { 129 reg = <PX30_PD_GMAC>; 130 clocks = <&cru ACLK_GMAC>, 131 <&cru PCLK_GMAC>, 132 <&cru SCLK_MAC_REF>, 133 <&cru SCLK_GMAC_RX_TX>; 134 }; 135 pd_mmc_nand@PX30_PD_MMC_NAND { 136 reg = <PX30_PD_MMC_NAND>; 137 clocks = <&cru HCLK_NANDC>, 138 <&cru HCLK_EMMC>, 139 <&cru HCLK_SDIO>, 140 <&cru HCLK_SFC>, 141 <&cru SCLK_EMMC>, 142 <&cru SCLK_NANDC>, 143 <&cru SCLK_SDIO>, 144 <&cru SCLK_SFC>; 145 }; 146 pd_vpu@PX30_PD_VPU { 147 reg = <PX30_PD_VPU>; 148 clocks = <&cru ACLK_VPU>, 149 <&cru HCLK_VPU>, 150 <&cru SCLK_CORE_VPU>; 151 }; 152 pd_vo@PX30_PD_VO { 153 reg = <PX30_PD_VO>; 154 clocks = <&cru ACLK_RGA>, 155 <&cru ACLK_VOPB>, 156 <&cru ACLK_VOPL>, 157 <&cru DCLK_VOPB>, 158 <&cru DCLK_VOPL>, 159 <&cru HCLK_RGA>, 160 <&cru HCLK_VOPB>, 161 <&cru HCLK_VOPL>, 162 <&cru PCLK_MIPI_DSI>, 163 <&cru SCLK_RGA_CORE>, 164 <&cru SCLK_VOPB_PWM>; 165 }; 166 pd_vi@PX30_PD_VI { 167 reg = <PX30_PD_VI>; 168 clocks = <&cru ACLK_CIF>, 169 <&cru ACLK_ISP>, 170 <&cru HCLK_CIF>, 171 <&cru HCLK_ISP>, 172 <&cru SCLK_ISP>; 173 }; 174 pd_gpu@PX30_PD_GPU { 175 reg = <PX30_PD_GPU>; 176 clocks = <&cru ACLK_GPU>; 177 }; 178 }; 179 }; 180 181 pmugrf: syscon@ff010000 { 182 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 183 reg = <0x0 0xff010000 0x0 0x1000>; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 187 pmu_io_domains: io-domains { 188 compatible = "rockchip,px30-pmu-io-voltage-domain"; 189 status = "disabled"; 190 }; 191 192 reboot-mode { 193 compatible = "syscon-reboot-mode"; 194 offset = <0x200>; 195 mode-bootloader = <BOOT_BL_DOWNLOAD>; 196 mode-charge = <BOOT_CHARGING>; 197 mode-fastboot = <BOOT_FASTBOOT>; 198 mode-loader = <BOOT_BL_DOWNLOAD>; 199 mode-normal = <BOOT_NORMAL>; 200 mode-recovery = <BOOT_RECOVERY>; 201 mode-ums = <BOOT_UMS>; 202 }; 203 204 pmu_pvtm: pmu-pvtm { 205 compatible = "rockchip,px30-pmu-pvtm"; 206 clocks = <&pmucru SCLK_PVTM_PMU>; 207 clock-names = "pmu"; 208 status = "disabled"; 209 }; 210 }; 211 212 uart0: serial@ff030000 { 213 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 214 reg = <0x0 0xff030000 0x0 0x100>; 215 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 217 clock-names = "baudclk", "apb_pclk"; 218 reg-shift = <2>; 219 reg-io-width = <4>; 220 dmas = <&dmac 0>, <&dmac 1>; 221 #dma-cells = <2>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 224 status = "disabled"; 225 }; 226 227 i2s0_8ch: i2s@ff060000 { 228 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 229 reg = <0x0 0xff060000 0x0 0x1000>; 230 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 232 clock-names = "i2s_clk", "i2s_hclk"; 233 dmas = <&dmac 16>, <&dmac 17>; 234 dma-names = "tx", "rx"; 235 status = "disabled"; 236 }; 237 238 i2s1_2ch: i2s@ff070000 { 239 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 240 reg = <0x0 0xff070000 0x0 0x1000>; 241 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 243 clock-names = "i2s_clk", "i2s_hclk"; 244 dmas = <&dmac 18>, <&dmac 19>; 245 dma-names = "tx", "rx"; 246 status = "disabled"; 247 }; 248 249 i2s2_2ch: i2s@ff080000 { 250 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 251 reg = <0x0 0xff080000 0x0 0x1000>; 252 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 254 clock-names = "i2s_clk", "i2s_hclk"; 255 dmas = <&dmac 20>, <&dmac 21>; 256 dma-names = "tx", "rx"; 257 status = "disabled"; 258 }; 259 260 pdm: pdm@ff0a0000 { 261 compatible = "rockchip,pdm"; 262 reg = <0x0 0xff0a0000 0x0 0x1000>; 263 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 264 clock-names = "pdm_clk", "pdm_hclk"; 265 dmas = <&dmac 24>; 266 dma-names = "rx"; 267 status = "disabled"; 268 }; 269 270 gic: interrupt-controller@ff131000 { 271 compatible = "arm,gic-400"; 272 #interrupt-cells = <3>; 273 #address-cells = <0>; 274 interrupt-controller; 275 reg = <0x0 0xff131000 0 0x1000>, 276 <0x0 0xff132000 0 0x2000>, 277 <0x0 0xff134000 0 0x2000>, 278 <0x0 0xff136000 0 0x2000>; 279 interrupts = <GIC_PPI 9 280 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 281 }; 282 283 grf: syscon@ff140000 { 284 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 285 reg = <0x0 0xff140000 0x0 0x1000>; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 289 io_domains: io-domains { 290 compatible = "rockchip,px30-io-voltage-domain"; 291 status = "disabled"; 292 }; 293 }; 294 295 core_grf: syscon@ff148000 { 296 compatible = "syscon", "simple-mfd"; 297 reg = <0x0 0xff148000 0x0 0x1000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 301 pvtm: pvtm { 302 compatible = "rockchip,px30-pvtm"; 303 clocks = <&cru SCLK_PVTM>; 304 clock-names = "core"; 305 status = "disabled"; 306 }; 307 }; 308 309 uart1: serial@ff158000 { 310 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 311 reg = <0x0 0xff158000 0x0 0x100>; 312 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 314 clock-names = "sclk_uart", "pclk_uart"; 315 reg-shift = <2>; 316 reg-io-width = <4>; 317 dmas = <&dmac 2>, <&dmac 3>; 318 #dma-cells = <2>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 321 status = "disabled"; 322 }; 323 324 uart2: serial@ff160000 { 325 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 326 reg = <0x0 0xff160000 0x0 0x100>; 327 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 329 clock-names = "baudclk", "apb_pclk"; 330 reg-shift = <2>; 331 reg-io-width = <4>; 332 dmas = <&dmac 4>, <&dmac 5>; 333 #dma-cells = <2>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&uart2m0_xfer>; 336 status = "disabled"; 337 }; 338 339 uart3: serial@ff168000 { 340 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 341 reg = <0x0 0xff168000 0x0 0x100>; 342 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 344 clock-names = "baudclk", "apb_pclk"; 345 reg-shift = <2>; 346 reg-io-width = <4>; 347 dmas = <&dmac 6>, <&dmac 7>; 348 #dma-cells = <2>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 351 status = "disabled"; 352 }; 353 354 uart4: serial@ff170000 { 355 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 356 reg = <0x0 0xff170000 0x0 0x100>; 357 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 359 clock-names = "baudclk", "apb_pclk"; 360 reg-shift = <2>; 361 reg-io-width = <4>; 362 dmas = <&dmac 8>, <&dmac 9>; 363 #dma-cells = <2>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 366 status = "disabled"; 367 }; 368 369 uart5: serial@ff178000 { 370 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 371 reg = <0x0 0xff178000 0x0 0x100>; 372 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 374 clock-names = "baudclk", "apb_pclk"; 375 reg-shift = <2>; 376 reg-io-width = <4>; 377 dmas = <&dmac 10>, <&dmac 11>; 378 #dma-cells = <2>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 381 status = "disabled"; 382 }; 383 384 i2c0: i2c@ff180000 { 385 compatible = "rockchip,rk3399-i2c"; 386 reg = <0x0 0xff180000 0x0 0x1000>; 387 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 388 clock-names = "i2c", "pclk"; 389 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&i2c0_xfer>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 i2c1: i2c@ff190000 { 398 compatible = "rockchip,rk3399-i2c"; 399 reg = <0x0 0xff190000 0x0 0x1000>; 400 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 401 clock-names = "i2c", "pclk"; 402 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&i2c1_xfer>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 410 i2c2: i2c@ff1a0000 { 411 compatible = "rockchip,rk3399-i2c"; 412 reg = <0x0 0xff1a0000 0x0 0x1000>; 413 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 414 clock-names = "i2c", "pclk"; 415 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&i2c2_xfer>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "disabled"; 421 }; 422 423 i2c3: i2c@ff1b0000 { 424 compatible = "rockchip,rk3399-i2c"; 425 reg = <0x0 0xff1b0000 0x0 0x1000>; 426 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 427 clock-names = "i2c", "pclk"; 428 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&i2c3_xfer>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 status = "disabled"; 434 }; 435 436 spi0: spi@ff1d0000 { 437 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 438 reg = <0x0 0xff1d0000 0x0 0x1000>; 439 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 443 clock-names = "spiclk", "apb_pclk"; 444 dmas = <&dmac 12>, <&dmac 13>; 445 #dma-cells = <2>; 446 dma-names = "tx", "rx"; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 449 status = "disabled"; 450 }; 451 452 spi1: spi@ff1d8000 { 453 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 454 reg = <0x0 0xff1d8000 0x0 0x1000>; 455 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 459 clock-names = "spiclk", "apb_pclk"; 460 dmas = <&dmac 14>, <&dmac 15>; 461 #dma-cells = <2>; 462 dma-names = "tx", "rx"; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 465 status = "disabled"; 466 }; 467 468 wdt: watchdog@ff1e0000 { 469 compatible = "snps,dw-wdt"; 470 reg = <0x0 0xff1e0000 0x0 0x100>; 471 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 472 status = "disabled"; 473 }; 474 475 pwm0: pwm@ff200000 { 476 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 477 reg = <0x0 0xff200000 0x0 0x10>; 478 #pwm-cells = <3>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pwm0_pin>; 481 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 482 clock-names = "pwm", "pclk"; 483 status = "disabled"; 484 }; 485 486 pwm1: pwm@ff200010 { 487 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 488 reg = <0x0 0xff200010 0x0 0x10>; 489 #pwm-cells = <3>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pwm1_pin>; 492 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 493 clock-names = "pwm", "pclk"; 494 status = "disabled"; 495 }; 496 497 pwm2: pwm@ff200020 { 498 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 499 reg = <0x0 0xff200020 0x0 0x10>; 500 #pwm-cells = <3>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&pwm2_pin>; 503 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 504 clock-names = "pwm", "pclk"; 505 status = "disabled"; 506 }; 507 508 pwm3: pwm@ff200030 { 509 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 510 reg = <0x0 0xff200030 0x0 0x10>; 511 #pwm-cells = <3>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&pwm3_pin>; 514 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 515 clock-names = "pwm", "pclk"; 516 status = "disabled"; 517 }; 518 519 pwm4: pwm@ff208000 { 520 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 521 reg = <0x0 0xff208000 0x0 0x10>; 522 #pwm-cells = <3>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&pwm4_pin>; 525 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 526 clock-names = "pwm", "pclk"; 527 status = "disabled"; 528 }; 529 530 pwm5: pwm@ff208010 { 531 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 532 reg = <0x0 0xff208010 0x0 0x10>; 533 #pwm-cells = <3>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&pwm5_pin>; 536 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 537 clock-names = "pwm", "pclk"; 538 status = "disabled"; 539 }; 540 541 pwm6: pwm@ff208020 { 542 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 543 reg = <0x0 0xff208020 0x0 0x10>; 544 #pwm-cells = <3>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pwm6_pin>; 547 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 548 clock-names = "pwm", "pclk"; 549 status = "disabled"; 550 }; 551 552 pwm7: pwm@ff208030 { 553 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 554 reg = <0x0 0xff208030 0x0 0x10>; 555 #pwm-cells = <3>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pwm7_pin>; 558 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 559 clock-names = "pwm", "pclk"; 560 status = "disabled"; 561 }; 562 563 amba { 564 compatible = "simple-bus"; 565 #address-cells = <2>; 566 #size-cells = <2>; 567 ranges; 568 569 dmac: dmac@ff240000 { 570 compatible = "arm,pl330", "arm,primecell"; 571 reg = <0x0 0xff240000 0x0 0x4000>; 572 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cru ACLK_DMAC>; 575 clock-names = "apb_pclk"; 576 #dma-cells = <1>; 577 peripherals-req-type-burst; 578 }; 579 }; 580 581 tsadc: tsadc@ff280000 { 582 compatible = "rockchip,px30-tsadc"; 583 reg = <0x0 0xff280000 0x0 0x100>; 584 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 585 rockchip,grf = <&grf>; 586 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 587 clock-names = "tsadc", "apb_pclk"; 588 assigned-clocks = <&cru SCLK_TSADC>; 589 assigned-clock-rates = <50000>; 590 resets = <&cru SRST_TSADC_P>; 591 reset-names = "tsadc-apb"; 592 pinctrl-names = "init", "default", "sleep"; 593 pinctrl-0 = <&tsadc_otp_gpio>; 594 pinctrl-1 = <&tsadc_otp_out>; 595 pinctrl-2 = <&tsadc_otp_gpio>; 596 #thermal-sensor-cells = <1>; 597 rockchip,hw-tshut-temp = <100000>; 598 status = "disabled"; 599 }; 600 601 saradc: saradc@ff288000 { 602 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 603 reg = <0x0 0xff288000 0x0 0x100>; 604 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 605 #io-channel-cells = <1>; 606 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 607 clock-names = "saradc", "apb_pclk"; 608 resets = <&cru SRST_SARADC_P>; 609 reset-names = "saradc-apb"; 610 status = "disabled"; 611 }; 612 613 cru: clock-controller@ff2b0000 { 614 compatible = "rockchip,px30-cru"; 615 reg = <0x0 0xff2b0000 0x0 0x9000>; 616 rockchip,grf = <&grf>; 617 #clock-cells = <1>; 618 #reset-cells = <1>; 619 620 assigned-clocks = 621 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 622 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 623 <&cru ARMCLK>; 624 assigned-clock-rates = 625 <1608000000>, <1416000000>, 626 <1188000000>, <1188000000>, 627 <816000000>; 628 }; 629 630 pmucru: pmu-clock-controller@ff2bc000 { 631 compatible = "rockchip,px30-pmucru"; 632 reg = <0x0 0xff2bc000 0x0 0x1000>; 633 rockchip,grf = <&grf>; 634 #clock-cells = <1>; 635 #reset-cells = <1>; 636 637 assigned-clocks = 638 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 639 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 640 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 641 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 642 assigned-clock-rates = 643 <1200000000>, <100000000>, 644 <26000000>, <300000000>, 645 <300000000>, <150000000>, 646 <150000000>, <75000000>; 647 }; 648 649 usb2phy_grf: syscon@ff2c0000 { 650 compatible = "rockchip,px30-usb2phy-grf", "syscon", 651 "simple-mfd"; 652 reg = <0x0 0xff2c0000 0x0 0x10000>; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 656 u2phy: usb2-phy@100 { 657 compatible = "rockchip,px30-usb2phy", 658 "rockchip,rk3328-usb2phy"; 659 reg = <0x100 0x10>; 660 clocks = <&pmucru SCLK_USBPHY_REF>; 661 clock-names = "phyclk"; 662 #clock-cells = <0>; 663 assigned-clocks = <&cru USB480M>; 664 assigned-clock-parents = <&u2phy>; 665 clock-output-names = "usb480m_phy"; 666 status = "disabled"; 667 668 u2phy_host: host-port { 669 #phy-cells = <0>; 670 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 671 interrupt-names = "linestate"; 672 status = "disabled"; 673 }; 674 675 u2phy_otg: otg-port { 676 #phy-cells = <0>; 677 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 680 interrupt-names = "otg-bvalid", "otg-id", 681 "linestate"; 682 status = "disabled"; 683 }; 684 }; 685 }; 686 687 mipi_dphy: mipi-dphy@ff2e0000 { 688 compatible = "rockchip,px30-mipi-dphy"; 689 reg = <0x0 0xff2e0000 0x0 0x10000>; 690 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 691 clock-names = "ref", "pclk"; 692 clock-output-names = "mipi_dphy_pll"; 693 #clock-cells = <0>; 694 resets = <&cru SRST_MIPIDSIPHY_P>; 695 reset-names = "apb"; 696 power-domains = <&power PX30_PD_VO>; 697 #phy-cells = <0>; 698 rockchip,grf = <&grf>; 699 status = "disabled"; 700 }; 701 702 lvds: lvds@ff2e0000 { 703 compatible = "rockchip,px30-lvds"; 704 reg = <0x0 0xff2e0000 0x0 0x100>, <0x0 0xff2e0100 0x0 0x100>; 705 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 706 clocks = <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 707 clock-names = "pclk_lvds", "pclk_lvds_ctl"; 708 power-domains = <&power PX30_PD_VO>; 709 rockchip,grf = <&grf>; 710 status = "disabled"; 711 712 ports { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 716 port@0 { 717 reg = <0>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 lvds_in_vopl: endpoint@0 { 722 reg = <0>; 723 remote-endpoint = <&vopl_out_lvds>; 724 }; 725 726 lvds_in_vopb: endpoint@1 { 727 reg = <1>; 728 remote-endpoint = <&vopb_out_lvds>; 729 }; 730 }; 731 }; 732 }; 733 734 usb20_otg: usb@ff300000 { 735 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 736 "snps,dwc2"; 737 reg = <0x0 0xff300000 0x0 0x40000>; 738 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cru HCLK_OTG>; 740 clock-names = "otg"; 741 dr_mode = "otg"; 742 g-np-tx-fifo-size = <16>; 743 g-rx-fifo-size = <275>; 744 g-tx-fifo-size = <256 128 128 64 64 32>; 745 g-use-dma; 746 phys = <&u2phy_otg>; 747 phy-names = "usb2-phy"; 748 status = "disabled"; 749 }; 750 751 usb_host0_ehci: usb@ff340000 { 752 compatible = "generic-ehci"; 753 reg = <0x0 0xff340000 0x0 0x10000>; 754 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 756 <&u2phy>; 757 clock-names = "usbhost", "arbiter", "utmi"; 758 phys = <&u2phy_host>; 759 phy-names = "usb"; 760 status = "disabled"; 761 }; 762 763 usb_host0_ohci: usb@ff350000 { 764 compatible = "generic-ohci"; 765 reg = <0x0 0xff350000 0x0 0x10000>; 766 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 768 <&u2phy>; 769 clock-names = "usbhost", "arbiter", "utmi"; 770 phys = <&u2phy_host>; 771 phy-names = "usb"; 772 }; 773 774 gmac: ethernet@ff360000 { 775 compatible = "rockchip,px30-gmac"; 776 reg = <0x0 0xff360000 0x0 0x10000>; 777 rockchip,grf = <&grf>; 778 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 779 interrupt-names = "macirq"; 780 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 781 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 782 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 783 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 784 clock-names = "stmmaceth", "mac_clk_rx", 785 "mac_clk_tx", "clk_mac_ref", 786 "clk_mac_refout", "aclk_mac", 787 "pclk_mac", "clk_mac_speed"; 788 phy-mode = "rmii"; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&rmii_pins>; 791 resets = <&cru SRST_GMAC_A>; 792 reset-names = "stmmaceth"; 793 power-domains = <&power PX30_PD_GMAC>; 794 status = "disabled"; 795 }; 796 797 sdmmc: dwmmc@ff370000 { 798 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 799 reg = <0x0 0xff370000 0x0 0x4000>; 800 max-frequency = <150000000>; 801 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 802 clock-names = "biu", "ciu"; 803 fifo-depth = <0x100>; 804 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 805 status = "disabled"; 806 }; 807 808 sdio: dwmmc@ff380000 { 809 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 810 reg = <0x0 0xff380000 0x0 0x4000>; 811 max-frequency = <150000000>; 812 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 813 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 814 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 815 fifo-depth = <0x100>; 816 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 817 status = "disabled"; 818 }; 819 820 emmc: dwmmc@ff390000 { 821 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 822 reg = <0x0 0xff390000 0x0 0x4000>; 823 max-frequency = <150000000>; 824 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 825 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 826 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 827 fifo-depth = <0x100>; 828 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 829 status = "disabled"; 830 }; 831 832 nandc0: nandc@ff3b0000 { 833 compatible = "rockchip,rk-nandc"; 834 reg = <0x0 0xff3b0000 0x0 0x4000>; 835 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 836 nandc_id = <0>; 837 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 838 clock-names = "clk_nandc", "hclk_nandc"; 839 status = "disabled"; 840 }; 841 842 gpu: gpu@ff400000 { 843 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 844 reg = <0x0 0xff400000 0x0 0x4000>; 845 846 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-names = "GPU", "MMU", "JOB"; 850 851 clocks = <&cru ACLK_GPU>; 852 clock-names = "clk_mali"; 853 854 status = "disabled"; 855 }; 856 857 hevc: hevc_service@ff440000 { 858 compatible = "rockchip,hevc_sub"; 859 iommu_enabled = <1>; 860 reg = <0x0 0xff440000 0x0 0x400>; 861 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 862 interrupt-names = "irq_dec"; 863 dev_mode = <1>; 864 iommus = <&hevc_mmu>; 865 name = "hevc_service"; 866 allocator = <1>; 867 }; 868 869 vpu: vpu_service@ff442000 { 870 compatible = "rockchip,vpu_sub"; 871 iommu_enabled = <1>; 872 reg = <0x0 0xff442000 0x0 0x800>; 873 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "irq_enc", "irq_dec"; 876 dev_mode = <0>; 877 iommus = <&vpu_mmu>; 878 name = "vpu_service"; 879 allocator = <1>; 880 }; 881 882 vpu_combo: vpu_combo { 883 compatible = "rockchip,vpu_combo"; 884 subcnt = <2>; 885 rockchip,grf = <&grf>; 886 rockchip,sub = <&vpu>, <&hevc>; 887 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 888 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 889 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 890 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 891 <&cru SRST_VPU_CORE>; 892 reset-names = "video_a", "video_h", "niu_a", "niu_h", 893 "video_core"; 894 mode_bit = <15>; 895 mode_ctrl = <0x410>; 896 name = "vpu_combo"; 897 status = "disabled"; 898 }; 899 900 hevc_mmu: iommu@ff440440 { 901 compatible = "rockchip,iommu"; 902 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 903 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-names = "hevc_mmu"; 905 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 906 clock-names = "aclk", "hclk"; 907 #iommu-cells = <0>; 908 }; 909 910 vpu_mmu: iommu@ff442800 { 911 compatible = "rockchip,iommu"; 912 reg = <0x0 0xff442800 0x0 0x100>; 913 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "vpu_mmu"; 915 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 916 clock-names = "aclk", "hclk"; 917 #iommu-cells = <0>; 918 }; 919 920 dsi: dsi@ff450000 { 921 compatible = "rockchip,px30-mipi-dsi"; 922 reg = <0x0 0xff450000 0x0 0x10000>; 923 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&cru PCLK_MIPI_DSI>, <&mipi_dphy>; 925 clock-names = "pclk", "hs_clk"; 926 resets = <&cru SRST_MIPIDSI_HOST_P>; 927 reset-names = "apb"; 928 phys = <&mipi_dphy>; 929 phy-names = "mipi_dphy"; 930 power-domains = <&power PX30_PD_VO>; 931 rockchip,grf = <&grf>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 936 ports { 937 port { 938 #address-cells = <1>; 939 #size-cells = <0>; 940 941 dsi_in_vopl: endpoint@0 { 942 reg = <0>; 943 remote-endpoint = <&vopl_out_dsi>; 944 }; 945 946 dsi_in_vopb: endpoint@1 { 947 reg = <1>; 948 remote-endpoint = <&vopb_out_dsi>; 949 }; 950 }; 951 }; 952 }; 953 954 vopb: vop@ff460000 { 955 compatible = "rockchip,px30-vop-big"; 956 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 957 reg-names = "regs", "gamma_lut"; 958 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 960 <&cru HCLK_VOPB>; 961 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 962 iommus = <&vopb_mmu>; 963 status = "disabled"; 964 965 vopb_out: port { 966 #address-cells = <1>; 967 #size-cells = <0>; 968 969 vopb_out_lvds: endpoint@0 { 970 reg = <0>; 971 remote-endpoint = <&lvds_in_vopb>; 972 }; 973 974 vopb_out_dsi: endpoint@1 { 975 reg = <1>; 976 remote-endpoint = <&dsi_in_vopb>; 977 }; 978 }; 979 }; 980 981 vopb_mmu: iommu@ff460f00 { 982 compatible = "rockchip,iommu"; 983 reg = <0x0 0xff460f00 0x0 0x100>; 984 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 985 interrupt-names = "vopb_mmu"; 986 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 987 clock-names = "aclk", "hclk"; 988 #iommu-cells = <0>; 989 status = "disabled"; 990 }; 991 992 vopl: vop@ff470000 { 993 compatible = "rockchip,px30-vop-lit"; 994 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 995 reg-names = "regs", "gamma_lut"; 996 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 998 <&cru HCLK_VOPL>; 999 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1000 iommus = <&vopl_mmu>; 1001 status = "disabled"; 1002 1003 vopl_out: port { 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 1007 vopl_out_lvds: endpoint@0 { 1008 reg = <0>; 1009 remote-endpoint = <&lvds_in_vopl>; 1010 }; 1011 1012 vopl_out_dsi: endpoint@1 { 1013 reg = <1>; 1014 remote-endpoint = <&dsi_in_vopl>; 1015 }; 1016 }; 1017 }; 1018 1019 vopl_mmu: iommu@ff470f00 { 1020 compatible = "rockchip,iommu"; 1021 reg = <0x0 0xff470f00 0x0 0x100>; 1022 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1023 interrupt-names = "vopl_mmu"; 1024 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1025 clock-names = "aclk", "hclk"; 1026 #iommu-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 rk_rga: rk_rga@ff480000 { 1031 compatible = "rockchip,rga2"; 1032 //dev_mode = <1>; 1033 reg = <0x0 0xff480000 0x0 0x1000>; 1034 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1036 clock-names = "aclk_rga", "hclk_rga"; 1037 dma-coherent; 1038 status = "disabled"; 1039 }; 1040 1041 cif: cif@ff490000 { 1042 compatible = "rockchip,cif"; 1043 reg = <0x0 0xff490000 0x0 0x200>; 1044 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1046 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1047 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1048 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1049 pinctrl-names = "cif_pin_all"; 1050 pinctrl-0 = <&dvp_d2d9_m0>; 1051 status = "disabled"; 1052 }; 1053 1054 vip_mmu: iommu@ff490800{ 1055 compatible = "rockchip,iommu"; 1056 reg = <0x0 0xff490800 0x0 0x100>; 1057 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupt-names = "vip_mmu"; 1059 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1060 clock-names = "aclk", "hclk"; 1061 rk_iommu,disable_reset_quirk; 1062 #iommu-cells = <0>; 1063 status = "disabled"; 1064 }; 1065 1066 rk_isp: rk_isp@ff4a0000 { 1067 compatible = "rockchip,px30-isp", "rockchip,isp"; 1068 reg = <0x0 0xff4a0000 0x0 0x4000>; 1069 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1071 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1072 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1073 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1074 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1075 reset-names = "rst_isp", "rst_mipicsiphy"; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&cif_clkout_m0>; 1078 rockchip,isp,mipiphy = <0>; 1079 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1080 rockchip,grf = <&grf>; 1081 rockchip,cru = <&cru>; 1082 rockchip,isp,iommu-enable = <1>; 1083 iommus = <&isp_mmu>; 1084 status = "disabled"; 1085 }; 1086 1087 isp_mmu: iommu@ff4a8000 { 1088 compatible = "rockchip,iommu"; 1089 reg = <0x0 0xff4a8000 0x0 0x100>; 1090 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1091 interrupt-names = "isp_mmu"; 1092 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1093 clock-names = "aclk", "hclk"; 1094 rk_iommu,disable_reset_quirk; 1095 #iommu-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 qos_gmac: qos@ff518000 { 1100 compatible = "syscon"; 1101 reg = <0x0 0xff518000 0x0 0x20>; 1102 }; 1103 1104 qos_gpu: qos@ff520000 { 1105 compatible = "syscon"; 1106 reg = <0x0 0xff520000 0x0 0x20>; 1107 }; 1108 1109 qos_sdmmc: qos@ff52c000 { 1110 compatible = "syscon"; 1111 reg = <0x0 0xff52c000 0x0 0x20>; 1112 }; 1113 1114 qos_emmc: qos@ff538000 { 1115 compatible = "syscon"; 1116 reg = <0x0 0xff538000 0x0 0x20>; 1117 }; 1118 1119 qos_nand: qos@ff538080 { 1120 compatible = "syscon"; 1121 reg = <0x0 0xff538080 0x0 0x20>; 1122 }; 1123 1124 qos_sdio: qos@ff538100 { 1125 compatible = "syscon"; 1126 reg = <0x0 0xff538100 0x0 0x20>; 1127 }; 1128 1129 qos_sfc: qos@ff538180 { 1130 compatible = "syscon"; 1131 reg = <0x0 0xff538180 0x0 0x20>; 1132 }; 1133 1134 qos_usb_host: qos@ff540000 { 1135 compatible = "syscon"; 1136 reg = <0x0 0xff540000 0x0 0x20>; 1137 }; 1138 1139 qos_usb_otg: qos@ff540080 { 1140 compatible = "syscon"; 1141 reg = <0x0 0xff540080 0x0 0x20>; 1142 }; 1143 1144 qos_isp_128: qos@ff548000 { 1145 compatible = "syscon"; 1146 reg = <0x0 0xff548000 0x0 0x20>; 1147 }; 1148 1149 qos_isp_rd: qos@ff548080 { 1150 compatible = "syscon"; 1151 reg = <0x0 0xff548080 0x0 0x20>; 1152 }; 1153 1154 qos_isp_wr: qos@ff548100 { 1155 compatible = "syscon"; 1156 reg = <0x0 0xff548100 0x0 0x20>; 1157 }; 1158 1159 qos_isp_m1: qos@ff548180 { 1160 compatible = "syscon"; 1161 reg = <0x0 0xff548180 0x0 0x20>; 1162 }; 1163 1164 qos_vip: qos@ff548200 { 1165 compatible = "syscon"; 1166 reg = <0x0 0xff548200 0x0 0x20>; 1167 }; 1168 1169 qos_rga_rd: qos@ff550000 { 1170 compatible = "syscon"; 1171 reg = <0x0 0xff550000 0x0 0x20>; 1172 }; 1173 1174 qos_rga_wr: qos@ff550080 { 1175 compatible = "syscon"; 1176 reg = <0x0 0xff550080 0x0 0x20>; 1177 }; 1178 1179 qos_vop_m0: qos@ff550100 { 1180 compatible = "syscon"; 1181 reg = <0x0 0xff550100 0x0 0x20>; 1182 }; 1183 1184 qos_vop_m1: qos@ff550180 { 1185 compatible = "syscon"; 1186 reg = <0x0 0xff550180 0x0 0x20>; 1187 }; 1188 1189 qos_vpu: qos@ff558000 { 1190 compatible = "syscon"; 1191 reg = <0x0 0xff558000 0x0 0x20>; 1192 }; 1193 1194 qos_vpu_r128: qos@ff558080 { 1195 compatible = "syscon"; 1196 reg = <0x0 0xff558080 0x0 0x20>; 1197 }; 1198 1199 pinctrl: pinctrl { 1200 compatible = "rockchip,px30-pinctrl"; 1201 rockchip,grf = <&grf>; 1202 rockchip,pmu = <&pmugrf>; 1203 #address-cells = <2>; 1204 #size-cells = <2>; 1205 ranges; 1206 1207 gpio0: gpio0@ff040000 { 1208 compatible = "rockchip,gpio-bank"; 1209 reg = <0x0 0xff040000 0x0 0x100>; 1210 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1211 clocks = <&cru PCLK_GPIO0_PMU>; 1212 gpio-controller; 1213 #gpio-cells = <2>; 1214 1215 interrupt-controller; 1216 #interrupt-cells = <2>; 1217 }; 1218 1219 gpio1: gpio1@ff250000 { 1220 compatible = "rockchip,gpio-bank"; 1221 reg = <0x0 0xff250000 0x0 0x100>; 1222 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&cru PCLK_GPIO1>; 1224 gpio-controller; 1225 #gpio-cells = <2>; 1226 1227 interrupt-controller; 1228 #interrupt-cells = <2>; 1229 }; 1230 1231 gpio2: gpio2@ff260000 { 1232 compatible = "rockchip,gpio-bank"; 1233 reg = <0x0 0xff260000 0x0 0x100>; 1234 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&cru PCLK_GPIO2>; 1236 gpio-controller; 1237 #gpio-cells = <2>; 1238 1239 interrupt-controller; 1240 #interrupt-cells = <2>; 1241 }; 1242 1243 gpio3: gpio3@ff270000 { 1244 compatible = "rockchip,gpio-bank"; 1245 reg = <0x0 0xff270000 0x0 0x100>; 1246 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&cru PCLK_GPIO3>; 1248 gpio-controller; 1249 #gpio-cells = <2>; 1250 1251 interrupt-controller; 1252 #interrupt-cells = <2>; 1253 }; 1254 1255 pcfg_pull_up: pcfg-pull-up { 1256 bias-pull-up; 1257 }; 1258 1259 pcfg_pull_down: pcfg-pull-down { 1260 bias-pull-down; 1261 }; 1262 1263 pcfg_pull_none: pcfg-pull-none { 1264 bias-disable; 1265 }; 1266 1267 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1268 bias-disable; 1269 drive-strength = <2>; 1270 }; 1271 1272 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1273 bias-pull-up; 1274 drive-strength = <2>; 1275 }; 1276 1277 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1278 bias-pull-up; 1279 drive-strength = <4>; 1280 }; 1281 1282 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1283 bias-disable; 1284 drive-strength = <4>; 1285 }; 1286 1287 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1288 bias-pull-down; 1289 drive-strength = <4>; 1290 }; 1291 1292 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1293 bias-disable; 1294 drive-strength = <8>; 1295 }; 1296 1297 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1298 bias-pull-up; 1299 drive-strength = <8>; 1300 }; 1301 1302 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1303 bias-disable; 1304 drive-strength = <12>; 1305 }; 1306 1307 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1308 bias-pull-up; 1309 drive-strength = <12>; 1310 }; 1311 1312 pcfg_pull_none_smt: pcfg-pull-none-smt { 1313 bias-disable; 1314 input-schmitt-enable; 1315 }; 1316 1317 pcfg_output_high: pcfg-output-high { 1318 output-high; 1319 }; 1320 1321 pcfg_output_low: pcfg-output-low { 1322 output-low; 1323 }; 1324 1325 pcfg_input_high: pcfg-input-high { 1326 bias-pull-up; 1327 input-enable; 1328 }; 1329 1330 pcfg_input: pcfg-input { 1331 input-enable; 1332 }; 1333 1334 i2c0 { 1335 i2c0_xfer: i2c0-xfer { 1336 rockchip,pins = 1337 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1338 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1339 }; 1340 }; 1341 1342 i2c1 { 1343 i2c1_xfer: i2c1-xfer { 1344 rockchip,pins = 1345 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1346 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1347 }; 1348 }; 1349 1350 i2c2 { 1351 i2c2_xfer: i2c2-xfer { 1352 rockchip,pins = 1353 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1354 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1355 }; 1356 }; 1357 1358 i2c3 { 1359 i2c3_xfer: i2c3-xfer { 1360 rockchip,pins = 1361 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1362 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1363 }; 1364 }; 1365 1366 tsadc { 1367 tsadc_otp_gpio: tsadc-otp-gpio { 1368 rockchip,pins = 1369 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1370 }; 1371 1372 tsadc_otp_out: tsadc-otp-out { 1373 rockchip,pins = 1374 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1375 }; 1376 }; 1377 1378 uart0 { 1379 uart0_xfer: uart0-xfer { 1380 rockchip,pins = 1381 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1382 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1383 }; 1384 1385 uart0_cts: uart0-cts { 1386 rockchip,pins = 1387 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1388 }; 1389 1390 uart0_rts: uart0-rts { 1391 rockchip,pins = 1392 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1393 }; 1394 1395 uart0_rts_gpio: uart0-rts-gpio { 1396 rockchip,pins = 1397 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1398 }; 1399 }; 1400 1401 uart1 { 1402 uart1_xfer: uart1-xfer { 1403 rockchip,pins = 1404 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1405 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1406 }; 1407 1408 uart1_cts: uart1-cts { 1409 rockchip,pins = 1410 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1411 }; 1412 1413 uart1_rts: uart1-rts { 1414 rockchip,pins = 1415 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1416 }; 1417 1418 uart1_rts_gpio: uart1-rts-gpio { 1419 rockchip,pins = 1420 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1421 }; 1422 }; 1423 1424 uart2-m0 { 1425 uart2m0_xfer: uart2m0-xfer { 1426 rockchip,pins = 1427 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1428 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1429 }; 1430 }; 1431 1432 uart2-m1 { 1433 uart2m1_xfer: uart2m1-xfer { 1434 rockchip,pins = 1435 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1436 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1437 }; 1438 }; 1439 1440 uart3-m0 { 1441 uart3m0_xfer: uart3m0-xfer { 1442 rockchip,pins = 1443 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1444 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1445 }; 1446 1447 uart3m0_cts: uart3m0-cts { 1448 rockchip,pins = 1449 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1450 }; 1451 1452 uart3m0_rts: uart3m0-rts { 1453 rockchip,pins = 1454 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1455 }; 1456 1457 uart3m0_rts_gpio: uart3m0-rts-gpio { 1458 rockchip,pins = 1459 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1460 }; 1461 }; 1462 1463 uart3-m1 { 1464 uart3m1_xfer: uart3m1-xfer { 1465 rockchip,pins = 1466 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1467 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1468 }; 1469 1470 uart3m1_cts: uart3m1-cts { 1471 rockchip,pins = 1472 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1473 }; 1474 1475 uart3m1_rts: uart3m1-rts { 1476 rockchip,pins = 1477 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1478 }; 1479 1480 uart3m1_rts_gpio: uart3m1-rts-gpio { 1481 rockchip,pins = 1482 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1483 }; 1484 }; 1485 1486 uart4 { 1487 1488 uart4_xfer: uart4-xfer { 1489 rockchip,pins = 1490 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1491 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1492 }; 1493 1494 uart4_cts: uart4-cts { 1495 rockchip,pins = 1496 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1497 1498 }; 1499 1500 uart4_rts: uart4-rts { 1501 rockchip,pins = 1502 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1503 }; 1504 }; 1505 1506 uart5 { 1507 1508 uart5_xfer: uart5-xfer { 1509 rockchip,pins = 1510 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1511 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1512 }; 1513 1514 uart5_cts: uart5-cts { 1515 rockchip,pins = 1516 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1517 1518 }; 1519 1520 uart5_rts: uart5-rts { 1521 rockchip,pins = 1522 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1523 }; 1524 }; 1525 1526 spi0 { 1527 spi0_clk: spi0-clk { 1528 rockchip,pins = 1529 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1530 }; 1531 1532 spi0_csn: spi0-csn { 1533 rockchip,pins = 1534 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1535 }; 1536 1537 spi0_miso: spi0-miso { 1538 rockchip,pins = 1539 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1540 }; 1541 1542 spi0_mosi: spi0-mosi { 1543 rockchip,pins = 1544 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1545 }; 1546 }; 1547 1548 spi1 { 1549 spi1_clk: spi1-clk { 1550 rockchip,pins = 1551 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1552 }; 1553 1554 spi1_csn: spi1-csn { 1555 rockchip,pins = 1556 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1557 }; 1558 1559 spi1_miso: spi1-miso { 1560 rockchip,pins = 1561 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1562 }; 1563 1564 spi1_mosi: spi1-mosi { 1565 rockchip,pins = 1566 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1567 }; 1568 }; 1569 1570 pdm { 1571 pdm_clk0m0: pdm-clk0m0 { 1572 rockchip,pins = 1573 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1574 }; 1575 1576 pdm_clk0m1: pdm-clk0m1 { 1577 rockchip,pins = 1578 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1579 }; 1580 1581 pdm_clk1: pdm-clk1 { 1582 rockchip,pins = 1583 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1584 }; 1585 1586 pdm_sdi0m0: pdm-sdi0m0 { 1587 rockchip,pins = 1588 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1589 }; 1590 1591 pdm_sdi0m1: pdm-sdi0m1 { 1592 rockchip,pins = 1593 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1594 }; 1595 1596 pdm_sdi1: pdm-sdi1 { 1597 rockchip,pins = 1598 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1599 }; 1600 1601 pdm_sdi2: pdm-sdi2 { 1602 rockchip,pins = 1603 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1604 }; 1605 1606 pdm_sdi3: pdm-sdi3 { 1607 rockchip,pins = 1608 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1609 }; 1610 1611 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1612 rockchip,pins = 1613 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1614 }; 1615 1616 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1617 rockchip,pins = 1618 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1619 }; 1620 1621 pdm_clk1_sleep: pdm-clk1-sleep { 1622 rockchip,pins = 1623 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1624 }; 1625 1626 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1627 rockchip,pins = 1628 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1629 }; 1630 1631 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1632 rockchip,pins = 1633 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1634 }; 1635 1636 pdm_sdi1_sleep: pdm-sdi1-sleep { 1637 rockchip,pins = 1638 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1639 }; 1640 1641 pdm_sdi2_sleep: pdm-sdi2-sleep { 1642 rockchip,pins = 1643 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1644 }; 1645 1646 pdm_sdi3_sleep: pdm-sdi3-sleep { 1647 rockchip,pins = 1648 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1649 }; 1650 }; 1651 1652 i2s0 { 1653 i2s0_8ch_mclk: i2s0-8ch-mclk { 1654 rockchip,pins = 1655 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1656 }; 1657 1658 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1659 rockchip,pins = 1660 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1661 }; 1662 1663 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1664 rockchip,pins = 1665 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1666 }; 1667 1668 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1669 rockchip,pins = 1670 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1671 }; 1672 1673 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1674 rockchip,pins = 1675 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1676 }; 1677 1678 i2s0_8ch_sdo: i2s0-8ch-sdo { 1679 rockchip,pins = 1680 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1681 }; 1682 1683 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1684 rockchip,pins = 1685 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1686 }; 1687 1688 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1689 rockchip,pins = 1690 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1691 }; 1692 1693 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1694 rockchip,pins = 1695 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1696 }; 1697 1698 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1699 rockchip,pins = 1700 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1701 }; 1702 1703 i2s0_8ch_sdi: i2s0-8ch-sdi { 1704 rockchip,pins = 1705 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1706 }; 1707 1708 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1709 rockchip,pins = 1710 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1711 }; 1712 1713 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1714 rockchip,pins = 1715 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1716 }; 1717 1718 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1719 rockchip,pins = 1720 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1721 }; 1722 1723 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1724 rockchip,pins = 1725 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1726 }; 1727 }; 1728 1729 i2s1 { 1730 i2s1_2ch_mclk: i2s1-2ch-mclk { 1731 rockchip,pins = 1732 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1733 }; 1734 1735 i2s1_2ch_sclk: i2s1-2ch-sclk { 1736 rockchip,pins = 1737 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1738 }; 1739 1740 i2s1_2ch_lrck: i2s1-2ch-lrck { 1741 rockchip,pins = 1742 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1743 }; 1744 1745 i2s1_2ch_sdi: i2s1-2ch-sdi { 1746 rockchip,pins = 1747 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1748 }; 1749 1750 i2s1_2ch_sdo: i2s1-2ch-sdo { 1751 rockchip,pins = 1752 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1753 }; 1754 }; 1755 1756 i2s2 { 1757 i2s2_2ch_mclk: i2s2-2ch-mclk { 1758 rockchip,pins = 1759 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1760 }; 1761 1762 i2s2_2ch_sclk: i2s2-2ch-sclk { 1763 rockchip,pins = 1764 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1765 }; 1766 1767 i2s2_2ch_lrck: i2s2-2ch-lrck { 1768 rockchip,pins = 1769 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1770 }; 1771 1772 i2s2_2ch_sdi: i2s2-2ch-sdi { 1773 rockchip,pins = 1774 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1775 }; 1776 1777 i2s2_2ch_sdo: i2s2-2ch-sdo { 1778 rockchip,pins = 1779 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1780 }; 1781 }; 1782 1783 sdmmc0 { 1784 sdmmc0_clk: sdmmc0-clk { 1785 rockchip,pins = 1786 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1787 }; 1788 1789 sdmmc0_cmd: sdmmc0-cmd { 1790 rockchip,pins = 1791 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1792 }; 1793 1794 sdmmc0_bus1: sdmmc0-bus1 { 1795 rockchip,pins = 1796 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_4ma>; 1797 }; 1798 1799 sdmmc0_bus4: sdmmc0-bus4 { 1800 rockchip,pins = 1801 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1802 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_4ma>, 1803 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_4ma>, 1804 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1805 }; 1806 1807 sdmmc0_gpio: sdmmc0-gpio { 1808 rockchip,pins = 1809 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1810 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1811 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1812 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1813 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1814 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1815 }; 1816 }; 1817 1818 sdmmc1 { 1819 sdmmc1_clk: sdmmc1-clk { 1820 rockchip,pins = 1821 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none_8ma>; 1822 }; 1823 1824 sdmmc1_cmd: sdmmc1-cmd { 1825 rockchip,pins = 1826 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up_8ma>; 1827 }; 1828 1829 sdmmc1_bus1: sdmmc1-bus1 { 1830 rockchip,pins = 1831 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up_8ma>; 1832 }; 1833 1834 sdmmc1_bus4: sdmmc1-bus4 { 1835 rockchip,pins = 1836 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up_8ma>, 1837 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up_8ma>, 1838 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up_8ma>, 1839 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up_8ma>; 1840 }; 1841 1842 sdmmc1_gpio: sdmmc1-gpio { 1843 rockchip,pins = 1844 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1845 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1846 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1847 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1848 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1849 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1850 }; 1851 }; 1852 1853 emmc { 1854 emmc_clk: emmc-clk { 1855 rockchip,pins = 1856 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1857 }; 1858 1859 emmc_cmd: emmc-cmd { 1860 rockchip,pins = 1861 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1862 }; 1863 1864 emmc_pwren: emmc-pwren { 1865 rockchip,pins = 1866 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1867 }; 1868 1869 emmc_rstnout: emmc-rstnout { 1870 rockchip,pins = 1871 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1872 }; 1873 1874 emmc_bus1: emmc-bus1 { 1875 rockchip,pins = 1876 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1877 }; 1878 1879 emmc_bus4: emmc-bus4 { 1880 rockchip,pins = 1881 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1882 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1883 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1884 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1885 }; 1886 1887 emmc_bus8: emmc-bus8 { 1888 rockchip,pins = 1889 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1890 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1891 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1892 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1893 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1894 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1895 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1896 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1897 }; 1898 }; 1899 1900 flash { 1901 flash_cs0: flash-cs0 { 1902 rockchip,pins = 1903 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1904 }; 1905 1906 flash_rdy: flash-rdy { 1907 rockchip,pins = 1908 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1909 }; 1910 1911 flash_dqs: flash-dqs { 1912 rockchip,pins = 1913 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1914 }; 1915 1916 flash_ale: flash-ale { 1917 rockchip,pins = 1918 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1919 }; 1920 1921 flash_cle: flash-cle { 1922 rockchip,pins = 1923 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1924 }; 1925 1926 flash_wrn: flash-wrn { 1927 rockchip,pins = 1928 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1929 }; 1930 1931 flash_csl: flash-csl { 1932 rockchip,pins = 1933 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 1934 }; 1935 1936 flash_rdn: flash-rdn { 1937 rockchip,pins = 1938 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 1939 }; 1940 1941 flash_bus8: flash-bus8 { 1942 rockchip,pins = 1943 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 1944 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 1945 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 1946 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 1947 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 1948 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 1949 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 1950 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 1951 }; 1952 }; 1953 1954 lcdc { 1955 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1956 rockchip,pins = 1957 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1958 }; 1959 1960 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1961 rockchip,pins = 1962 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1963 }; 1964 1965 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1966 rockchip,pins = 1967 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>; 1968 }; 1969 1970 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1971 rockchip,pins = 1972 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 1973 }; 1974 1975 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1976 rockchip,pins = 1977 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 1978 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 1979 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 1980 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 1981 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 1982 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 1983 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 1984 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 1985 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 1986 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 1987 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 1988 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 1989 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 1990 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 1991 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 1992 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 1993 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 1994 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 1995 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 1996 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 1997 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 1998 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 1999 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2000 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2001 }; 2002 2003 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2004 rockchip,pins = 2005 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2006 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2007 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2008 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2009 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2010 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2011 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2012 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2013 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2014 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2015 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2016 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2017 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2018 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2019 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2020 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2021 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2022 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2023 }; 2024 2025 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2026 rockchip,pins = 2027 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2028 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2029 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2030 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2031 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2032 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2033 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2034 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2035 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2036 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2037 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2038 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2039 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2040 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2041 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2042 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2043 }; 2044 2045 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2046 rockchip,pins = 2047 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2048 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2049 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2050 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2051 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2052 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2053 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2054 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2055 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2056 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 2057 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 2058 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2059 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2060 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2061 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2062 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2063 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2064 }; 2065 2066 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2067 rockchip,pins = 2068 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2069 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2070 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2071 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2072 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2073 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2074 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2075 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2076 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2077 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2078 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2079 }; 2080 2081 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2082 rockchip,pins = 2083 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2084 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2085 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2086 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2087 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2088 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2089 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2090 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2091 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2092 }; 2093 }; 2094 2095 pwm0 { 2096 pwm0_pin: pwm0-pin { 2097 rockchip,pins = 2098 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2099 }; 2100 }; 2101 2102 pwm1 { 2103 pwm1_pin: pwm1-pin { 2104 rockchip,pins = 2105 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2106 }; 2107 }; 2108 2109 pwm2 { 2110 pwm2_pin: pwm2-pin { 2111 rockchip,pins = 2112 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2113 }; 2114 }; 2115 2116 pwm3 { 2117 pwm3_pin: pwm3-pin { 2118 rockchip,pins = 2119 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2120 }; 2121 }; 2122 2123 pwm4 { 2124 pwm4_pin: pwm4-pin { 2125 rockchip,pins = 2126 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2127 }; 2128 }; 2129 2130 pwm5 { 2131 pwm5_pin: pwm5-pin { 2132 rockchip,pins = 2133 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2134 }; 2135 }; 2136 2137 pwm6 { 2138 pwm6_pin: pwm6-pin { 2139 rockchip,pins = 2140 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2141 }; 2142 }; 2143 2144 pwm7 { 2145 pwm7_pin: pwm7-pin { 2146 rockchip,pins = 2147 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2148 }; 2149 }; 2150 2151 gmac { 2152 rmii_pins: rmii-pins { 2153 rockchip,pins = 2154 /* mac_txen */ 2155 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2156 /* mac_txd1 */ 2157 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2158 /* mac_txd0 */ 2159 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2160 /* mac_rxd0 */ 2161 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2162 /* mac_rxd1 */ 2163 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2164 /* mac_rxer */ 2165 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2166 /* mac_rxdv */ 2167 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2168 /* mac_mdio */ 2169 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2170 /* mac_mdc */ 2171 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>, 2172 /* mac_clk */ 2173 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2174 }; 2175 }; 2176 2177 cif-m0 { 2178 cif_clkout_m0: cif-clkout-m0 { 2179 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2180 }; 2181 2182 dvp_d2d9_m0: dvp-d2d9-m0 { 2183 rockchip,pins = 2184 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2185 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2186 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2187 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2188 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2189 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2190 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2191 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2192 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2193 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2194 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2195 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2196 }; 2197 2198 dvp_d0d1_m0: dvp-d0d1-m0 { 2199 rockchip,pins = 2200 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2201 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2202 }; 2203 2204 dvp_d10d11_m0:d10-d11-m0 { 2205 rockchip,pins = 2206 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2207 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2208 }; 2209 }; 2210 2211 cif-m1 { 2212 cif_clkout_m1: cif-clkout-m1 { 2213 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2214 }; 2215 2216 dvp_d2d9_m1: dvp-d2d9-m1 { 2217 rockchip,pins = 2218 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2219 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2220 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2221 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2222 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2223 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2224 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2225 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2226 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2227 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2228 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2229 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2230 }; 2231 2232 dvp_d0d1_m1: dvp-d0d1-m1 { 2233 rockchip,pins = 2234 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2235 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2236 }; 2237 2238 dvp_d10d11_m1:d10-d11-m1 { 2239 rockchip,pins = 2240 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2241 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2242 }; 2243 }; 2244 2245 isp { 2246 isp_prelight: isp-prelight { 2247 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2248 }; 2249 }; 2250 }; 2251}; 2252