1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 display_subsystem: display-subsystem { 73 compatible = "rockchip,display-subsystem"; 74 ports = <&vopb_out>, <&vopl_out>; 75 status = "disabled"; 76 }; 77 78 firmware { 79 optee { 80 compatible = "linaro,optee-tz"; 81 method = "smc"; 82 }; 83 }; 84 85 psci { 86 compatible = "arm,psci-1.0"; 87 method = "smc"; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 93 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 }; 97 98 xin24m: xin24m { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <24000000>; 102 clock-output-names = "xin24m"; 103 }; 104 105 pmu: power-management@ff000000 { 106 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 107 reg = <0x0 0xff000000 0x0 0x1000>; 108 109 power: power-controller { 110 compatible = "rockchip,px30-power-controller"; 111 #power-domain-cells = <1>; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 status = "disabled"; 115 116 /* These power domains are grouped by VD_LOGIC */ 117 pd_usb@PX30_PD_USB { 118 reg = <PX30_PD_USB>; 119 clocks = <&cru HCLK_HOST>, 120 <&cru HCLK_OTG>, 121 <&cru SCLK_OTG_ADP>; 122 }; 123 pd_sdcard@PX30_PD_SDCARD { 124 reg = <PX30_PD_SDCARD>; 125 clocks = <&cru HCLK_SDMMC>, 126 <&cru SCLK_SDMMC>; 127 }; 128 pd_gmac@PX30_PD_GMAC { 129 reg = <PX30_PD_GMAC>; 130 clocks = <&cru ACLK_GMAC>, 131 <&cru PCLK_GMAC>, 132 <&cru SCLK_MAC_REF>, 133 <&cru SCLK_GMAC_RX_TX>; 134 }; 135 pd_mmc_nand@PX30_PD_MMC_NAND { 136 reg = <PX30_PD_MMC_NAND>; 137 clocks = <&cru HCLK_NANDC>, 138 <&cru HCLK_EMMC>, 139 <&cru HCLK_SDIO>, 140 <&cru HCLK_SFC>, 141 <&cru SCLK_EMMC>, 142 <&cru SCLK_NANDC>, 143 <&cru SCLK_SDIO>, 144 <&cru SCLK_SFC>; 145 }; 146 pd_vpu@PX30_PD_VPU { 147 reg = <PX30_PD_VPU>; 148 clocks = <&cru ACLK_VPU>, 149 <&cru HCLK_VPU>, 150 <&cru SCLK_CORE_VPU>; 151 }; 152 pd_vo@PX30_PD_VO { 153 reg = <PX30_PD_VO>; 154 clocks = <&cru ACLK_RGA>, 155 <&cru ACLK_VOPB>, 156 <&cru ACLK_VOPL>, 157 <&cru DCLK_VOPB>, 158 <&cru DCLK_VOPL>, 159 <&cru HCLK_RGA>, 160 <&cru HCLK_VOPB>, 161 <&cru HCLK_VOPL>, 162 <&cru PCLK_MIPI_DSI>, 163 <&cru SCLK_RGA_CORE>, 164 <&cru SCLK_VOPB_PWM>; 165 }; 166 pd_vi@PX30_PD_VI { 167 reg = <PX30_PD_VI>; 168 clocks = <&cru ACLK_CIF>, 169 <&cru ACLK_ISP>, 170 <&cru HCLK_CIF>, 171 <&cru HCLK_ISP>, 172 <&cru SCLK_ISP>; 173 }; 174 pd_gpu@PX30_PD_GPU { 175 reg = <PX30_PD_GPU>; 176 clocks = <&cru ACLK_GPU>; 177 }; 178 }; 179 }; 180 181 pmugrf: syscon@ff010000 { 182 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 183 reg = <0x0 0xff010000 0x0 0x1000>; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 187 pmu_io_domains: io-domains { 188 compatible = "rockchip,px30-pmu-io-voltage-domain"; 189 status = "disabled"; 190 }; 191 192 reboot-mode { 193 compatible = "syscon-reboot-mode"; 194 offset = <0x200>; 195 mode-bootloader = <BOOT_BL_DOWNLOAD>; 196 mode-charge = <BOOT_CHARGING>; 197 mode-fastboot = <BOOT_FASTBOOT>; 198 mode-loader = <BOOT_BL_DOWNLOAD>; 199 mode-normal = <BOOT_NORMAL>; 200 mode-recovery = <BOOT_RECOVERY>; 201 mode-ums = <BOOT_UMS>; 202 }; 203 204 pmu_pvtm: pmu-pvtm { 205 compatible = "rockchip,px30-pmu-pvtm"; 206 clocks = <&pmucru SCLK_PVTM_PMU>; 207 clock-names = "pmu"; 208 status = "disabled"; 209 }; 210 }; 211 212 uart0: serial@ff030000 { 213 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 214 reg = <0x0 0xff030000 0x0 0x100>; 215 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 217 clock-names = "baudclk", "apb_pclk"; 218 reg-shift = <2>; 219 reg-io-width = <4>; 220 dmas = <&dmac 0>, <&dmac 1>; 221 #dma-cells = <2>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 224 status = "disabled"; 225 }; 226 227 i2s0_8ch: i2s@ff060000 { 228 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 229 reg = <0x0 0xff060000 0x0 0x1000>; 230 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 232 clock-names = "i2s_clk", "i2s_hclk"; 233 dmas = <&dmac 16>, <&dmac 17>; 234 dma-names = "tx", "rx"; 235 status = "disabled"; 236 }; 237 238 i2s1_2ch: i2s@ff070000 { 239 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 240 reg = <0x0 0xff070000 0x0 0x1000>; 241 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 243 clock-names = "i2s_clk", "i2s_hclk"; 244 dmas = <&dmac 18>, <&dmac 19>; 245 dma-names = "tx", "rx"; 246 status = "disabled"; 247 }; 248 249 i2s2_2ch: i2s@ff080000 { 250 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 251 reg = <0x0 0xff080000 0x0 0x1000>; 252 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 254 clock-names = "i2s_clk", "i2s_hclk"; 255 dmas = <&dmac 20>, <&dmac 21>; 256 dma-names = "tx", "rx"; 257 status = "disabled"; 258 }; 259 260 pdm: pdm@ff0a0000 { 261 compatible = "rockchip,pdm"; 262 reg = <0x0 0xff0a0000 0x0 0x1000>; 263 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 264 clock-names = "pdm_clk", "pdm_hclk"; 265 dmas = <&dmac 24>; 266 dma-names = "rx"; 267 status = "disabled"; 268 }; 269 270 gic: interrupt-controller@ff131000 { 271 compatible = "arm,gic-400"; 272 #interrupt-cells = <3>; 273 #address-cells = <0>; 274 interrupt-controller; 275 reg = <0x0 0xff131000 0 0x1000>, 276 <0x0 0xff132000 0 0x2000>, 277 <0x0 0xff134000 0 0x2000>, 278 <0x0 0xff136000 0 0x2000>; 279 interrupts = <GIC_PPI 9 280 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 281 }; 282 283 grf: syscon@ff140000 { 284 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 285 reg = <0x0 0xff140000 0x0 0x1000>; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 289 io_domains: io-domains { 290 compatible = "rockchip,px30-io-voltage-domain"; 291 status = "disabled"; 292 }; 293 }; 294 295 core_grf: syscon@ff148000 { 296 compatible = "syscon", "simple-mfd"; 297 reg = <0x0 0xff148000 0x0 0x1000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 301 pvtm: pvtm { 302 compatible = "rockchip,px30-pvtm"; 303 clocks = <&cru SCLK_PVTM>; 304 clock-names = "core"; 305 status = "disabled"; 306 }; 307 }; 308 309 uart1: serial@ff158000 { 310 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 311 reg = <0x0 0xff158000 0x0 0x100>; 312 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 314 clock-names = "sclk_uart", "pclk_uart"; 315 reg-shift = <2>; 316 reg-io-width = <4>; 317 dmas = <&dmac 2>, <&dmac 3>; 318 #dma-cells = <2>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 321 status = "disabled"; 322 }; 323 324 uart2: serial@ff160000 { 325 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 326 reg = <0x0 0xff160000 0x0 0x100>; 327 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 329 clock-names = "baudclk", "apb_pclk"; 330 reg-shift = <2>; 331 reg-io-width = <4>; 332 dmas = <&dmac 4>, <&dmac 5>; 333 #dma-cells = <2>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&uart2m0_xfer>; 336 status = "disabled"; 337 }; 338 339 uart3: serial@ff168000 { 340 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 341 reg = <0x0 0xff168000 0x0 0x100>; 342 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 344 clock-names = "baudclk", "apb_pclk"; 345 reg-shift = <2>; 346 reg-io-width = <4>; 347 dmas = <&dmac 6>, <&dmac 7>; 348 #dma-cells = <2>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 351 status = "disabled"; 352 }; 353 354 uart4: serial@ff170000 { 355 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 356 reg = <0x0 0xff170000 0x0 0x100>; 357 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 359 clock-names = "baudclk", "apb_pclk"; 360 reg-shift = <2>; 361 reg-io-width = <4>; 362 dmas = <&dmac 8>, <&dmac 9>; 363 #dma-cells = <2>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 366 status = "disabled"; 367 }; 368 369 uart5: serial@ff178000 { 370 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 371 reg = <0x0 0xff178000 0x0 0x100>; 372 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 374 clock-names = "baudclk", "apb_pclk"; 375 reg-shift = <2>; 376 reg-io-width = <4>; 377 dmas = <&dmac 10>, <&dmac 11>; 378 #dma-cells = <2>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 381 status = "disabled"; 382 }; 383 384 i2c0: i2c@ff180000 { 385 compatible = "rockchip,rk3399-i2c"; 386 reg = <0x0 0xff180000 0x0 0x1000>; 387 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 388 clock-names = "i2c", "pclk"; 389 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&i2c0_xfer>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 i2c1: i2c@ff190000 { 398 compatible = "rockchip,rk3399-i2c"; 399 reg = <0x0 0xff190000 0x0 0x1000>; 400 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 401 clock-names = "i2c", "pclk"; 402 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&i2c1_xfer>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 410 i2c2: i2c@ff1a0000 { 411 compatible = "rockchip,rk3399-i2c"; 412 reg = <0x0 0xff1a0000 0x0 0x1000>; 413 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 414 clock-names = "i2c", "pclk"; 415 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&i2c2_xfer>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "disabled"; 421 }; 422 423 i2c3: i2c@ff1b0000 { 424 compatible = "rockchip,rk3399-i2c"; 425 reg = <0x0 0xff1b0000 0x0 0x1000>; 426 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 427 clock-names = "i2c", "pclk"; 428 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&i2c3_xfer>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 status = "disabled"; 434 }; 435 436 spi0: spi@ff1d0000 { 437 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 438 reg = <0x0 0xff1d0000 0x0 0x1000>; 439 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 443 clock-names = "spiclk", "apb_pclk"; 444 dmas = <&dmac 12>, <&dmac 13>; 445 #dma-cells = <2>; 446 dma-names = "tx", "rx"; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 449 status = "disabled"; 450 }; 451 452 spi1: spi@ff1d8000 { 453 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 454 reg = <0x0 0xff1d8000 0x0 0x1000>; 455 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 459 clock-names = "spiclk", "apb_pclk"; 460 dmas = <&dmac 14>, <&dmac 15>; 461 #dma-cells = <2>; 462 dma-names = "tx", "rx"; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 465 status = "disabled"; 466 }; 467 468 wdt: watchdog@ff1e0000 { 469 compatible = "snps,dw-wdt"; 470 reg = <0x0 0xff1e0000 0x0 0x100>; 471 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 472 status = "disabled"; 473 }; 474 475 pwm0: pwm@ff200000 { 476 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 477 reg = <0x0 0xff200000 0x0 0x10>; 478 #pwm-cells = <3>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pwm0_pin>; 481 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 482 clock-names = "pwm", "pclk"; 483 status = "disabled"; 484 }; 485 486 pwm1: pwm@ff200010 { 487 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 488 reg = <0x0 0xff200010 0x0 0x10>; 489 #pwm-cells = <3>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pwm1_pin>; 492 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 493 clock-names = "pwm", "pclk"; 494 status = "disabled"; 495 }; 496 497 pwm2: pwm@ff200020 { 498 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 499 reg = <0x0 0xff200020 0x0 0x10>; 500 #pwm-cells = <3>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&pwm2_pin>; 503 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 504 clock-names = "pwm", "pclk"; 505 status = "disabled"; 506 }; 507 508 pwm3: pwm@ff200030 { 509 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 510 reg = <0x0 0xff200030 0x0 0x10>; 511 #pwm-cells = <3>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&pwm3_pin>; 514 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 515 clock-names = "pwm", "pclk"; 516 status = "disabled"; 517 }; 518 519 pwm4: pwm@ff208000 { 520 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 521 reg = <0x0 0xff208000 0x0 0x10>; 522 #pwm-cells = <3>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&pwm4_pin>; 525 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 526 clock-names = "pwm", "pclk"; 527 status = "disabled"; 528 }; 529 530 pwm5: pwm@ff208010 { 531 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 532 reg = <0x0 0xff208010 0x0 0x10>; 533 #pwm-cells = <3>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&pwm5_pin>; 536 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 537 clock-names = "pwm", "pclk"; 538 status = "disabled"; 539 }; 540 541 pwm6: pwm@ff208020 { 542 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 543 reg = <0x0 0xff208020 0x0 0x10>; 544 #pwm-cells = <3>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pwm6_pin>; 547 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 548 clock-names = "pwm", "pclk"; 549 status = "disabled"; 550 }; 551 552 pwm7: pwm@ff208030 { 553 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 554 reg = <0x0 0xff208030 0x0 0x10>; 555 #pwm-cells = <3>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pwm7_pin>; 558 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 559 clock-names = "pwm", "pclk"; 560 status = "disabled"; 561 }; 562 563 amba { 564 compatible = "simple-bus"; 565 #address-cells = <2>; 566 #size-cells = <2>; 567 ranges; 568 569 dmac: dmac@ff240000 { 570 compatible = "arm,pl330", "arm,primecell"; 571 reg = <0x0 0xff240000 0x0 0x4000>; 572 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cru ACLK_DMAC>; 575 clock-names = "apb_pclk"; 576 #dma-cells = <1>; 577 peripherals-req-type-burst; 578 }; 579 }; 580 581 tsadc: tsadc@ff280000 { 582 compatible = "rockchip,px30-tsadc"; 583 reg = <0x0 0xff280000 0x0 0x100>; 584 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 585 rockchip,grf = <&grf>; 586 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 587 clock-names = "tsadc", "apb_pclk"; 588 assigned-clocks = <&cru SCLK_TSADC>; 589 assigned-clock-rates = <50000>; 590 resets = <&cru SRST_TSADC_P>; 591 reset-names = "tsadc-apb"; 592 pinctrl-names = "init", "default", "sleep"; 593 pinctrl-0 = <&tsadc_otp_gpio>; 594 pinctrl-1 = <&tsadc_otp_out>; 595 pinctrl-2 = <&tsadc_otp_gpio>; 596 #thermal-sensor-cells = <1>; 597 rockchip,hw-tshut-temp = <100000>; 598 status = "disabled"; 599 }; 600 601 saradc: saradc@ff288000 { 602 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 603 reg = <0x0 0xff288000 0x0 0x100>; 604 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 605 #io-channel-cells = <1>; 606 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 607 clock-names = "saradc", "apb_pclk"; 608 resets = <&cru SRST_SARADC_P>; 609 reset-names = "saradc-apb"; 610 status = "disabled"; 611 }; 612 613 cru: clock-controller@ff2b0000 { 614 compatible = "rockchip,px30-cru"; 615 reg = <0x0 0xff2b0000 0x0 0x9000>; 616 rockchip,grf = <&grf>; 617 #clock-cells = <1>; 618 #reset-cells = <1>; 619 620 assigned-clocks = 621 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 622 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 623 <&cru ARMCLK>; 624 assigned-clock-rates = 625 <1608000000>, <1416000000>, 626 <1188000000>, <1188000000>, 627 <816000000>; 628 }; 629 630 pmucru: pmu-clock-controller@ff2bc000 { 631 compatible = "rockchip,px30-pmucru"; 632 reg = <0x0 0xff2bc000 0x0 0x1000>; 633 rockchip,grf = <&grf>; 634 #clock-cells = <1>; 635 #reset-cells = <1>; 636 637 assigned-clocks = 638 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 639 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 640 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 641 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 642 assigned-clock-rates = 643 <1200000000>, <100000000>, 644 <26000000>, <300000000>, 645 <300000000>, <150000000>, 646 <150000000>, <75000000>; 647 }; 648 649 usb2phy_grf: syscon@ff2c0000 { 650 compatible = "rockchip,px30-usb2phy-grf", "syscon", 651 "simple-mfd"; 652 reg = <0x0 0xff2c0000 0x0 0x10000>; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 656 u2phy: usb2-phy@100 { 657 compatible = "rockchip,px30-usb2phy", 658 "rockchip,rk3328-usb2phy"; 659 reg = <0x100 0x10>; 660 clocks = <&pmucru SCLK_USBPHY_REF>; 661 clock-names = "phyclk"; 662 #clock-cells = <0>; 663 assigned-clocks = <&cru USB480M>; 664 assigned-clock-parents = <&u2phy>; 665 clock-output-names = "usb480m_phy"; 666 status = "disabled"; 667 668 u2phy_host: host-port { 669 #phy-cells = <0>; 670 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 671 interrupt-names = "linestate"; 672 status = "disabled"; 673 }; 674 675 u2phy_otg: otg-port { 676 #phy-cells = <0>; 677 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 680 interrupt-names = "otg-bvalid", "otg-id", 681 "linestate"; 682 status = "disabled"; 683 }; 684 }; 685 }; 686 687 mipi_dphy: mipi-dphy@ff2e0000 { 688 compatible = "rockchip,px30-mipi-dphy"; 689 reg = <0x0 0xff2e0000 0x0 0x10000>; 690 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 691 clock-names = "ref", "pclk"; 692 clock-output-names = "mipi_dphy_pll"; 693 #clock-cells = <0>; 694 resets = <&cru SRST_MIPIDSIPHY_P>; 695 reset-names = "apb"; 696 power-domains = <&power PX30_PD_VO>; 697 #phy-cells = <0>; 698 rockchip,grf = <&grf>; 699 status = "disabled"; 700 }; 701 702 lvds: lvds@ff2e0000 { 703 compatible = "rockchip,px30-lvds"; 704 reg = <0x0 0xff2e0000 0x0 0x100>, <0x0 0xff2e0100 0x0 0x100>; 705 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 706 clocks = <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 707 clock-names = "pclk_lvds", "pclk_lvds_ctl"; 708 power-domains = <&power PX30_PD_VO>; 709 rockchip,grf = <&grf>; 710 status = "disabled"; 711 712 ports { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 716 port@0 { 717 reg = <0>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 lvds_in_vopl: endpoint@0 { 722 reg = <0>; 723 remote-endpoint = <&vopl_out_lvds>; 724 }; 725 726 lvds_in_vopb: endpoint@1 { 727 reg = <1>; 728 remote-endpoint = <&vopb_out_lvds>; 729 }; 730 }; 731 }; 732 }; 733 734 usb20_otg: usb@ff300000 { 735 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 736 "snps,dwc2"; 737 reg = <0x0 0xff300000 0x0 0x40000>; 738 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cru HCLK_OTG>; 740 clock-names = "otg"; 741 dr_mode = "otg"; 742 g-np-tx-fifo-size = <16>; 743 g-rx-fifo-size = <275>; 744 g-tx-fifo-size = <256 128 128 64 64 32>; 745 g-use-dma; 746 phys = <&u2phy_otg>; 747 phy-names = "usb2-phy"; 748 status = "disabled"; 749 }; 750 751 usb_host0_ehci: usb@ff340000 { 752 compatible = "generic-ehci"; 753 reg = <0x0 0xff340000 0x0 0x10000>; 754 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 756 <&u2phy>; 757 clock-names = "usbhost", "arbiter", "utmi"; 758 phys = <&u2phy_host>; 759 phy-names = "usb"; 760 status = "disabled"; 761 }; 762 763 usb_host0_ohci: usb@ff350000 { 764 compatible = "generic-ohci"; 765 reg = <0x0 0xff350000 0x0 0x10000>; 766 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 768 <&u2phy>; 769 clock-names = "usbhost", "arbiter", "utmi"; 770 phys = <&u2phy_host>; 771 phy-names = "usb"; 772 }; 773 774 gmac: ethernet@ff360000 { 775 compatible = "rockchip,px30-gmac"; 776 reg = <0x0 0xff360000 0x0 0x10000>; 777 rockchip,grf = <&grf>; 778 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 779 interrupt-names = "macirq"; 780 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 781 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 782 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 783 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 784 clock-names = "stmmaceth", "mac_clk_rx", 785 "mac_clk_tx", "clk_mac_ref", 786 "clk_mac_refout", "aclk_mac", 787 "pclk_mac", "clk_mac_speed"; 788 phy-mode = "rmii"; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&rmii_pins>; 791 resets = <&cru SRST_GMAC_A>; 792 reset-names = "stmmaceth"; 793 power-domains = <&power PX30_PD_GMAC>; 794 status = "disabled"; 795 }; 796 797 sdmmc: dwmmc@ff370000 { 798 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 799 reg = <0x0 0xff370000 0x0 0x4000>; 800 max-frequency = <150000000>; 801 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 802 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 803 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 804 fifo-depth = <0x100>; 805 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 808 status = "disabled"; 809 }; 810 811 sdio: dwmmc@ff380000 { 812 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 813 reg = <0x0 0xff380000 0x0 0x4000>; 814 max-frequency = <150000000>; 815 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 816 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 817 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 818 fifo-depth = <0x100>; 819 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 820 status = "disabled"; 821 }; 822 823 emmc: dwmmc@ff390000 { 824 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 825 reg = <0x0 0xff390000 0x0 0x4000>; 826 max-frequency = <150000000>; 827 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 828 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 829 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 830 fifo-depth = <0x100>; 831 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 832 status = "disabled"; 833 }; 834 835 nandc0: nandc@ff3b0000 { 836 compatible = "rockchip,rk-nandc"; 837 reg = <0x0 0xff3b0000 0x0 0x4000>; 838 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 839 nandc_id = <0>; 840 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 841 clock-names = "clk_nandc", "hclk_nandc"; 842 status = "disabled"; 843 }; 844 845 gpu: gpu@ff400000 { 846 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 847 reg = <0x0 0xff400000 0x0 0x4000>; 848 849 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-names = "GPU", "MMU", "JOB"; 853 854 clocks = <&cru ACLK_GPU>; 855 clock-names = "clk_mali"; 856 857 status = "disabled"; 858 }; 859 860 hevc: hevc_service@ff440000 { 861 compatible = "rockchip,hevc_sub"; 862 iommu_enabled = <1>; 863 reg = <0x0 0xff440000 0x0 0x400>; 864 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 865 interrupt-names = "irq_dec"; 866 dev_mode = <1>; 867 iommus = <&hevc_mmu>; 868 name = "hevc_service"; 869 allocator = <1>; 870 }; 871 872 vpu: vpu_service@ff442000 { 873 compatible = "rockchip,vpu_sub"; 874 iommu_enabled = <1>; 875 reg = <0x0 0xff442000 0x0 0x800>; 876 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 878 interrupt-names = "irq_enc", "irq_dec"; 879 dev_mode = <0>; 880 iommus = <&vpu_mmu>; 881 name = "vpu_service"; 882 allocator = <1>; 883 }; 884 885 vpu_combo: vpu_combo { 886 compatible = "rockchip,vpu_combo"; 887 subcnt = <2>; 888 rockchip,grf = <&grf>; 889 rockchip,sub = <&vpu>, <&hevc>; 890 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 891 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 892 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 893 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 894 <&cru SRST_VPU_CORE>; 895 reset-names = "video_a", "video_h", "niu_a", "niu_h", 896 "video_core"; 897 mode_bit = <15>; 898 mode_ctrl = <0x410>; 899 name = "vpu_combo"; 900 status = "disabled"; 901 }; 902 903 hevc_mmu: iommu@ff440440 { 904 compatible = "rockchip,iommu"; 905 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 906 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 907 interrupt-names = "hevc_mmu"; 908 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 909 clock-names = "aclk", "hclk"; 910 #iommu-cells = <0>; 911 }; 912 913 vpu_mmu: iommu@ff442800 { 914 compatible = "rockchip,iommu"; 915 reg = <0x0 0xff442800 0x0 0x100>; 916 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "vpu_mmu"; 918 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 919 clock-names = "aclk", "hclk"; 920 #iommu-cells = <0>; 921 }; 922 923 dsi: dsi@ff450000 { 924 compatible = "rockchip,px30-mipi-dsi"; 925 reg = <0x0 0xff450000 0x0 0x10000>; 926 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&cru PCLK_MIPI_DSI>, <&mipi_dphy>; 928 clock-names = "pclk", "hs_clk"; 929 resets = <&cru SRST_MIPIDSI_HOST_P>; 930 reset-names = "apb"; 931 phys = <&mipi_dphy>; 932 phy-names = "mipi_dphy"; 933 power-domains = <&power PX30_PD_VO>; 934 rockchip,grf = <&grf>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 status = "disabled"; 938 939 ports { 940 port { 941 #address-cells = <1>; 942 #size-cells = <0>; 943 944 dsi_in_vopl: endpoint@0 { 945 reg = <0>; 946 remote-endpoint = <&vopl_out_dsi>; 947 }; 948 949 dsi_in_vopb: endpoint@1 { 950 reg = <1>; 951 remote-endpoint = <&vopb_out_dsi>; 952 }; 953 }; 954 }; 955 }; 956 957 vopb: vop@ff460000 { 958 compatible = "rockchip,px30-vop-big"; 959 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 960 reg-names = "regs", "gamma_lut"; 961 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 963 <&cru HCLK_VOPB>; 964 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 965 iommus = <&vopb_mmu>; 966 status = "disabled"; 967 968 vopb_out: port { 969 #address-cells = <1>; 970 #size-cells = <0>; 971 972 vopb_out_lvds: endpoint@0 { 973 reg = <0>; 974 remote-endpoint = <&lvds_in_vopb>; 975 }; 976 977 vopb_out_dsi: endpoint@1 { 978 reg = <1>; 979 remote-endpoint = <&dsi_in_vopb>; 980 }; 981 }; 982 }; 983 984 vopb_mmu: iommu@ff460f00 { 985 compatible = "rockchip,iommu"; 986 reg = <0x0 0xff460f00 0x0 0x100>; 987 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "vopb_mmu"; 989 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 990 clock-names = "aclk", "hclk"; 991 #iommu-cells = <0>; 992 status = "disabled"; 993 }; 994 995 vopl: vop@ff470000 { 996 compatible = "rockchip,px30-vop-lit"; 997 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 998 reg-names = "regs", "gamma_lut"; 999 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1001 <&cru HCLK_VOPL>; 1002 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1003 iommus = <&vopl_mmu>; 1004 status = "disabled"; 1005 1006 vopl_out: port { 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 1010 vopl_out_lvds: endpoint@0 { 1011 reg = <0>; 1012 remote-endpoint = <&lvds_in_vopl>; 1013 }; 1014 1015 vopl_out_dsi: endpoint@1 { 1016 reg = <1>; 1017 remote-endpoint = <&dsi_in_vopl>; 1018 }; 1019 }; 1020 }; 1021 1022 vopl_mmu: iommu@ff470f00 { 1023 compatible = "rockchip,iommu"; 1024 reg = <0x0 0xff470f00 0x0 0x100>; 1025 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1026 interrupt-names = "vopl_mmu"; 1027 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1028 clock-names = "aclk", "hclk"; 1029 #iommu-cells = <0>; 1030 status = "disabled"; 1031 }; 1032 1033 rk_rga: rk_rga@ff480000 { 1034 compatible = "rockchip,rga2"; 1035 //dev_mode = <1>; 1036 reg = <0x0 0xff480000 0x0 0x1000>; 1037 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1039 clock-names = "aclk_rga", "hclk_rga"; 1040 dma-coherent; 1041 status = "disabled"; 1042 }; 1043 1044 cif: cif@ff490000 { 1045 compatible = "rockchip,cif"; 1046 reg = <0x0 0xff490000 0x0 0x200>; 1047 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1049 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1050 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1051 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1052 pinctrl-names = "cif_pin_all"; 1053 pinctrl-0 = <&dvp_d2d9_m0>; 1054 status = "disabled"; 1055 }; 1056 1057 vip_mmu: iommu@ff490800{ 1058 compatible = "rockchip,iommu"; 1059 reg = <0x0 0xff490800 0x0 0x100>; 1060 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1061 interrupt-names = "vip_mmu"; 1062 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1063 clock-names = "aclk", "hclk"; 1064 rk_iommu,disable_reset_quirk; 1065 #iommu-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 rk_isp: rk_isp@ff4a0000 { 1070 compatible = "rockchip,px30-isp", "rockchip,isp"; 1071 reg = <0x0 0xff4a0000 0x0 0x4000>; 1072 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1074 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1075 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1076 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1077 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1078 reset-names = "rst_isp", "rst_mipicsiphy"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&cif_clkout_m0>; 1081 rockchip,isp,mipiphy = <0>; 1082 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1083 rockchip,grf = <&grf>; 1084 rockchip,cru = <&cru>; 1085 rockchip,isp,iommu-enable = <1>; 1086 iommus = <&isp_mmu>; 1087 status = "disabled"; 1088 }; 1089 1090 isp_mmu: iommu@ff4a8000 { 1091 compatible = "rockchip,iommu"; 1092 reg = <0x0 0xff4a8000 0x0 0x100>; 1093 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1094 interrupt-names = "isp_mmu"; 1095 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1096 clock-names = "aclk", "hclk"; 1097 rk_iommu,disable_reset_quirk; 1098 #iommu-cells = <0>; 1099 status = "disabled"; 1100 }; 1101 1102 qos_gmac: qos@ff518000 { 1103 compatible = "syscon"; 1104 reg = <0x0 0xff518000 0x0 0x20>; 1105 }; 1106 1107 qos_gpu: qos@ff520000 { 1108 compatible = "syscon"; 1109 reg = <0x0 0xff520000 0x0 0x20>; 1110 }; 1111 1112 qos_sdmmc: qos@ff52c000 { 1113 compatible = "syscon"; 1114 reg = <0x0 0xff52c000 0x0 0x20>; 1115 }; 1116 1117 qos_emmc: qos@ff538000 { 1118 compatible = "syscon"; 1119 reg = <0x0 0xff538000 0x0 0x20>; 1120 }; 1121 1122 qos_nand: qos@ff538080 { 1123 compatible = "syscon"; 1124 reg = <0x0 0xff538080 0x0 0x20>; 1125 }; 1126 1127 qos_sdio: qos@ff538100 { 1128 compatible = "syscon"; 1129 reg = <0x0 0xff538100 0x0 0x20>; 1130 }; 1131 1132 qos_sfc: qos@ff538180 { 1133 compatible = "syscon"; 1134 reg = <0x0 0xff538180 0x0 0x20>; 1135 }; 1136 1137 qos_usb_host: qos@ff540000 { 1138 compatible = "syscon"; 1139 reg = <0x0 0xff540000 0x0 0x20>; 1140 }; 1141 1142 qos_usb_otg: qos@ff540080 { 1143 compatible = "syscon"; 1144 reg = <0x0 0xff540080 0x0 0x20>; 1145 }; 1146 1147 qos_isp_128: qos@ff548000 { 1148 compatible = "syscon"; 1149 reg = <0x0 0xff548000 0x0 0x20>; 1150 }; 1151 1152 qos_isp_rd: qos@ff548080 { 1153 compatible = "syscon"; 1154 reg = <0x0 0xff548080 0x0 0x20>; 1155 }; 1156 1157 qos_isp_wr: qos@ff548100 { 1158 compatible = "syscon"; 1159 reg = <0x0 0xff548100 0x0 0x20>; 1160 }; 1161 1162 qos_isp_m1: qos@ff548180 { 1163 compatible = "syscon"; 1164 reg = <0x0 0xff548180 0x0 0x20>; 1165 }; 1166 1167 qos_vip: qos@ff548200 { 1168 compatible = "syscon"; 1169 reg = <0x0 0xff548200 0x0 0x20>; 1170 }; 1171 1172 qos_rga_rd: qos@ff550000 { 1173 compatible = "syscon"; 1174 reg = <0x0 0xff550000 0x0 0x20>; 1175 }; 1176 1177 qos_rga_wr: qos@ff550080 { 1178 compatible = "syscon"; 1179 reg = <0x0 0xff550080 0x0 0x20>; 1180 }; 1181 1182 qos_vop_m0: qos@ff550100 { 1183 compatible = "syscon"; 1184 reg = <0x0 0xff550100 0x0 0x20>; 1185 }; 1186 1187 qos_vop_m1: qos@ff550180 { 1188 compatible = "syscon"; 1189 reg = <0x0 0xff550180 0x0 0x20>; 1190 }; 1191 1192 qos_vpu: qos@ff558000 { 1193 compatible = "syscon"; 1194 reg = <0x0 0xff558000 0x0 0x20>; 1195 }; 1196 1197 qos_vpu_r128: qos@ff558080 { 1198 compatible = "syscon"; 1199 reg = <0x0 0xff558080 0x0 0x20>; 1200 }; 1201 1202 pinctrl: pinctrl { 1203 compatible = "rockchip,px30-pinctrl"; 1204 rockchip,grf = <&grf>; 1205 rockchip,pmu = <&pmugrf>; 1206 #address-cells = <2>; 1207 #size-cells = <2>; 1208 ranges; 1209 1210 gpio0: gpio0@ff040000 { 1211 compatible = "rockchip,gpio-bank"; 1212 reg = <0x0 0xff040000 0x0 0x100>; 1213 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1214 clocks = <&cru PCLK_GPIO0_PMU>; 1215 gpio-controller; 1216 #gpio-cells = <2>; 1217 1218 interrupt-controller; 1219 #interrupt-cells = <2>; 1220 }; 1221 1222 gpio1: gpio1@ff250000 { 1223 compatible = "rockchip,gpio-bank"; 1224 reg = <0x0 0xff250000 0x0 0x100>; 1225 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1226 clocks = <&cru PCLK_GPIO1>; 1227 gpio-controller; 1228 #gpio-cells = <2>; 1229 1230 interrupt-controller; 1231 #interrupt-cells = <2>; 1232 }; 1233 1234 gpio2: gpio2@ff260000 { 1235 compatible = "rockchip,gpio-bank"; 1236 reg = <0x0 0xff260000 0x0 0x100>; 1237 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&cru PCLK_GPIO2>; 1239 gpio-controller; 1240 #gpio-cells = <2>; 1241 1242 interrupt-controller; 1243 #interrupt-cells = <2>; 1244 }; 1245 1246 gpio3: gpio3@ff270000 { 1247 compatible = "rockchip,gpio-bank"; 1248 reg = <0x0 0xff270000 0x0 0x100>; 1249 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&cru PCLK_GPIO3>; 1251 gpio-controller; 1252 #gpio-cells = <2>; 1253 1254 interrupt-controller; 1255 #interrupt-cells = <2>; 1256 }; 1257 1258 pcfg_pull_up: pcfg-pull-up { 1259 bias-pull-up; 1260 }; 1261 1262 pcfg_pull_down: pcfg-pull-down { 1263 bias-pull-down; 1264 }; 1265 1266 pcfg_pull_none: pcfg-pull-none { 1267 bias-disable; 1268 }; 1269 1270 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1271 bias-disable; 1272 drive-strength = <2>; 1273 }; 1274 1275 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1276 bias-pull-up; 1277 drive-strength = <2>; 1278 }; 1279 1280 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1281 bias-pull-up; 1282 drive-strength = <4>; 1283 }; 1284 1285 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1286 bias-disable; 1287 drive-strength = <4>; 1288 }; 1289 1290 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1291 bias-pull-down; 1292 drive-strength = <4>; 1293 }; 1294 1295 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1296 bias-disable; 1297 drive-strength = <8>; 1298 }; 1299 1300 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1301 bias-pull-up; 1302 drive-strength = <8>; 1303 }; 1304 1305 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1306 bias-disable; 1307 drive-strength = <12>; 1308 }; 1309 1310 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1311 bias-pull-up; 1312 drive-strength = <12>; 1313 }; 1314 1315 pcfg_pull_none_smt: pcfg-pull-none-smt { 1316 bias-disable; 1317 input-schmitt-enable; 1318 }; 1319 1320 pcfg_output_high: pcfg-output-high { 1321 output-high; 1322 }; 1323 1324 pcfg_output_low: pcfg-output-low { 1325 output-low; 1326 }; 1327 1328 pcfg_input_high: pcfg-input-high { 1329 bias-pull-up; 1330 input-enable; 1331 }; 1332 1333 pcfg_input: pcfg-input { 1334 input-enable; 1335 }; 1336 1337 i2c0 { 1338 i2c0_xfer: i2c0-xfer { 1339 rockchip,pins = 1340 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1341 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1342 }; 1343 }; 1344 1345 i2c1 { 1346 i2c1_xfer: i2c1-xfer { 1347 rockchip,pins = 1348 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1349 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1350 }; 1351 }; 1352 1353 i2c2 { 1354 i2c2_xfer: i2c2-xfer { 1355 rockchip,pins = 1356 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1357 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1358 }; 1359 }; 1360 1361 i2c3 { 1362 i2c3_xfer: i2c3-xfer { 1363 rockchip,pins = 1364 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1365 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1366 }; 1367 }; 1368 1369 tsadc { 1370 tsadc_otp_gpio: tsadc-otp-gpio { 1371 rockchip,pins = 1372 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1373 }; 1374 1375 tsadc_otp_out: tsadc-otp-out { 1376 rockchip,pins = 1377 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1378 }; 1379 }; 1380 1381 uart0 { 1382 uart0_xfer: uart0-xfer { 1383 rockchip,pins = 1384 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1385 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1386 }; 1387 1388 uart0_cts: uart0-cts { 1389 rockchip,pins = 1390 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1391 }; 1392 1393 uart0_rts: uart0-rts { 1394 rockchip,pins = 1395 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1396 }; 1397 1398 uart0_rts_gpio: uart0-rts-gpio { 1399 rockchip,pins = 1400 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1401 }; 1402 }; 1403 1404 uart1 { 1405 uart1_xfer: uart1-xfer { 1406 rockchip,pins = 1407 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1408 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1409 }; 1410 1411 uart1_cts: uart1-cts { 1412 rockchip,pins = 1413 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1414 }; 1415 1416 uart1_rts: uart1-rts { 1417 rockchip,pins = 1418 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1419 }; 1420 1421 uart1_rts_gpio: uart1-rts-gpio { 1422 rockchip,pins = 1423 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1424 }; 1425 }; 1426 1427 uart2-m0 { 1428 uart2m0_xfer: uart2m0-xfer { 1429 rockchip,pins = 1430 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1431 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1432 }; 1433 }; 1434 1435 uart2-m1 { 1436 uart2m1_xfer: uart2m1-xfer { 1437 rockchip,pins = 1438 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1439 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1440 }; 1441 }; 1442 1443 uart3-m0 { 1444 uart3m0_xfer: uart3m0-xfer { 1445 rockchip,pins = 1446 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1447 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1448 }; 1449 1450 uart3m0_cts: uart3m0-cts { 1451 rockchip,pins = 1452 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1453 }; 1454 1455 uart3m0_rts: uart3m0-rts { 1456 rockchip,pins = 1457 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1458 }; 1459 1460 uart3m0_rts_gpio: uart3m0-rts-gpio { 1461 rockchip,pins = 1462 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1463 }; 1464 }; 1465 1466 uart3-m1 { 1467 uart3m1_xfer: uart3m1-xfer { 1468 rockchip,pins = 1469 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1470 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1471 }; 1472 1473 uart3m1_cts: uart3m1-cts { 1474 rockchip,pins = 1475 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1476 }; 1477 1478 uart3m1_rts: uart3m1-rts { 1479 rockchip,pins = 1480 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1481 }; 1482 1483 uart3m1_rts_gpio: uart3m1-rts-gpio { 1484 rockchip,pins = 1485 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1486 }; 1487 }; 1488 1489 uart4 { 1490 1491 uart4_xfer: uart4-xfer { 1492 rockchip,pins = 1493 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1494 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1495 }; 1496 1497 uart4_cts: uart4-cts { 1498 rockchip,pins = 1499 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1500 1501 }; 1502 1503 uart4_rts: uart4-rts { 1504 rockchip,pins = 1505 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1506 }; 1507 }; 1508 1509 uart5 { 1510 1511 uart5_xfer: uart5-xfer { 1512 rockchip,pins = 1513 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1514 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1515 }; 1516 1517 uart5_cts: uart5-cts { 1518 rockchip,pins = 1519 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1520 1521 }; 1522 1523 uart5_rts: uart5-rts { 1524 rockchip,pins = 1525 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1526 }; 1527 }; 1528 1529 spi0 { 1530 spi0_clk: spi0-clk { 1531 rockchip,pins = 1532 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1533 }; 1534 1535 spi0_csn: spi0-csn { 1536 rockchip,pins = 1537 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1538 }; 1539 1540 spi0_miso: spi0-miso { 1541 rockchip,pins = 1542 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1543 }; 1544 1545 spi0_mosi: spi0-mosi { 1546 rockchip,pins = 1547 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1548 }; 1549 }; 1550 1551 spi1 { 1552 spi1_clk: spi1-clk { 1553 rockchip,pins = 1554 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1555 }; 1556 1557 spi1_csn: spi1-csn { 1558 rockchip,pins = 1559 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1560 }; 1561 1562 spi1_miso: spi1-miso { 1563 rockchip,pins = 1564 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1565 }; 1566 1567 spi1_mosi: spi1-mosi { 1568 rockchip,pins = 1569 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1570 }; 1571 }; 1572 1573 pdm { 1574 pdm_clk0m0: pdm-clk0m0 { 1575 rockchip,pins = 1576 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1577 }; 1578 1579 pdm_clk0m1: pdm-clk0m1 { 1580 rockchip,pins = 1581 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1582 }; 1583 1584 pdm_clk1: pdm-clk1 { 1585 rockchip,pins = 1586 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1587 }; 1588 1589 pdm_sdi0m0: pdm-sdi0m0 { 1590 rockchip,pins = 1591 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1592 }; 1593 1594 pdm_sdi0m1: pdm-sdi0m1 { 1595 rockchip,pins = 1596 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1597 }; 1598 1599 pdm_sdi1: pdm-sdi1 { 1600 rockchip,pins = 1601 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1602 }; 1603 1604 pdm_sdi2: pdm-sdi2 { 1605 rockchip,pins = 1606 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1607 }; 1608 1609 pdm_sdi3: pdm-sdi3 { 1610 rockchip,pins = 1611 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1612 }; 1613 1614 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1615 rockchip,pins = 1616 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1617 }; 1618 1619 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1620 rockchip,pins = 1621 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1622 }; 1623 1624 pdm_clk1_sleep: pdm-clk1-sleep { 1625 rockchip,pins = 1626 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1627 }; 1628 1629 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1630 rockchip,pins = 1631 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1632 }; 1633 1634 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1635 rockchip,pins = 1636 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1637 }; 1638 1639 pdm_sdi1_sleep: pdm-sdi1-sleep { 1640 rockchip,pins = 1641 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1642 }; 1643 1644 pdm_sdi2_sleep: pdm-sdi2-sleep { 1645 rockchip,pins = 1646 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1647 }; 1648 1649 pdm_sdi3_sleep: pdm-sdi3-sleep { 1650 rockchip,pins = 1651 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1652 }; 1653 }; 1654 1655 i2s0 { 1656 i2s0_8ch_mclk: i2s0-8ch-mclk { 1657 rockchip,pins = 1658 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1659 }; 1660 1661 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1662 rockchip,pins = 1663 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1664 }; 1665 1666 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1667 rockchip,pins = 1668 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1669 }; 1670 1671 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1672 rockchip,pins = 1673 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1674 }; 1675 1676 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1677 rockchip,pins = 1678 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1679 }; 1680 1681 i2s0_8ch_sdo: i2s0-8ch-sdo { 1682 rockchip,pins = 1683 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1684 }; 1685 1686 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1687 rockchip,pins = 1688 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1689 }; 1690 1691 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1692 rockchip,pins = 1693 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1694 }; 1695 1696 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1697 rockchip,pins = 1698 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1699 }; 1700 1701 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1702 rockchip,pins = 1703 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1704 }; 1705 1706 i2s0_8ch_sdi: i2s0-8ch-sdi { 1707 rockchip,pins = 1708 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1709 }; 1710 1711 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1712 rockchip,pins = 1713 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1714 }; 1715 1716 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1717 rockchip,pins = 1718 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1719 }; 1720 1721 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1722 rockchip,pins = 1723 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1724 }; 1725 1726 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1727 rockchip,pins = 1728 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1729 }; 1730 }; 1731 1732 i2s1 { 1733 i2s1_2ch_mclk: i2s1-2ch-mclk { 1734 rockchip,pins = 1735 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1736 }; 1737 1738 i2s1_2ch_sclk: i2s1-2ch-sclk { 1739 rockchip,pins = 1740 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1741 }; 1742 1743 i2s1_2ch_lrck: i2s1-2ch-lrck { 1744 rockchip,pins = 1745 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1746 }; 1747 1748 i2s1_2ch_sdi: i2s1-2ch-sdi { 1749 rockchip,pins = 1750 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1751 }; 1752 1753 i2s1_2ch_sdo: i2s1-2ch-sdo { 1754 rockchip,pins = 1755 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1756 }; 1757 }; 1758 1759 i2s2 { 1760 i2s2_2ch_mclk: i2s2-2ch-mclk { 1761 rockchip,pins = 1762 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1763 }; 1764 1765 i2s2_2ch_sclk: i2s2-2ch-sclk { 1766 rockchip,pins = 1767 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1768 }; 1769 1770 i2s2_2ch_lrck: i2s2-2ch-lrck { 1771 rockchip,pins = 1772 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1773 }; 1774 1775 i2s2_2ch_sdi: i2s2-2ch-sdi { 1776 rockchip,pins = 1777 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1778 }; 1779 1780 i2s2_2ch_sdo: i2s2-2ch-sdo { 1781 rockchip,pins = 1782 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1783 }; 1784 }; 1785 1786 sdmmc { 1787 sdmmc_clk: sdmmc-clk { 1788 rockchip,pins = 1789 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_8ma>; 1790 }; 1791 1792 sdmmc_cmd: sdmmc-cmd { 1793 rockchip,pins = 1794 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_8ma>; 1795 }; 1796 1797 sdmmc_det: sdmmc-det { 1798 rockchip,pins = 1799 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>; 1800 }; 1801 1802 sdmmc_bus1: sdmmc-bus1 { 1803 rockchip,pins = 1804 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>; 1805 }; 1806 1807 sdmmc_bus4: sdmmc-bus4 { 1808 rockchip,pins = 1809 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>, 1810 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_8ma>, 1811 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_8ma>, 1812 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_8ma>; 1813 }; 1814 1815 sdmmc_gpio: sdmmc-gpio { 1816 rockchip,pins = 1817 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1818 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1819 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1820 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1821 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1822 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1823 }; 1824 }; 1825 1826 sdio { 1827 sdio_clk: sdio-clk { 1828 rockchip,pins = 1829 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1830 }; 1831 1832 sdio_cmd: sdio-cmd { 1833 rockchip,pins = 1834 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1835 }; 1836 1837 sdio_bus4: sdio-bus4 { 1838 rockchip,pins = 1839 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1840 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>, 1841 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>, 1842 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>; 1843 }; 1844 1845 sdio_gpio: sdio-gpio { 1846 rockchip,pins = 1847 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 1848 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, 1849 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, 1850 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, 1851 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, 1852 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 1853 }; 1854 }; 1855 1856 emmc { 1857 emmc_clk: emmc-clk { 1858 rockchip,pins = 1859 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1860 }; 1861 1862 emmc_cmd: emmc-cmd { 1863 rockchip,pins = 1864 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1865 }; 1866 1867 emmc_pwren: emmc-pwren { 1868 rockchip,pins = 1869 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1870 }; 1871 1872 emmc_rstnout: emmc-rstnout { 1873 rockchip,pins = 1874 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1875 }; 1876 1877 emmc_bus1: emmc-bus1 { 1878 rockchip,pins = 1879 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1880 }; 1881 1882 emmc_bus4: emmc-bus4 { 1883 rockchip,pins = 1884 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1885 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1886 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1887 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1888 }; 1889 1890 emmc_bus8: emmc-bus8 { 1891 rockchip,pins = 1892 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1893 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1894 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1895 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1896 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1897 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1898 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1899 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1900 }; 1901 }; 1902 1903 flash { 1904 flash_cs0: flash-cs0 { 1905 rockchip,pins = 1906 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1907 }; 1908 1909 flash_rdy: flash-rdy { 1910 rockchip,pins = 1911 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1912 }; 1913 1914 flash_dqs: flash-dqs { 1915 rockchip,pins = 1916 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1917 }; 1918 1919 flash_ale: flash-ale { 1920 rockchip,pins = 1921 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1922 }; 1923 1924 flash_cle: flash-cle { 1925 rockchip,pins = 1926 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1927 }; 1928 1929 flash_wrn: flash-wrn { 1930 rockchip,pins = 1931 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1932 }; 1933 1934 flash_csl: flash-csl { 1935 rockchip,pins = 1936 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 1937 }; 1938 1939 flash_rdn: flash-rdn { 1940 rockchip,pins = 1941 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 1942 }; 1943 1944 flash_bus8: flash-bus8 { 1945 rockchip,pins = 1946 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 1947 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 1948 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 1949 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 1950 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 1951 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 1952 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 1953 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 1954 }; 1955 }; 1956 1957 lcdc { 1958 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1959 rockchip,pins = 1960 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1961 }; 1962 1963 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1964 rockchip,pins = 1965 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1966 }; 1967 1968 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1969 rockchip,pins = 1970 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>; 1971 }; 1972 1973 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1974 rockchip,pins = 1975 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 1976 }; 1977 1978 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1979 rockchip,pins = 1980 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 1981 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 1982 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 1983 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 1984 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 1985 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 1986 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 1987 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 1988 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 1989 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 1990 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 1991 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 1992 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 1993 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 1994 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 1995 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 1996 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 1997 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 1998 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 1999 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2000 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2001 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2002 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2003 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2004 }; 2005 2006 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2007 rockchip,pins = 2008 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2009 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2010 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2011 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2012 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2013 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2014 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2015 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2016 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2017 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2018 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2019 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2020 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2021 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2022 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2023 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2024 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2025 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2026 }; 2027 2028 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2029 rockchip,pins = 2030 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2031 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2032 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2033 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2034 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2035 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2036 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2037 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2038 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2039 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2040 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2041 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2042 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2043 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2044 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2045 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2046 }; 2047 2048 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2049 rockchip,pins = 2050 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2051 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2052 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2053 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2054 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2055 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2056 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2057 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2058 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2059 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 2060 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 2061 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2062 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2063 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2064 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2065 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2066 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2067 }; 2068 2069 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2070 rockchip,pins = 2071 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2072 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2073 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2074 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2075 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2076 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2077 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2078 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2079 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2080 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2081 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2082 }; 2083 2084 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2085 rockchip,pins = 2086 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2087 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2088 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2089 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2090 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2091 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2092 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2093 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2094 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2095 }; 2096 }; 2097 2098 pwm0 { 2099 pwm0_pin: pwm0-pin { 2100 rockchip,pins = 2101 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2102 }; 2103 }; 2104 2105 pwm1 { 2106 pwm1_pin: pwm1-pin { 2107 rockchip,pins = 2108 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2109 }; 2110 }; 2111 2112 pwm2 { 2113 pwm2_pin: pwm2-pin { 2114 rockchip,pins = 2115 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2116 }; 2117 }; 2118 2119 pwm3 { 2120 pwm3_pin: pwm3-pin { 2121 rockchip,pins = 2122 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2123 }; 2124 }; 2125 2126 pwm4 { 2127 pwm4_pin: pwm4-pin { 2128 rockchip,pins = 2129 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2130 }; 2131 }; 2132 2133 pwm5 { 2134 pwm5_pin: pwm5-pin { 2135 rockchip,pins = 2136 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2137 }; 2138 }; 2139 2140 pwm6 { 2141 pwm6_pin: pwm6-pin { 2142 rockchip,pins = 2143 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2144 }; 2145 }; 2146 2147 pwm7 { 2148 pwm7_pin: pwm7-pin { 2149 rockchip,pins = 2150 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2151 }; 2152 }; 2153 2154 gmac { 2155 rmii_pins: rmii-pins { 2156 rockchip,pins = 2157 /* mac_txen */ 2158 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2159 /* mac_txd1 */ 2160 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2161 /* mac_txd0 */ 2162 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2163 /* mac_rxd0 */ 2164 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2165 /* mac_rxd1 */ 2166 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2167 /* mac_rxer */ 2168 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2169 /* mac_rxdv */ 2170 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2171 /* mac_mdio */ 2172 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2173 /* mac_mdc */ 2174 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>, 2175 /* mac_clk */ 2176 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2177 }; 2178 }; 2179 2180 cif-m0 { 2181 cif_clkout_m0: cif-clkout-m0 { 2182 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2183 }; 2184 2185 dvp_d2d9_m0: dvp-d2d9-m0 { 2186 rockchip,pins = 2187 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2188 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2189 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2190 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2191 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2192 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2193 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2194 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2195 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2196 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2197 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2198 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2199 }; 2200 2201 dvp_d0d1_m0: dvp-d0d1-m0 { 2202 rockchip,pins = 2203 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2204 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2205 }; 2206 2207 dvp_d10d11_m0:d10-d11-m0 { 2208 rockchip,pins = 2209 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2210 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2211 }; 2212 }; 2213 2214 cif-m1 { 2215 cif_clkout_m1: cif-clkout-m1 { 2216 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2217 }; 2218 2219 dvp_d2d9_m1: dvp-d2d9-m1 { 2220 rockchip,pins = 2221 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2222 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2223 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2224 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2225 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2226 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2227 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2228 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2229 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2230 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2231 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2232 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2233 }; 2234 2235 dvp_d0d1_m1: dvp-d0d1-m1 { 2236 rockchip,pins = 2237 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2238 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2239 }; 2240 2241 dvp_d10d11_m1:d10-d11-m1 { 2242 rockchip,pins = 2243 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2244 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2245 }; 2246 }; 2247 2248 isp { 2249 isp_prelight: isp-prelight { 2250 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2251 }; 2252 }; 2253 }; 2254}; 2255