1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 dmc: dmc { 73 compatible = "rockchip,px30-dmc", "syscon"; 74 reg = <0x0 0xff2a0000 0x0 0x1000>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vopb_out>, <&vopl_out>; 80 status = "disabled"; 81 }; 82 83 firmware { 84 optee { 85 compatible = "linaro,optee-tz"; 86 method = "smc"; 87 }; 88 }; 89 90 psci { 91 compatible = "arm,psci-1.0"; 92 method = "smc"; 93 }; 94 95 timer { 96 compatible = "arm,armv8-timer"; 97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 101 }; 102 103 xin24m: xin24m { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <24000000>; 107 clock-output-names = "xin24m"; 108 }; 109 110 pmu: power-management@ff000000 { 111 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 112 reg = <0x0 0xff000000 0x0 0x1000>; 113 114 power: power-controller { 115 compatible = "rockchip,px30-power-controller"; 116 #power-domain-cells = <1>; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 status = "disabled"; 120 121 /* These power domains are grouped by VD_LOGIC */ 122 pd_usb@PX30_PD_USB { 123 reg = <PX30_PD_USB>; 124 clocks = <&cru HCLK_HOST>, 125 <&cru HCLK_OTG>, 126 <&cru SCLK_OTG_ADP>; 127 }; 128 pd_sdcard@PX30_PD_SDCARD { 129 reg = <PX30_PD_SDCARD>; 130 clocks = <&cru HCLK_SDMMC>, 131 <&cru SCLK_SDMMC>; 132 }; 133 pd_gmac@PX30_PD_GMAC { 134 reg = <PX30_PD_GMAC>; 135 clocks = <&cru ACLK_GMAC>, 136 <&cru PCLK_GMAC>, 137 <&cru SCLK_MAC_REF>, 138 <&cru SCLK_GMAC_RX_TX>; 139 }; 140 pd_mmc_nand@PX30_PD_MMC_NAND { 141 reg = <PX30_PD_MMC_NAND>; 142 clocks = <&cru HCLK_NANDC>, 143 <&cru HCLK_EMMC>, 144 <&cru HCLK_SDIO>, 145 <&cru HCLK_SFC>, 146 <&cru SCLK_EMMC>, 147 <&cru SCLK_NANDC>, 148 <&cru SCLK_SDIO>, 149 <&cru SCLK_SFC>; 150 }; 151 pd_vpu@PX30_PD_VPU { 152 reg = <PX30_PD_VPU>; 153 clocks = <&cru ACLK_VPU>, 154 <&cru HCLK_VPU>, 155 <&cru SCLK_CORE_VPU>; 156 }; 157 pd_vo@PX30_PD_VO { 158 reg = <PX30_PD_VO>; 159 clocks = <&cru ACLK_RGA>, 160 <&cru ACLK_VOPB>, 161 <&cru ACLK_VOPL>, 162 <&cru DCLK_VOPB>, 163 <&cru DCLK_VOPL>, 164 <&cru HCLK_RGA>, 165 <&cru HCLK_VOPB>, 166 <&cru HCLK_VOPL>, 167 <&cru PCLK_MIPI_DSI>, 168 <&cru SCLK_RGA_CORE>, 169 <&cru SCLK_VOPB_PWM>; 170 }; 171 pd_vi@PX30_PD_VI { 172 reg = <PX30_PD_VI>; 173 clocks = <&cru ACLK_CIF>, 174 <&cru ACLK_ISP>, 175 <&cru HCLK_CIF>, 176 <&cru HCLK_ISP>, 177 <&cru SCLK_ISP>; 178 }; 179 pd_gpu@PX30_PD_GPU { 180 reg = <PX30_PD_GPU>; 181 clocks = <&cru ACLK_GPU>; 182 }; 183 }; 184 }; 185 186 pmugrf: syscon@ff010000 { 187 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 188 reg = <0x0 0xff010000 0x0 0x1000>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 192 pmu_io_domains: io-domains { 193 compatible = "rockchip,px30-pmu-io-voltage-domain"; 194 status = "disabled"; 195 }; 196 197 reboot-mode { 198 compatible = "syscon-reboot-mode"; 199 offset = <0x200>; 200 mode-bootloader = <BOOT_BL_DOWNLOAD>; 201 mode-charge = <BOOT_CHARGING>; 202 mode-fastboot = <BOOT_FASTBOOT>; 203 mode-loader = <BOOT_BL_DOWNLOAD>; 204 mode-normal = <BOOT_NORMAL>; 205 mode-recovery = <BOOT_RECOVERY>; 206 mode-ums = <BOOT_UMS>; 207 }; 208 209 pmu_pvtm: pmu-pvtm { 210 compatible = "rockchip,px30-pmu-pvtm"; 211 clocks = <&pmucru SCLK_PVTM_PMU>; 212 clock-names = "pmu"; 213 status = "disabled"; 214 }; 215 }; 216 217 uart0: serial@ff030000 { 218 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 219 reg = <0x0 0xff030000 0x0 0x100>; 220 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 222 clock-names = "baudclk", "apb_pclk"; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 dmas = <&dmac 0>, <&dmac 1>; 226 #dma-cells = <2>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 229 status = "disabled"; 230 }; 231 232 i2s0_8ch: i2s@ff060000 { 233 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 234 reg = <0x0 0xff060000 0x0 0x1000>; 235 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 237 clock-names = "i2s_clk", "i2s_hclk"; 238 dmas = <&dmac 16>, <&dmac 17>; 239 dma-names = "tx", "rx"; 240 status = "disabled"; 241 }; 242 243 i2s1_2ch: i2s@ff070000 { 244 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 245 reg = <0x0 0xff070000 0x0 0x1000>; 246 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 248 clock-names = "i2s_clk", "i2s_hclk"; 249 dmas = <&dmac 18>, <&dmac 19>; 250 dma-names = "tx", "rx"; 251 status = "disabled"; 252 }; 253 254 i2s2_2ch: i2s@ff080000 { 255 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 256 reg = <0x0 0xff080000 0x0 0x1000>; 257 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 259 clock-names = "i2s_clk", "i2s_hclk"; 260 dmas = <&dmac 20>, <&dmac 21>; 261 dma-names = "tx", "rx"; 262 status = "disabled"; 263 }; 264 265 pdm: pdm@ff0a0000 { 266 compatible = "rockchip,pdm"; 267 reg = <0x0 0xff0a0000 0x0 0x1000>; 268 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 269 clock-names = "pdm_clk", "pdm_hclk"; 270 dmas = <&dmac 24>; 271 dma-names = "rx"; 272 status = "disabled"; 273 }; 274 275 gic: interrupt-controller@ff131000 { 276 compatible = "arm,gic-400"; 277 #interrupt-cells = <3>; 278 #address-cells = <0>; 279 interrupt-controller; 280 reg = <0x0 0xff131000 0 0x1000>, 281 <0x0 0xff132000 0 0x2000>, 282 <0x0 0xff134000 0 0x2000>, 283 <0x0 0xff136000 0 0x2000>; 284 interrupts = <GIC_PPI 9 285 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 286 }; 287 288 grf: syscon@ff140000 { 289 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 290 reg = <0x0 0xff140000 0x0 0x1000>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 294 io_domains: io-domains { 295 compatible = "rockchip,px30-io-voltage-domain"; 296 status = "disabled"; 297 }; 298 }; 299 300 core_grf: syscon@ff148000 { 301 compatible = "syscon", "simple-mfd"; 302 reg = <0x0 0xff148000 0x0 0x1000>; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 306 pvtm: pvtm { 307 compatible = "rockchip,px30-pvtm"; 308 clocks = <&cru SCLK_PVTM>; 309 clock-names = "core"; 310 status = "disabled"; 311 }; 312 }; 313 314 uart1: serial@ff158000 { 315 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 316 reg = <0x0 0xff158000 0x0 0x100>; 317 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 319 clock-names = "sclk_uart", "pclk_uart"; 320 reg-shift = <2>; 321 reg-io-width = <4>; 322 dmas = <&dmac 2>, <&dmac 3>; 323 #dma-cells = <2>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 326 status = "disabled"; 327 }; 328 329 uart2: serial@ff160000 { 330 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 331 reg = <0x0 0xff160000 0x0 0x100>; 332 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 334 clock-names = "baudclk", "apb_pclk"; 335 reg-shift = <2>; 336 reg-io-width = <4>; 337 dmas = <&dmac 4>, <&dmac 5>; 338 #dma-cells = <2>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&uart2m0_xfer>; 341 status = "disabled"; 342 }; 343 344 uart3: serial@ff168000 { 345 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 346 reg = <0x0 0xff168000 0x0 0x100>; 347 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 349 clock-names = "baudclk", "apb_pclk"; 350 reg-shift = <2>; 351 reg-io-width = <4>; 352 dmas = <&dmac 6>, <&dmac 7>; 353 #dma-cells = <2>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 356 status = "disabled"; 357 }; 358 359 uart4: serial@ff170000 { 360 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 361 reg = <0x0 0xff170000 0x0 0x100>; 362 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 364 clock-names = "baudclk", "apb_pclk"; 365 reg-shift = <2>; 366 reg-io-width = <4>; 367 dmas = <&dmac 8>, <&dmac 9>; 368 #dma-cells = <2>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 371 status = "disabled"; 372 }; 373 374 uart5: serial@ff178000 { 375 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 376 reg = <0x0 0xff178000 0x0 0x100>; 377 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 379 clock-names = "baudclk", "apb_pclk"; 380 reg-shift = <2>; 381 reg-io-width = <4>; 382 dmas = <&dmac 10>, <&dmac 11>; 383 #dma-cells = <2>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 386 status = "disabled"; 387 }; 388 389 i2c0: i2c@ff180000 { 390 compatible = "rockchip,rk3399-i2c"; 391 reg = <0x0 0xff180000 0x0 0x1000>; 392 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 393 clock-names = "i2c", "pclk"; 394 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&i2c0_xfer>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 status = "disabled"; 400 }; 401 402 i2c1: i2c@ff190000 { 403 compatible = "rockchip,rk3399-i2c"; 404 reg = <0x0 0xff190000 0x0 0x1000>; 405 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 406 clock-names = "i2c", "pclk"; 407 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c1_xfer>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 i2c2: i2c@ff1a0000 { 416 compatible = "rockchip,rk3399-i2c"; 417 reg = <0x0 0xff1a0000 0x0 0x1000>; 418 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 419 clock-names = "i2c", "pclk"; 420 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&i2c2_xfer>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c3: i2c@ff1b0000 { 429 compatible = "rockchip,rk3399-i2c"; 430 reg = <0x0 0xff1b0000 0x0 0x1000>; 431 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 432 clock-names = "i2c", "pclk"; 433 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&i2c3_xfer>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 status = "disabled"; 439 }; 440 441 spi0: spi@ff1d0000 { 442 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 443 reg = <0x0 0xff1d0000 0x0 0x1000>; 444 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 448 clock-names = "spiclk", "apb_pclk"; 449 dmas = <&dmac 12>, <&dmac 13>; 450 #dma-cells = <2>; 451 dma-names = "tx", "rx"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 454 status = "disabled"; 455 }; 456 457 spi1: spi@ff1d8000 { 458 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 459 reg = <0x0 0xff1d8000 0x0 0x1000>; 460 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 464 clock-names = "spiclk", "apb_pclk"; 465 dmas = <&dmac 14>, <&dmac 15>; 466 #dma-cells = <2>; 467 dma-names = "tx", "rx"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 470 status = "disabled"; 471 }; 472 473 wdt: watchdog@ff1e0000 { 474 compatible = "snps,dw-wdt"; 475 reg = <0x0 0xff1e0000 0x0 0x100>; 476 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 477 status = "disabled"; 478 }; 479 480 pwm0: pwm@ff200000 { 481 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 482 reg = <0x0 0xff200000 0x0 0x10>; 483 #pwm-cells = <3>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&pwm0_pin>; 486 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 487 clock-names = "pwm", "pclk"; 488 status = "disabled"; 489 }; 490 491 pwm1: pwm@ff200010 { 492 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 493 reg = <0x0 0xff200010 0x0 0x10>; 494 #pwm-cells = <3>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pwm1_pin>; 497 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 498 clock-names = "pwm", "pclk"; 499 status = "disabled"; 500 }; 501 502 pwm2: pwm@ff200020 { 503 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 504 reg = <0x0 0xff200020 0x0 0x10>; 505 #pwm-cells = <3>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&pwm2_pin>; 508 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 509 clock-names = "pwm", "pclk"; 510 status = "disabled"; 511 }; 512 513 pwm3: pwm@ff200030 { 514 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 515 reg = <0x0 0xff200030 0x0 0x10>; 516 #pwm-cells = <3>; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&pwm3_pin>; 519 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 520 clock-names = "pwm", "pclk"; 521 status = "disabled"; 522 }; 523 524 pwm4: pwm@ff208000 { 525 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 526 reg = <0x0 0xff208000 0x0 0x10>; 527 #pwm-cells = <3>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&pwm4_pin>; 530 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 531 clock-names = "pwm", "pclk"; 532 status = "disabled"; 533 }; 534 535 pwm5: pwm@ff208010 { 536 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 537 reg = <0x0 0xff208010 0x0 0x10>; 538 #pwm-cells = <3>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&pwm5_pin>; 541 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 542 clock-names = "pwm", "pclk"; 543 status = "disabled"; 544 }; 545 546 pwm6: pwm@ff208020 { 547 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 548 reg = <0x0 0xff208020 0x0 0x10>; 549 #pwm-cells = <3>; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pwm6_pin>; 552 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 553 clock-names = "pwm", "pclk"; 554 status = "disabled"; 555 }; 556 557 pwm7: pwm@ff208030 { 558 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 559 reg = <0x0 0xff208030 0x0 0x10>; 560 #pwm-cells = <3>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pwm7_pin>; 563 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 564 clock-names = "pwm", "pclk"; 565 status = "disabled"; 566 }; 567 568 amba { 569 compatible = "simple-bus"; 570 #address-cells = <2>; 571 #size-cells = <2>; 572 ranges; 573 574 dmac: dmac@ff240000 { 575 compatible = "arm,pl330", "arm,primecell"; 576 reg = <0x0 0xff240000 0x0 0x4000>; 577 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&cru ACLK_DMAC>; 580 clock-names = "apb_pclk"; 581 #dma-cells = <1>; 582 peripherals-req-type-burst; 583 }; 584 }; 585 586 tsadc: tsadc@ff280000 { 587 compatible = "rockchip,px30-tsadc"; 588 reg = <0x0 0xff280000 0x0 0x100>; 589 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 590 rockchip,grf = <&grf>; 591 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 592 clock-names = "tsadc", "apb_pclk"; 593 assigned-clocks = <&cru SCLK_TSADC>; 594 assigned-clock-rates = <50000>; 595 resets = <&cru SRST_TSADC_P>; 596 reset-names = "tsadc-apb"; 597 pinctrl-names = "init", "default", "sleep"; 598 pinctrl-0 = <&tsadc_otp_gpio>; 599 pinctrl-1 = <&tsadc_otp_out>; 600 pinctrl-2 = <&tsadc_otp_gpio>; 601 #thermal-sensor-cells = <1>; 602 rockchip,hw-tshut-temp = <100000>; 603 status = "disabled"; 604 }; 605 606 saradc: saradc@ff288000 { 607 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 608 reg = <0x0 0xff288000 0x0 0x100>; 609 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 610 #io-channel-cells = <1>; 611 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 612 clock-names = "saradc", "apb_pclk"; 613 resets = <&cru SRST_SARADC_P>; 614 reset-names = "saradc-apb"; 615 status = "disabled"; 616 }; 617 618 cru: clock-controller@ff2b0000 { 619 compatible = "rockchip,px30-cru"; 620 reg = <0x0 0xff2b0000 0x0 0x9000>; 621 rockchip,grf = <&grf>; 622 #clock-cells = <1>; 623 #reset-cells = <1>; 624 625 assigned-clocks = 626 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 627 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 628 <&cru ARMCLK>; 629 assigned-clock-rates = 630 <1608000000>, <1416000000>, 631 <1188000000>, <1188000000>, 632 <816000000>; 633 }; 634 635 pmucru: pmu-clock-controller@ff2bc000 { 636 compatible = "rockchip,px30-pmucru"; 637 reg = <0x0 0xff2bc000 0x0 0x1000>; 638 rockchip,grf = <&grf>; 639 #clock-cells = <1>; 640 #reset-cells = <1>; 641 642 assigned-clocks = 643 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 644 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 645 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 646 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 647 assigned-clock-rates = 648 <1200000000>, <100000000>, 649 <26000000>, <300000000>, 650 <300000000>, <150000000>, 651 <150000000>, <75000000>; 652 }; 653 654 usb2phy_grf: syscon@ff2c0000 { 655 compatible = "rockchip,px30-usb2phy-grf", "syscon", 656 "simple-mfd"; 657 reg = <0x0 0xff2c0000 0x0 0x10000>; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 661 u2phy: usb2-phy@100 { 662 compatible = "rockchip,px30-usb2phy", 663 "rockchip,rk3328-usb2phy"; 664 reg = <0x100 0x10>; 665 clocks = <&pmucru SCLK_USBPHY_REF>; 666 clock-names = "phyclk"; 667 #clock-cells = <0>; 668 assigned-clocks = <&cru USB480M>; 669 assigned-clock-parents = <&u2phy>; 670 clock-output-names = "usb480m_phy"; 671 status = "disabled"; 672 673 u2phy_host: host-port { 674 #phy-cells = <0>; 675 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 676 interrupt-names = "linestate"; 677 status = "disabled"; 678 }; 679 680 u2phy_otg: otg-port { 681 #phy-cells = <0>; 682 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "otg-bvalid", "otg-id", 686 "linestate"; 687 status = "disabled"; 688 }; 689 }; 690 }; 691 692 mipi_dphy: mipi-dphy@ff2e0000 { 693 compatible = "rockchip,px30-mipi-dphy"; 694 reg = <0x0 0xff2e0000 0x0 0x10000>; 695 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 696 clock-names = "ref", "pclk"; 697 clock-output-names = "mipi_dphy_pll"; 698 #clock-cells = <0>; 699 resets = <&cru SRST_MIPIDSIPHY_P>; 700 reset-names = "apb"; 701 power-domains = <&power PX30_PD_VO>; 702 #phy-cells = <0>; 703 rockchip,grf = <&grf>; 704 status = "disabled"; 705 }; 706 707 lvds: lvds@ff2e0000 { 708 compatible = "rockchip,px30-lvds"; 709 reg = <0x0 0xff2e0000 0x0 0x100>, <0x0 0xff2e0100 0x0 0x100>; 710 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 711 clocks = <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 712 clock-names = "pclk_lvds", "pclk_lvds_ctl"; 713 power-domains = <&power PX30_PD_VO>; 714 rockchip,grf = <&grf>; 715 status = "disabled"; 716 717 ports { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 port@0 { 722 reg = <0>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 726 lvds_in_vopl: endpoint@0 { 727 reg = <0>; 728 remote-endpoint = <&vopl_out_lvds>; 729 }; 730 731 lvds_in_vopb: endpoint@1 { 732 reg = <1>; 733 remote-endpoint = <&vopb_out_lvds>; 734 }; 735 }; 736 }; 737 }; 738 739 usb20_otg: usb@ff300000 { 740 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 741 "snps,dwc2"; 742 reg = <0x0 0xff300000 0x0 0x40000>; 743 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&cru HCLK_OTG>; 745 clock-names = "otg"; 746 dr_mode = "otg"; 747 g-np-tx-fifo-size = <16>; 748 g-rx-fifo-size = <275>; 749 g-tx-fifo-size = <256 128 128 64 64 32>; 750 g-use-dma; 751 phys = <&u2phy_otg>; 752 phy-names = "usb2-phy"; 753 status = "disabled"; 754 }; 755 756 usb_host0_ehci: usb@ff340000 { 757 compatible = "generic-ehci"; 758 reg = <0x0 0xff340000 0x0 0x10000>; 759 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 761 <&u2phy>; 762 clock-names = "usbhost", "arbiter", "utmi"; 763 phys = <&u2phy_host>; 764 phy-names = "usb"; 765 status = "disabled"; 766 }; 767 768 usb_host0_ohci: usb@ff350000 { 769 compatible = "generic-ohci"; 770 reg = <0x0 0xff350000 0x0 0x10000>; 771 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 773 <&u2phy>; 774 clock-names = "usbhost", "arbiter", "utmi"; 775 phys = <&u2phy_host>; 776 phy-names = "usb"; 777 }; 778 779 gmac: ethernet@ff360000 { 780 compatible = "rockchip,px30-gmac"; 781 reg = <0x0 0xff360000 0x0 0x10000>; 782 rockchip,grf = <&grf>; 783 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 784 interrupt-names = "macirq"; 785 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 786 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 787 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 788 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 789 clock-names = "stmmaceth", "mac_clk_rx", 790 "mac_clk_tx", "clk_mac_ref", 791 "clk_mac_refout", "aclk_mac", 792 "pclk_mac", "clk_mac_speed"; 793 phy-mode = "rmii"; 794 pinctrl-names = "default"; 795 pinctrl-0 = <&rmii_pins>; 796 resets = <&cru SRST_GMAC_A>; 797 reset-names = "stmmaceth"; 798 power-domains = <&power PX30_PD_GMAC>; 799 status = "disabled"; 800 }; 801 802 sdmmc: dwmmc@ff370000 { 803 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 804 reg = <0x0 0xff370000 0x0 0x4000>; 805 max-frequency = <150000000>; 806 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 807 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 808 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 809 fifo-depth = <0x100>; 810 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 811 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 814 status = "disabled"; 815 }; 816 817 sdio: dwmmc@ff380000 { 818 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 819 reg = <0x0 0xff380000 0x0 0x4000>; 820 max-frequency = <150000000>; 821 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 822 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 823 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 824 fifo-depth = <0x100>; 825 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 826 status = "disabled"; 827 }; 828 829 emmc: dwmmc@ff390000 { 830 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 831 reg = <0x0 0xff390000 0x0 0x4000>; 832 max-frequency = <150000000>; 833 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 834 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 835 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 836 fifo-depth = <0x100>; 837 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 838 status = "disabled"; 839 }; 840 841 nandc0: nandc@ff3b0000 { 842 compatible = "rockchip,rk-nandc"; 843 reg = <0x0 0xff3b0000 0x0 0x4000>; 844 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 845 nandc_id = <0>; 846 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 847 clock-names = "clk_nandc", "hclk_nandc"; 848 status = "disabled"; 849 }; 850 851 gpu: gpu@ff400000 { 852 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 853 reg = <0x0 0xff400000 0x0 0x4000>; 854 855 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 858 interrupt-names = "GPU", "MMU", "JOB"; 859 860 clocks = <&cru ACLK_GPU>; 861 clock-names = "clk_mali"; 862 863 status = "disabled"; 864 }; 865 866 hevc: hevc_service@ff440000 { 867 compatible = "rockchip,hevc_sub"; 868 iommu_enabled = <1>; 869 reg = <0x0 0xff440000 0x0 0x400>; 870 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 871 interrupt-names = "irq_dec"; 872 dev_mode = <1>; 873 iommus = <&hevc_mmu>; 874 name = "hevc_service"; 875 allocator = <1>; 876 }; 877 878 vpu: vpu_service@ff442000 { 879 compatible = "rockchip,vpu_sub"; 880 iommu_enabled = <1>; 881 reg = <0x0 0xff442000 0x0 0x800>; 882 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 884 interrupt-names = "irq_enc", "irq_dec"; 885 dev_mode = <0>; 886 iommus = <&vpu_mmu>; 887 name = "vpu_service"; 888 allocator = <1>; 889 }; 890 891 vpu_combo: vpu_combo { 892 compatible = "rockchip,vpu_combo"; 893 subcnt = <2>; 894 rockchip,grf = <&grf>; 895 rockchip,sub = <&vpu>, <&hevc>; 896 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 897 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 898 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 899 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 900 <&cru SRST_VPU_CORE>; 901 reset-names = "video_a", "video_h", "niu_a", "niu_h", 902 "video_core"; 903 mode_bit = <15>; 904 mode_ctrl = <0x410>; 905 name = "vpu_combo"; 906 status = "disabled"; 907 }; 908 909 hevc_mmu: iommu@ff440440 { 910 compatible = "rockchip,iommu"; 911 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 912 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 913 interrupt-names = "hevc_mmu"; 914 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 915 clock-names = "aclk", "hclk"; 916 #iommu-cells = <0>; 917 }; 918 919 vpu_mmu: iommu@ff442800 { 920 compatible = "rockchip,iommu"; 921 reg = <0x0 0xff442800 0x0 0x100>; 922 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 923 interrupt-names = "vpu_mmu"; 924 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 925 clock-names = "aclk", "hclk"; 926 #iommu-cells = <0>; 927 }; 928 929 dsi: dsi@ff450000 { 930 compatible = "rockchip,px30-mipi-dsi"; 931 reg = <0x0 0xff450000 0x0 0x10000>; 932 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&cru PCLK_MIPI_DSI>, <&mipi_dphy>; 934 clock-names = "pclk", "hs_clk"; 935 resets = <&cru SRST_MIPIDSI_HOST_P>; 936 reset-names = "apb"; 937 phys = <&mipi_dphy>; 938 phy-names = "mipi_dphy"; 939 power-domains = <&power PX30_PD_VO>; 940 rockchip,grf = <&grf>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 945 ports { 946 port { 947 #address-cells = <1>; 948 #size-cells = <0>; 949 950 dsi_in_vopl: endpoint@0 { 951 reg = <0>; 952 remote-endpoint = <&vopl_out_dsi>; 953 }; 954 955 dsi_in_vopb: endpoint@1 { 956 reg = <1>; 957 remote-endpoint = <&vopb_out_dsi>; 958 }; 959 }; 960 }; 961 }; 962 963 vopb: vop@ff460000 { 964 compatible = "rockchip,px30-vop-big"; 965 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 966 reg-names = "regs", "gamma_lut"; 967 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 969 <&cru HCLK_VOPB>; 970 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 971 iommus = <&vopb_mmu>; 972 status = "disabled"; 973 974 vopb_out: port { 975 #address-cells = <1>; 976 #size-cells = <0>; 977 978 vopb_out_lvds: endpoint@0 { 979 reg = <0>; 980 remote-endpoint = <&lvds_in_vopb>; 981 }; 982 983 vopb_out_dsi: endpoint@1 { 984 reg = <1>; 985 remote-endpoint = <&dsi_in_vopb>; 986 }; 987 }; 988 }; 989 990 vopb_mmu: iommu@ff460f00 { 991 compatible = "rockchip,iommu"; 992 reg = <0x0 0xff460f00 0x0 0x100>; 993 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 994 interrupt-names = "vopb_mmu"; 995 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 996 clock-names = "aclk", "hclk"; 997 #iommu-cells = <0>; 998 status = "disabled"; 999 }; 1000 1001 vopl: vop@ff470000 { 1002 compatible = "rockchip,px30-vop-lit"; 1003 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 1004 reg-names = "regs", "gamma_lut"; 1005 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1007 <&cru HCLK_VOPL>; 1008 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1009 iommus = <&vopl_mmu>; 1010 status = "disabled"; 1011 1012 vopl_out: port { 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 1016 vopl_out_lvds: endpoint@0 { 1017 reg = <0>; 1018 remote-endpoint = <&lvds_in_vopl>; 1019 }; 1020 1021 vopl_out_dsi: endpoint@1 { 1022 reg = <1>; 1023 remote-endpoint = <&dsi_in_vopl>; 1024 }; 1025 }; 1026 }; 1027 1028 vopl_mmu: iommu@ff470f00 { 1029 compatible = "rockchip,iommu"; 1030 reg = <0x0 0xff470f00 0x0 0x100>; 1031 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1032 interrupt-names = "vopl_mmu"; 1033 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1034 clock-names = "aclk", "hclk"; 1035 #iommu-cells = <0>; 1036 status = "disabled"; 1037 }; 1038 1039 rk_rga: rk_rga@ff480000 { 1040 compatible = "rockchip,rga2"; 1041 //dev_mode = <1>; 1042 reg = <0x0 0xff480000 0x0 0x1000>; 1043 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1045 clock-names = "aclk_rga", "hclk_rga"; 1046 dma-coherent; 1047 status = "disabled"; 1048 }; 1049 1050 cif: cif@ff490000 { 1051 compatible = "rockchip,cif"; 1052 reg = <0x0 0xff490000 0x0 0x200>; 1053 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1055 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1056 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1057 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1058 pinctrl-names = "cif_pin_all"; 1059 pinctrl-0 = <&dvp_d2d9_m0>; 1060 status = "disabled"; 1061 }; 1062 1063 vip_mmu: iommu@ff490800{ 1064 compatible = "rockchip,iommu"; 1065 reg = <0x0 0xff490800 0x0 0x100>; 1066 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1067 interrupt-names = "vip_mmu"; 1068 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1069 clock-names = "aclk", "hclk"; 1070 rk_iommu,disable_reset_quirk; 1071 #iommu-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 rk_isp: rk_isp@ff4a0000 { 1076 compatible = "rockchip,px30-isp", "rockchip,isp"; 1077 reg = <0x0 0xff4a0000 0x0 0x4000>; 1078 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1080 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1081 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1082 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1083 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1084 reset-names = "rst_isp", "rst_mipicsiphy"; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&cif_clkout_m0>; 1087 rockchip,isp,mipiphy = <0>; 1088 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1089 rockchip,grf = <&grf>; 1090 rockchip,cru = <&cru>; 1091 rockchip,isp,iommu-enable = <1>; 1092 iommus = <&isp_mmu>; 1093 status = "disabled"; 1094 }; 1095 1096 isp_mmu: iommu@ff4a8000 { 1097 compatible = "rockchip,iommu"; 1098 reg = <0x0 0xff4a8000 0x0 0x100>; 1099 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1100 interrupt-names = "isp_mmu"; 1101 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1102 clock-names = "aclk", "hclk"; 1103 rk_iommu,disable_reset_quirk; 1104 #iommu-cells = <0>; 1105 status = "disabled"; 1106 }; 1107 1108 qos_gmac: qos@ff518000 { 1109 compatible = "syscon"; 1110 reg = <0x0 0xff518000 0x0 0x20>; 1111 }; 1112 1113 qos_gpu: qos@ff520000 { 1114 compatible = "syscon"; 1115 reg = <0x0 0xff520000 0x0 0x20>; 1116 }; 1117 1118 qos_sdmmc: qos@ff52c000 { 1119 compatible = "syscon"; 1120 reg = <0x0 0xff52c000 0x0 0x20>; 1121 }; 1122 1123 qos_emmc: qos@ff538000 { 1124 compatible = "syscon"; 1125 reg = <0x0 0xff538000 0x0 0x20>; 1126 }; 1127 1128 qos_nand: qos@ff538080 { 1129 compatible = "syscon"; 1130 reg = <0x0 0xff538080 0x0 0x20>; 1131 }; 1132 1133 qos_sdio: qos@ff538100 { 1134 compatible = "syscon"; 1135 reg = <0x0 0xff538100 0x0 0x20>; 1136 }; 1137 1138 qos_sfc: qos@ff538180 { 1139 compatible = "syscon"; 1140 reg = <0x0 0xff538180 0x0 0x20>; 1141 }; 1142 1143 qos_usb_host: qos@ff540000 { 1144 compatible = "syscon"; 1145 reg = <0x0 0xff540000 0x0 0x20>; 1146 }; 1147 1148 qos_usb_otg: qos@ff540080 { 1149 compatible = "syscon"; 1150 reg = <0x0 0xff540080 0x0 0x20>; 1151 }; 1152 1153 qos_isp_128: qos@ff548000 { 1154 compatible = "syscon"; 1155 reg = <0x0 0xff548000 0x0 0x20>; 1156 }; 1157 1158 qos_isp_rd: qos@ff548080 { 1159 compatible = "syscon"; 1160 reg = <0x0 0xff548080 0x0 0x20>; 1161 }; 1162 1163 qos_isp_wr: qos@ff548100 { 1164 compatible = "syscon"; 1165 reg = <0x0 0xff548100 0x0 0x20>; 1166 }; 1167 1168 qos_isp_m1: qos@ff548180 { 1169 compatible = "syscon"; 1170 reg = <0x0 0xff548180 0x0 0x20>; 1171 }; 1172 1173 qos_vip: qos@ff548200 { 1174 compatible = "syscon"; 1175 reg = <0x0 0xff548200 0x0 0x20>; 1176 }; 1177 1178 qos_rga_rd: qos@ff550000 { 1179 compatible = "syscon"; 1180 reg = <0x0 0xff550000 0x0 0x20>; 1181 }; 1182 1183 qos_rga_wr: qos@ff550080 { 1184 compatible = "syscon"; 1185 reg = <0x0 0xff550080 0x0 0x20>; 1186 }; 1187 1188 qos_vop_m0: qos@ff550100 { 1189 compatible = "syscon"; 1190 reg = <0x0 0xff550100 0x0 0x20>; 1191 }; 1192 1193 qos_vop_m1: qos@ff550180 { 1194 compatible = "syscon"; 1195 reg = <0x0 0xff550180 0x0 0x20>; 1196 }; 1197 1198 qos_vpu: qos@ff558000 { 1199 compatible = "syscon"; 1200 reg = <0x0 0xff558000 0x0 0x20>; 1201 }; 1202 1203 qos_vpu_r128: qos@ff558080 { 1204 compatible = "syscon"; 1205 reg = <0x0 0xff558080 0x0 0x20>; 1206 }; 1207 1208 pinctrl: pinctrl { 1209 compatible = "rockchip,px30-pinctrl"; 1210 rockchip,grf = <&grf>; 1211 rockchip,pmu = <&pmugrf>; 1212 #address-cells = <2>; 1213 #size-cells = <2>; 1214 ranges; 1215 1216 gpio0: gpio0@ff040000 { 1217 compatible = "rockchip,gpio-bank"; 1218 reg = <0x0 0xff040000 0x0 0x100>; 1219 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&cru PCLK_GPIO0_PMU>; 1221 gpio-controller; 1222 #gpio-cells = <2>; 1223 1224 interrupt-controller; 1225 #interrupt-cells = <2>; 1226 }; 1227 1228 gpio1: gpio1@ff250000 { 1229 compatible = "rockchip,gpio-bank"; 1230 reg = <0x0 0xff250000 0x0 0x100>; 1231 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&cru PCLK_GPIO1>; 1233 gpio-controller; 1234 #gpio-cells = <2>; 1235 1236 interrupt-controller; 1237 #interrupt-cells = <2>; 1238 }; 1239 1240 gpio2: gpio2@ff260000 { 1241 compatible = "rockchip,gpio-bank"; 1242 reg = <0x0 0xff260000 0x0 0x100>; 1243 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&cru PCLK_GPIO2>; 1245 gpio-controller; 1246 #gpio-cells = <2>; 1247 1248 interrupt-controller; 1249 #interrupt-cells = <2>; 1250 }; 1251 1252 gpio3: gpio3@ff270000 { 1253 compatible = "rockchip,gpio-bank"; 1254 reg = <0x0 0xff270000 0x0 0x100>; 1255 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&cru PCLK_GPIO3>; 1257 gpio-controller; 1258 #gpio-cells = <2>; 1259 1260 interrupt-controller; 1261 #interrupt-cells = <2>; 1262 }; 1263 1264 pcfg_pull_up: pcfg-pull-up { 1265 bias-pull-up; 1266 }; 1267 1268 pcfg_pull_down: pcfg-pull-down { 1269 bias-pull-down; 1270 }; 1271 1272 pcfg_pull_none: pcfg-pull-none { 1273 bias-disable; 1274 }; 1275 1276 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1277 bias-disable; 1278 drive-strength = <2>; 1279 }; 1280 1281 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1282 bias-pull-up; 1283 drive-strength = <2>; 1284 }; 1285 1286 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1287 bias-pull-up; 1288 drive-strength = <4>; 1289 }; 1290 1291 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1292 bias-disable; 1293 drive-strength = <4>; 1294 }; 1295 1296 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1297 bias-pull-down; 1298 drive-strength = <4>; 1299 }; 1300 1301 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1302 bias-disable; 1303 drive-strength = <8>; 1304 }; 1305 1306 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1307 bias-pull-up; 1308 drive-strength = <8>; 1309 }; 1310 1311 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1312 bias-disable; 1313 drive-strength = <12>; 1314 }; 1315 1316 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1317 bias-pull-up; 1318 drive-strength = <12>; 1319 }; 1320 1321 pcfg_pull_none_smt: pcfg-pull-none-smt { 1322 bias-disable; 1323 input-schmitt-enable; 1324 }; 1325 1326 pcfg_output_high: pcfg-output-high { 1327 output-high; 1328 }; 1329 1330 pcfg_output_low: pcfg-output-low { 1331 output-low; 1332 }; 1333 1334 pcfg_input_high: pcfg-input-high { 1335 bias-pull-up; 1336 input-enable; 1337 }; 1338 1339 pcfg_input: pcfg-input { 1340 input-enable; 1341 }; 1342 1343 i2c0 { 1344 i2c0_xfer: i2c0-xfer { 1345 rockchip,pins = 1346 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1347 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1348 }; 1349 }; 1350 1351 i2c1 { 1352 i2c1_xfer: i2c1-xfer { 1353 rockchip,pins = 1354 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1355 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1356 }; 1357 }; 1358 1359 i2c2 { 1360 i2c2_xfer: i2c2-xfer { 1361 rockchip,pins = 1362 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1363 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1364 }; 1365 }; 1366 1367 i2c3 { 1368 i2c3_xfer: i2c3-xfer { 1369 rockchip,pins = 1370 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1371 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1372 }; 1373 }; 1374 1375 tsadc { 1376 tsadc_otp_gpio: tsadc-otp-gpio { 1377 rockchip,pins = 1378 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1379 }; 1380 1381 tsadc_otp_out: tsadc-otp-out { 1382 rockchip,pins = 1383 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1384 }; 1385 }; 1386 1387 uart0 { 1388 uart0_xfer: uart0-xfer { 1389 rockchip,pins = 1390 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1391 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1392 }; 1393 1394 uart0_cts: uart0-cts { 1395 rockchip,pins = 1396 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1397 }; 1398 1399 uart0_rts: uart0-rts { 1400 rockchip,pins = 1401 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1402 }; 1403 1404 uart0_rts_gpio: uart0-rts-gpio { 1405 rockchip,pins = 1406 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1407 }; 1408 }; 1409 1410 uart1 { 1411 uart1_xfer: uart1-xfer { 1412 rockchip,pins = 1413 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1414 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1415 }; 1416 1417 uart1_cts: uart1-cts { 1418 rockchip,pins = 1419 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1420 }; 1421 1422 uart1_rts: uart1-rts { 1423 rockchip,pins = 1424 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1425 }; 1426 1427 uart1_rts_gpio: uart1-rts-gpio { 1428 rockchip,pins = 1429 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1430 }; 1431 }; 1432 1433 uart2-m0 { 1434 uart2m0_xfer: uart2m0-xfer { 1435 rockchip,pins = 1436 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1437 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1438 }; 1439 }; 1440 1441 uart2-m1 { 1442 uart2m1_xfer: uart2m1-xfer { 1443 rockchip,pins = 1444 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1445 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1446 }; 1447 }; 1448 1449 uart3-m0 { 1450 uart3m0_xfer: uart3m0-xfer { 1451 rockchip,pins = 1452 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1453 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1454 }; 1455 1456 uart3m0_cts: uart3m0-cts { 1457 rockchip,pins = 1458 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1459 }; 1460 1461 uart3m0_rts: uart3m0-rts { 1462 rockchip,pins = 1463 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1464 }; 1465 1466 uart3m0_rts_gpio: uart3m0-rts-gpio { 1467 rockchip,pins = 1468 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1469 }; 1470 }; 1471 1472 uart3-m1 { 1473 uart3m1_xfer: uart3m1-xfer { 1474 rockchip,pins = 1475 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1476 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1477 }; 1478 1479 uart3m1_cts: uart3m1-cts { 1480 rockchip,pins = 1481 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1482 }; 1483 1484 uart3m1_rts: uart3m1-rts { 1485 rockchip,pins = 1486 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1487 }; 1488 1489 uart3m1_rts_gpio: uart3m1-rts-gpio { 1490 rockchip,pins = 1491 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1492 }; 1493 }; 1494 1495 uart4 { 1496 1497 uart4_xfer: uart4-xfer { 1498 rockchip,pins = 1499 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1500 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1501 }; 1502 1503 uart4_cts: uart4-cts { 1504 rockchip,pins = 1505 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1506 1507 }; 1508 1509 uart4_rts: uart4-rts { 1510 rockchip,pins = 1511 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1512 }; 1513 }; 1514 1515 uart5 { 1516 1517 uart5_xfer: uart5-xfer { 1518 rockchip,pins = 1519 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1520 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1521 }; 1522 1523 uart5_cts: uart5-cts { 1524 rockchip,pins = 1525 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1526 1527 }; 1528 1529 uart5_rts: uart5-rts { 1530 rockchip,pins = 1531 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1532 }; 1533 }; 1534 1535 spi0 { 1536 spi0_clk: spi0-clk { 1537 rockchip,pins = 1538 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1539 }; 1540 1541 spi0_csn: spi0-csn { 1542 rockchip,pins = 1543 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1544 }; 1545 1546 spi0_miso: spi0-miso { 1547 rockchip,pins = 1548 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1549 }; 1550 1551 spi0_mosi: spi0-mosi { 1552 rockchip,pins = 1553 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1554 }; 1555 }; 1556 1557 spi1 { 1558 spi1_clk: spi1-clk { 1559 rockchip,pins = 1560 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1561 }; 1562 1563 spi1_csn: spi1-csn { 1564 rockchip,pins = 1565 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1566 }; 1567 1568 spi1_miso: spi1-miso { 1569 rockchip,pins = 1570 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1571 }; 1572 1573 spi1_mosi: spi1-mosi { 1574 rockchip,pins = 1575 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1576 }; 1577 }; 1578 1579 pdm { 1580 pdm_clk0m0: pdm-clk0m0 { 1581 rockchip,pins = 1582 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1583 }; 1584 1585 pdm_clk0m1: pdm-clk0m1 { 1586 rockchip,pins = 1587 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1588 }; 1589 1590 pdm_clk1: pdm-clk1 { 1591 rockchip,pins = 1592 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1593 }; 1594 1595 pdm_sdi0m0: pdm-sdi0m0 { 1596 rockchip,pins = 1597 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1598 }; 1599 1600 pdm_sdi0m1: pdm-sdi0m1 { 1601 rockchip,pins = 1602 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1603 }; 1604 1605 pdm_sdi1: pdm-sdi1 { 1606 rockchip,pins = 1607 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1608 }; 1609 1610 pdm_sdi2: pdm-sdi2 { 1611 rockchip,pins = 1612 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1613 }; 1614 1615 pdm_sdi3: pdm-sdi3 { 1616 rockchip,pins = 1617 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1618 }; 1619 1620 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1621 rockchip,pins = 1622 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1623 }; 1624 1625 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1626 rockchip,pins = 1627 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1628 }; 1629 1630 pdm_clk1_sleep: pdm-clk1-sleep { 1631 rockchip,pins = 1632 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1633 }; 1634 1635 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1636 rockchip,pins = 1637 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1638 }; 1639 1640 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1641 rockchip,pins = 1642 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1643 }; 1644 1645 pdm_sdi1_sleep: pdm-sdi1-sleep { 1646 rockchip,pins = 1647 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1648 }; 1649 1650 pdm_sdi2_sleep: pdm-sdi2-sleep { 1651 rockchip,pins = 1652 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1653 }; 1654 1655 pdm_sdi3_sleep: pdm-sdi3-sleep { 1656 rockchip,pins = 1657 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1658 }; 1659 }; 1660 1661 i2s0 { 1662 i2s0_8ch_mclk: i2s0-8ch-mclk { 1663 rockchip,pins = 1664 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1665 }; 1666 1667 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1668 rockchip,pins = 1669 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1670 }; 1671 1672 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1673 rockchip,pins = 1674 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1675 }; 1676 1677 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1678 rockchip,pins = 1679 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1680 }; 1681 1682 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1683 rockchip,pins = 1684 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1685 }; 1686 1687 i2s0_8ch_sdo: i2s0-8ch-sdo { 1688 rockchip,pins = 1689 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1690 }; 1691 1692 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1693 rockchip,pins = 1694 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1695 }; 1696 1697 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1698 rockchip,pins = 1699 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1700 }; 1701 1702 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1703 rockchip,pins = 1704 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1705 }; 1706 1707 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1708 rockchip,pins = 1709 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1710 }; 1711 1712 i2s0_8ch_sdi: i2s0-8ch-sdi { 1713 rockchip,pins = 1714 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1715 }; 1716 1717 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1718 rockchip,pins = 1719 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1720 }; 1721 1722 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1723 rockchip,pins = 1724 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1725 }; 1726 1727 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1728 rockchip,pins = 1729 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1730 }; 1731 1732 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1733 rockchip,pins = 1734 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1735 }; 1736 }; 1737 1738 i2s1 { 1739 i2s1_2ch_mclk: i2s1-2ch-mclk { 1740 rockchip,pins = 1741 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1742 }; 1743 1744 i2s1_2ch_sclk: i2s1-2ch-sclk { 1745 rockchip,pins = 1746 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1747 }; 1748 1749 i2s1_2ch_lrck: i2s1-2ch-lrck { 1750 rockchip,pins = 1751 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1752 }; 1753 1754 i2s1_2ch_sdi: i2s1-2ch-sdi { 1755 rockchip,pins = 1756 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1757 }; 1758 1759 i2s1_2ch_sdo: i2s1-2ch-sdo { 1760 rockchip,pins = 1761 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1762 }; 1763 }; 1764 1765 i2s2 { 1766 i2s2_2ch_mclk: i2s2-2ch-mclk { 1767 rockchip,pins = 1768 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1769 }; 1770 1771 i2s2_2ch_sclk: i2s2-2ch-sclk { 1772 rockchip,pins = 1773 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1774 }; 1775 1776 i2s2_2ch_lrck: i2s2-2ch-lrck { 1777 rockchip,pins = 1778 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1779 }; 1780 1781 i2s2_2ch_sdi: i2s2-2ch-sdi { 1782 rockchip,pins = 1783 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1784 }; 1785 1786 i2s2_2ch_sdo: i2s2-2ch-sdo { 1787 rockchip,pins = 1788 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1789 }; 1790 }; 1791 1792 sdmmc { 1793 sdmmc_clk: sdmmc-clk { 1794 rockchip,pins = 1795 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_8ma>; 1796 }; 1797 1798 sdmmc_cmd: sdmmc-cmd { 1799 rockchip,pins = 1800 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_8ma>; 1801 }; 1802 1803 sdmmc_det: sdmmc-det { 1804 rockchip,pins = 1805 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>; 1806 }; 1807 1808 sdmmc_bus1: sdmmc-bus1 { 1809 rockchip,pins = 1810 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>; 1811 }; 1812 1813 sdmmc_bus4: sdmmc-bus4 { 1814 rockchip,pins = 1815 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>, 1816 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_8ma>, 1817 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_8ma>, 1818 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_8ma>; 1819 }; 1820 1821 sdmmc_gpio: sdmmc-gpio { 1822 rockchip,pins = 1823 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1824 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1825 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1826 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1827 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1828 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1829 }; 1830 }; 1831 1832 sdio { 1833 sdio_clk: sdio-clk { 1834 rockchip,pins = 1835 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1836 }; 1837 1838 sdio_cmd: sdio-cmd { 1839 rockchip,pins = 1840 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1841 }; 1842 1843 sdio_bus4: sdio-bus4 { 1844 rockchip,pins = 1845 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1846 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>, 1847 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>, 1848 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>; 1849 }; 1850 1851 sdio_gpio: sdio-gpio { 1852 rockchip,pins = 1853 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 1854 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, 1855 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, 1856 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, 1857 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, 1858 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 1859 }; 1860 }; 1861 1862 emmc { 1863 emmc_clk: emmc-clk { 1864 rockchip,pins = 1865 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1866 }; 1867 1868 emmc_cmd: emmc-cmd { 1869 rockchip,pins = 1870 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1871 }; 1872 1873 emmc_pwren: emmc-pwren { 1874 rockchip,pins = 1875 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1876 }; 1877 1878 emmc_rstnout: emmc-rstnout { 1879 rockchip,pins = 1880 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1881 }; 1882 1883 emmc_bus1: emmc-bus1 { 1884 rockchip,pins = 1885 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1886 }; 1887 1888 emmc_bus4: emmc-bus4 { 1889 rockchip,pins = 1890 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1891 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1892 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1893 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1894 }; 1895 1896 emmc_bus8: emmc-bus8 { 1897 rockchip,pins = 1898 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1899 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1900 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1901 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1902 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1903 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1904 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1905 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1906 }; 1907 }; 1908 1909 flash { 1910 flash_cs0: flash-cs0 { 1911 rockchip,pins = 1912 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1913 }; 1914 1915 flash_rdy: flash-rdy { 1916 rockchip,pins = 1917 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1918 }; 1919 1920 flash_dqs: flash-dqs { 1921 rockchip,pins = 1922 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1923 }; 1924 1925 flash_ale: flash-ale { 1926 rockchip,pins = 1927 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1928 }; 1929 1930 flash_cle: flash-cle { 1931 rockchip,pins = 1932 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1933 }; 1934 1935 flash_wrn: flash-wrn { 1936 rockchip,pins = 1937 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1938 }; 1939 1940 flash_csl: flash-csl { 1941 rockchip,pins = 1942 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 1943 }; 1944 1945 flash_rdn: flash-rdn { 1946 rockchip,pins = 1947 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 1948 }; 1949 1950 flash_bus8: flash-bus8 { 1951 rockchip,pins = 1952 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 1953 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 1954 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 1955 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 1956 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 1957 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 1958 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 1959 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 1960 }; 1961 }; 1962 1963 lcdc { 1964 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1965 rockchip,pins = 1966 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1967 }; 1968 1969 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1970 rockchip,pins = 1971 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1972 }; 1973 1974 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1975 rockchip,pins = 1976 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>; 1977 }; 1978 1979 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1980 rockchip,pins = 1981 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 1982 }; 1983 1984 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1985 rockchip,pins = 1986 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 1987 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 1988 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 1989 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 1990 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 1991 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 1992 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 1993 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 1994 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 1995 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 1996 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 1997 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 1998 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 1999 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2000 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2001 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2002 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 2003 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 2004 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2005 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2006 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2007 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2008 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2009 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2010 }; 2011 2012 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2013 rockchip,pins = 2014 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2015 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2016 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2017 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2018 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2019 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2020 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2021 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2022 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2023 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2024 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2025 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2026 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2027 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2028 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2029 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2030 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2031 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2032 }; 2033 2034 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2035 rockchip,pins = 2036 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2037 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2038 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2039 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2040 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2041 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2042 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2043 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2044 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2045 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2046 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2047 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2048 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2049 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2050 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2051 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2052 }; 2053 2054 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2055 rockchip,pins = 2056 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2057 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2058 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2059 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2060 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2061 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2062 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2063 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2064 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2065 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 2066 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 2067 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2068 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2069 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2070 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2071 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2072 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2073 }; 2074 2075 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2076 rockchip,pins = 2077 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2078 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2079 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2080 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2081 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2082 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2083 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2084 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2085 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2086 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2087 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2088 }; 2089 2090 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2091 rockchip,pins = 2092 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2093 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2094 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2095 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2096 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2097 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2098 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2099 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2100 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2101 }; 2102 }; 2103 2104 pwm0 { 2105 pwm0_pin: pwm0-pin { 2106 rockchip,pins = 2107 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2108 }; 2109 }; 2110 2111 pwm1 { 2112 pwm1_pin: pwm1-pin { 2113 rockchip,pins = 2114 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2115 }; 2116 }; 2117 2118 pwm2 { 2119 pwm2_pin: pwm2-pin { 2120 rockchip,pins = 2121 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2122 }; 2123 }; 2124 2125 pwm3 { 2126 pwm3_pin: pwm3-pin { 2127 rockchip,pins = 2128 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2129 }; 2130 }; 2131 2132 pwm4 { 2133 pwm4_pin: pwm4-pin { 2134 rockchip,pins = 2135 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2136 }; 2137 }; 2138 2139 pwm5 { 2140 pwm5_pin: pwm5-pin { 2141 rockchip,pins = 2142 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2143 }; 2144 }; 2145 2146 pwm6 { 2147 pwm6_pin: pwm6-pin { 2148 rockchip,pins = 2149 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2150 }; 2151 }; 2152 2153 pwm7 { 2154 pwm7_pin: pwm7-pin { 2155 rockchip,pins = 2156 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2157 }; 2158 }; 2159 2160 gmac { 2161 rmii_pins: rmii-pins { 2162 rockchip,pins = 2163 /* mac_txen */ 2164 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2165 /* mac_txd1 */ 2166 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2167 /* mac_txd0 */ 2168 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2169 /* mac_rxd0 */ 2170 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2171 /* mac_rxd1 */ 2172 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2173 /* mac_rxer */ 2174 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2175 /* mac_rxdv */ 2176 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2177 /* mac_mdio */ 2178 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2179 /* mac_mdc */ 2180 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>, 2181 /* mac_clk */ 2182 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2183 }; 2184 }; 2185 2186 cif-m0 { 2187 cif_clkout_m0: cif-clkout-m0 { 2188 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2189 }; 2190 2191 dvp_d2d9_m0: dvp-d2d9-m0 { 2192 rockchip,pins = 2193 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2194 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2195 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2196 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2197 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2198 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2199 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2200 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2201 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2202 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2203 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2204 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2205 }; 2206 2207 dvp_d0d1_m0: dvp-d0d1-m0 { 2208 rockchip,pins = 2209 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2210 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2211 }; 2212 2213 dvp_d10d11_m0:d10-d11-m0 { 2214 rockchip,pins = 2215 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2216 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2217 }; 2218 }; 2219 2220 cif-m1 { 2221 cif_clkout_m1: cif-clkout-m1 { 2222 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2223 }; 2224 2225 dvp_d2d9_m1: dvp-d2d9-m1 { 2226 rockchip,pins = 2227 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2228 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2229 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2230 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2231 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2232 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2233 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2234 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2235 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2236 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2237 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2238 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2239 }; 2240 2241 dvp_d0d1_m1: dvp-d0d1-m1 { 2242 rockchip,pins = 2243 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2244 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2245 }; 2246 2247 dvp_d10d11_m1:d10-d11-m1 { 2248 rockchip,pins = 2249 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2250 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2251 }; 2252 }; 2253 2254 isp { 2255 isp_prelight: isp-prelight { 2256 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2257 }; 2258 }; 2259 }; 2260}; 2261