1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 dmc: dmc { 73 compatible = "rockchip,px30-dmc", "syscon"; 74 reg = <0x0 0xff2a0000 0x0 0x1000>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vopb_out>, <&vopl_out>; 80 status = "disabled"; 81 }; 82 83 firmware { 84 optee { 85 compatible = "linaro,optee-tz"; 86 method = "smc"; 87 }; 88 }; 89 90 gmac_clkin: external-gmac-clock { 91 compatible = "fixed-clock"; 92 clock-frequency = <50000000>; 93 clock-output-names = "gmac_clkin"; 94 #clock-cells = <0>; 95 }; 96 97 psci { 98 compatible = "arm,psci-1.0"; 99 method = "smc"; 100 }; 101 102 timer { 103 compatible = "arm,armv8-timer"; 104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 108 }; 109 110 xin24m: xin24m { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <24000000>; 114 clock-output-names = "xin24m"; 115 }; 116 117 pmu: power-management@ff000000 { 118 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 119 reg = <0x0 0xff000000 0x0 0x1000>; 120 121 power: power-controller { 122 compatible = "rockchip,px30-power-controller"; 123 #power-domain-cells = <1>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* These power domains are grouped by VD_LOGIC */ 129 pd_usb@PX30_PD_USB { 130 reg = <PX30_PD_USB>; 131 clocks = <&cru HCLK_HOST>, 132 <&cru HCLK_OTG>, 133 <&cru SCLK_OTG_ADP>; 134 }; 135 pd_sdcard@PX30_PD_SDCARD { 136 reg = <PX30_PD_SDCARD>; 137 clocks = <&cru HCLK_SDMMC>, 138 <&cru SCLK_SDMMC>; 139 }; 140 pd_gmac@PX30_PD_GMAC { 141 reg = <PX30_PD_GMAC>; 142 clocks = <&cru ACLK_GMAC>, 143 <&cru PCLK_GMAC>, 144 <&cru SCLK_MAC_REF>, 145 <&cru SCLK_GMAC_RX_TX>; 146 }; 147 pd_mmc_nand@PX30_PD_MMC_NAND { 148 reg = <PX30_PD_MMC_NAND>; 149 clocks = <&cru HCLK_NANDC>, 150 <&cru HCLK_EMMC>, 151 <&cru HCLK_SDIO>, 152 <&cru HCLK_SFC>, 153 <&cru SCLK_EMMC>, 154 <&cru SCLK_NANDC>, 155 <&cru SCLK_SDIO>, 156 <&cru SCLK_SFC>; 157 }; 158 pd_vpu@PX30_PD_VPU { 159 reg = <PX30_PD_VPU>; 160 clocks = <&cru ACLK_VPU>, 161 <&cru HCLK_VPU>, 162 <&cru SCLK_CORE_VPU>; 163 }; 164 pd_vo@PX30_PD_VO { 165 reg = <PX30_PD_VO>; 166 clocks = <&cru ACLK_RGA>, 167 <&cru ACLK_VOPB>, 168 <&cru ACLK_VOPL>, 169 <&cru DCLK_VOPB>, 170 <&cru DCLK_VOPL>, 171 <&cru HCLK_RGA>, 172 <&cru HCLK_VOPB>, 173 <&cru HCLK_VOPL>, 174 <&cru PCLK_MIPI_DSI>, 175 <&cru SCLK_RGA_CORE>, 176 <&cru SCLK_VOPB_PWM>; 177 }; 178 pd_vi@PX30_PD_VI { 179 reg = <PX30_PD_VI>; 180 clocks = <&cru ACLK_CIF>, 181 <&cru ACLK_ISP>, 182 <&cru HCLK_CIF>, 183 <&cru HCLK_ISP>, 184 <&cru SCLK_ISP>; 185 }; 186 pd_gpu@PX30_PD_GPU { 187 reg = <PX30_PD_GPU>; 188 clocks = <&cru ACLK_GPU>; 189 }; 190 }; 191 }; 192 193 pmugrf: syscon@ff010000 { 194 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 195 reg = <0x0 0xff010000 0x0 0x1000>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 199 pmu_io_domains: io-domains { 200 compatible = "rockchip,px30-pmu-io-voltage-domain"; 201 status = "disabled"; 202 }; 203 204 reboot-mode { 205 compatible = "syscon-reboot-mode"; 206 offset = <0x200>; 207 mode-bootloader = <BOOT_BL_DOWNLOAD>; 208 mode-charge = <BOOT_CHARGING>; 209 mode-fastboot = <BOOT_FASTBOOT>; 210 mode-loader = <BOOT_BL_DOWNLOAD>; 211 mode-normal = <BOOT_NORMAL>; 212 mode-recovery = <BOOT_RECOVERY>; 213 mode-ums = <BOOT_UMS>; 214 }; 215 216 pmu_pvtm: pmu-pvtm { 217 compatible = "rockchip,px30-pmu-pvtm"; 218 clocks = <&pmucru SCLK_PVTM_PMU>; 219 clock-names = "pmu"; 220 status = "disabled"; 221 }; 222 }; 223 224 uart0: serial@ff030000 { 225 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 226 reg = <0x0 0xff030000 0x0 0x100>; 227 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 229 clock-names = "baudclk", "apb_pclk"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 dmas = <&dmac 0>, <&dmac 1>; 233 #dma-cells = <2>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 236 status = "disabled"; 237 }; 238 239 i2s0_8ch: i2s@ff060000 { 240 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 241 reg = <0x0 0xff060000 0x0 0x1000>; 242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 244 clock-names = "i2s_clk", "i2s_hclk"; 245 dmas = <&dmac 16>, <&dmac 17>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 i2s1_2ch: i2s@ff070000 { 251 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 252 reg = <0x0 0xff070000 0x0 0x1000>; 253 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 255 clock-names = "i2s_clk", "i2s_hclk"; 256 dmas = <&dmac 18>, <&dmac 19>; 257 dma-names = "tx", "rx"; 258 status = "disabled"; 259 }; 260 261 i2s2_2ch: i2s@ff080000 { 262 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 263 reg = <0x0 0xff080000 0x0 0x1000>; 264 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 266 clock-names = "i2s_clk", "i2s_hclk"; 267 dmas = <&dmac 20>, <&dmac 21>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 pdm: pdm@ff0a0000 { 273 compatible = "rockchip,pdm"; 274 reg = <0x0 0xff0a0000 0x0 0x1000>; 275 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 276 clock-names = "pdm_clk", "pdm_hclk"; 277 dmas = <&dmac 24>; 278 dma-names = "rx"; 279 status = "disabled"; 280 }; 281 282 crypto: crypto@ff0b0000 { 283 compatible = "rockchip,px30-crypto"; 284 reg = <0x0 0xff0b0000 0x0 0x4000>; 285 clock-names = "sclk_crypto", "apkclk_crypto"; 286 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 287 clock-frequency = <200000000>, <300000000>; 288 status = "disabled"; 289 }; 290 291 gic: interrupt-controller@ff131000 { 292 compatible = "arm,gic-400"; 293 #interrupt-cells = <3>; 294 #address-cells = <0>; 295 interrupt-controller; 296 reg = <0x0 0xff131000 0 0x1000>, 297 <0x0 0xff132000 0 0x2000>, 298 <0x0 0xff134000 0 0x2000>, 299 <0x0 0xff136000 0 0x2000>; 300 interrupts = <GIC_PPI 9 301 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 302 }; 303 304 grf: syscon@ff140000 { 305 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 306 reg = <0x0 0xff140000 0x0 0x1000>; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 310 io_domains: io-domains { 311 compatible = "rockchip,px30-io-voltage-domain"; 312 status = "disabled"; 313 }; 314 315 lvds: lvds { 316 compatible = "rockchip,px30-lvds"; 317 phys = <&video_phy>; 318 phy-names = "phy"; 319 status = "disabled"; 320 321 ports { 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 port@0 { 326 reg = <0>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 330 lvds_in_vopb: endpoint@0 { 331 reg = <0>; 332 remote-endpoint = <&vopb_out_lvds>; 333 }; 334 335 lvds_in_vopl: endpoint@1 { 336 reg = <1>; 337 remote-endpoint = <&vopl_out_lvds>; 338 }; 339 }; 340 }; 341 }; 342 343 rgb: rgb { 344 compatible = "rockchip,px30-rgb"; 345 pinctrl-names = "default", "sleep"; 346 pinctrl-0 = <&lcdc_m0_rgb_pins>; 347 pinctrl-1 = <&lcdc_m0_sleep_pins>; 348 status = "disabled"; 349 350 ports { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 354 port@0 { 355 reg = <0>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 359 rgb_in_vopb: endpoint@0 { 360 reg = <0>; 361 remote-endpoint = <&vopb_out_rgb>; 362 }; 363 364 rgb_in_vopl: endpoint@1 { 365 reg = <1>; 366 remote-endpoint = <&vopl_out_rgb>; 367 }; 368 }; 369 }; 370 }; 371 }; 372 373 core_grf: syscon@ff148000 { 374 compatible = "syscon", "simple-mfd"; 375 reg = <0x0 0xff148000 0x0 0x1000>; 376 #address-cells = <1>; 377 #size-cells = <1>; 378 379 pvtm: pvtm { 380 compatible = "rockchip,px30-pvtm"; 381 clocks = <&cru SCLK_PVTM>; 382 clock-names = "core"; 383 status = "disabled"; 384 }; 385 }; 386 387 uart1: serial@ff158000 { 388 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 389 reg = <0x0 0xff158000 0x0 0x100>; 390 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 392 clock-names = "sclk_uart", "pclk_uart"; 393 reg-shift = <2>; 394 reg-io-width = <4>; 395 dmas = <&dmac 2>, <&dmac 3>; 396 #dma-cells = <2>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 399 status = "disabled"; 400 }; 401 402 uart2: serial@ff160000 { 403 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 404 reg = <0x0 0xff160000 0x0 0x100>; 405 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 407 clock-names = "baudclk", "apb_pclk"; 408 reg-shift = <2>; 409 reg-io-width = <4>; 410 dmas = <&dmac 4>, <&dmac 5>; 411 #dma-cells = <2>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&uart2m0_xfer>; 414 status = "disabled"; 415 }; 416 417 uart3: serial@ff168000 { 418 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 419 reg = <0x0 0xff168000 0x0 0x100>; 420 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 422 clock-names = "baudclk", "apb_pclk"; 423 reg-shift = <2>; 424 reg-io-width = <4>; 425 dmas = <&dmac 6>, <&dmac 7>; 426 #dma-cells = <2>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 429 status = "disabled"; 430 }; 431 432 uart4: serial@ff170000 { 433 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 434 reg = <0x0 0xff170000 0x0 0x100>; 435 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 437 clock-names = "baudclk", "apb_pclk"; 438 reg-shift = <2>; 439 reg-io-width = <4>; 440 dmas = <&dmac 8>, <&dmac 9>; 441 #dma-cells = <2>; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 444 status = "disabled"; 445 }; 446 447 uart5: serial@ff178000 { 448 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 449 reg = <0x0 0xff178000 0x0 0x100>; 450 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 452 clock-names = "baudclk", "apb_pclk"; 453 reg-shift = <2>; 454 reg-io-width = <4>; 455 dmas = <&dmac 10>, <&dmac 11>; 456 #dma-cells = <2>; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 459 status = "disabled"; 460 }; 461 462 i2c0: i2c@ff180000 { 463 compatible = "rockchip,rk3399-i2c"; 464 reg = <0x0 0xff180000 0x0 0x1000>; 465 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 466 clock-names = "i2c", "pclk"; 467 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&i2c0_xfer>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 i2c1: i2c@ff190000 { 476 compatible = "rockchip,rk3399-i2c"; 477 reg = <0x0 0xff190000 0x0 0x1000>; 478 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 479 clock-names = "i2c", "pclk"; 480 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&i2c1_xfer>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 status = "disabled"; 486 }; 487 488 i2c2: i2c@ff1a0000 { 489 compatible = "rockchip,rk3399-i2c"; 490 reg = <0x0 0xff1a0000 0x0 0x1000>; 491 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 492 clock-names = "i2c", "pclk"; 493 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&i2c2_xfer>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 i2c3: i2c@ff1b0000 { 502 compatible = "rockchip,rk3399-i2c"; 503 reg = <0x0 0xff1b0000 0x0 0x1000>; 504 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 505 clock-names = "i2c", "pclk"; 506 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&i2c3_xfer>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 status = "disabled"; 512 }; 513 514 spi0: spi@ff1d0000 { 515 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 516 reg = <0x0 0xff1d0000 0x0 0x1000>; 517 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 521 clock-names = "spiclk", "apb_pclk"; 522 dmas = <&dmac 12>, <&dmac 13>; 523 #dma-cells = <2>; 524 dma-names = "tx", "rx"; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 527 status = "disabled"; 528 }; 529 530 spi1: spi@ff1d8000 { 531 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 532 reg = <0x0 0xff1d8000 0x0 0x1000>; 533 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 537 clock-names = "spiclk", "apb_pclk"; 538 dmas = <&dmac 14>, <&dmac 15>; 539 #dma-cells = <2>; 540 dma-names = "tx", "rx"; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 543 status = "disabled"; 544 }; 545 546 wdt: watchdog@ff1e0000 { 547 compatible = "snps,dw-wdt"; 548 reg = <0x0 0xff1e0000 0x0 0x100>; 549 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 550 status = "disabled"; 551 }; 552 553 pwm0: pwm@ff200000 { 554 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 555 reg = <0x0 0xff200000 0x0 0x10>; 556 #pwm-cells = <3>; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pwm0_pin>; 559 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 560 clock-names = "pwm", "pclk"; 561 status = "disabled"; 562 }; 563 564 pwm1: pwm@ff200010 { 565 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 566 reg = <0x0 0xff200010 0x0 0x10>; 567 #pwm-cells = <3>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pwm1_pin>; 570 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 571 clock-names = "pwm", "pclk"; 572 status = "disabled"; 573 }; 574 575 pwm2: pwm@ff200020 { 576 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 577 reg = <0x0 0xff200020 0x0 0x10>; 578 #pwm-cells = <3>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pwm2_pin>; 581 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 582 clock-names = "pwm", "pclk"; 583 status = "disabled"; 584 }; 585 586 pwm3: pwm@ff200030 { 587 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 588 reg = <0x0 0xff200030 0x0 0x10>; 589 #pwm-cells = <3>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&pwm3_pin>; 592 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 593 clock-names = "pwm", "pclk"; 594 status = "disabled"; 595 }; 596 597 pwm4: pwm@ff208000 { 598 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 599 reg = <0x0 0xff208000 0x0 0x10>; 600 #pwm-cells = <3>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pwm4_pin>; 603 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 604 clock-names = "pwm", "pclk"; 605 status = "disabled"; 606 }; 607 608 pwm5: pwm@ff208010 { 609 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 610 reg = <0x0 0xff208010 0x0 0x10>; 611 #pwm-cells = <3>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pwm5_pin>; 614 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 615 clock-names = "pwm", "pclk"; 616 status = "disabled"; 617 }; 618 619 pwm6: pwm@ff208020 { 620 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 621 reg = <0x0 0xff208020 0x0 0x10>; 622 #pwm-cells = <3>; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pwm6_pin>; 625 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 626 clock-names = "pwm", "pclk"; 627 status = "disabled"; 628 }; 629 630 pwm7: pwm@ff208030 { 631 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 632 reg = <0x0 0xff208030 0x0 0x10>; 633 #pwm-cells = <3>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pwm7_pin>; 636 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 637 clock-names = "pwm", "pclk"; 638 status = "disabled"; 639 }; 640 641 amba { 642 compatible = "simple-bus"; 643 #address-cells = <2>; 644 #size-cells = <2>; 645 ranges; 646 647 dmac: dmac@ff240000 { 648 compatible = "arm,pl330", "arm,primecell"; 649 reg = <0x0 0xff240000 0x0 0x4000>; 650 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cru ACLK_DMAC>; 653 clock-names = "apb_pclk"; 654 #dma-cells = <1>; 655 peripherals-req-type-burst; 656 }; 657 }; 658 659 tsadc: tsadc@ff280000 { 660 compatible = "rockchip,px30-tsadc"; 661 reg = <0x0 0xff280000 0x0 0x100>; 662 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 663 rockchip,grf = <&grf>; 664 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 665 clock-names = "tsadc", "apb_pclk"; 666 assigned-clocks = <&cru SCLK_TSADC>; 667 assigned-clock-rates = <50000>; 668 resets = <&cru SRST_TSADC_P>; 669 reset-names = "tsadc-apb"; 670 pinctrl-names = "init", "default", "sleep"; 671 pinctrl-0 = <&tsadc_otp_gpio>; 672 pinctrl-1 = <&tsadc_otp_out>; 673 pinctrl-2 = <&tsadc_otp_gpio>; 674 #thermal-sensor-cells = <1>; 675 rockchip,hw-tshut-temp = <100000>; 676 status = "disabled"; 677 }; 678 679 saradc: saradc@ff288000 { 680 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 681 reg = <0x0 0xff288000 0x0 0x100>; 682 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 683 #io-channel-cells = <1>; 684 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 685 clock-names = "saradc", "apb_pclk"; 686 resets = <&cru SRST_SARADC_P>; 687 reset-names = "saradc-apb"; 688 status = "disabled"; 689 }; 690 691 cru: clock-controller@ff2b0000 { 692 compatible = "rockchip,px30-cru"; 693 reg = <0x0 0xff2b0000 0x0 0x9000>; 694 rockchip,grf = <&grf>; 695 #clock-cells = <1>; 696 #reset-cells = <1>; 697 698 assigned-clocks = 699 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 700 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 701 <&cru ARMCLK>; 702 assigned-clock-rates = 703 <1608000000>, <1416000000>, 704 <1188000000>, <1188000000>, 705 <816000000>; 706 }; 707 708 pmucru: pmu-clock-controller@ff2bc000 { 709 compatible = "rockchip,px30-pmucru"; 710 reg = <0x0 0xff2bc000 0x0 0x1000>; 711 rockchip,grf = <&grf>; 712 #clock-cells = <1>; 713 #reset-cells = <1>; 714 715 assigned-clocks = 716 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 717 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 718 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 719 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 720 assigned-clock-rates = 721 <1200000000>, <100000000>, 722 <26000000>, <300000000>, 723 <300000000>, <150000000>, 724 <150000000>, <75000000>; 725 }; 726 727 usb2phy_grf: syscon@ff2c0000 { 728 compatible = "rockchip,px30-usb2phy-grf", "syscon", 729 "simple-mfd"; 730 reg = <0x0 0xff2c0000 0x0 0x10000>; 731 #address-cells = <1>; 732 #size-cells = <1>; 733 734 u2phy: usb2-phy@100 { 735 compatible = "rockchip,px30-usb2phy", 736 "rockchip,rk3328-usb2phy"; 737 reg = <0x100 0x10>; 738 clocks = <&pmucru SCLK_USBPHY_REF>; 739 clock-names = "phyclk"; 740 #clock-cells = <0>; 741 assigned-clocks = <&cru USB480M>; 742 assigned-clock-parents = <&u2phy>; 743 clock-output-names = "usb480m_phy"; 744 status = "disabled"; 745 746 u2phy_host: host-port { 747 #phy-cells = <0>; 748 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 749 interrupt-names = "linestate"; 750 status = "disabled"; 751 }; 752 753 u2phy_otg: otg-port { 754 #phy-cells = <0>; 755 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 758 interrupt-names = "otg-bvalid", "otg-id", 759 "linestate"; 760 status = "disabled"; 761 }; 762 }; 763 }; 764 765 video_phy: video-phy@ff2e0000 { 766 compatible = "rockchip,px30-video-phy"; 767 reg = <0x0 0xff2e0000 0x0 0x10000>, 768 <0x0 0xff450000 0x0 0x10000>; 769 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, 770 <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 771 clock-names = "ref", "pclk_phy", "pclk_host"; 772 #clock-cells = <0>; 773 resets = <&cru SRST_MIPIDSIPHY_P>; 774 reset-names = "rst"; 775 power-domains = <&power PX30_PD_VO>; 776 #phy-cells = <0>; 777 status = "disabled"; 778 }; 779 780 usb20_otg: usb@ff300000 { 781 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 782 "snps,dwc2"; 783 reg = <0x0 0xff300000 0x0 0x40000>; 784 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&cru HCLK_OTG>; 786 clock-names = "otg"; 787 dr_mode = "otg"; 788 g-np-tx-fifo-size = <16>; 789 g-rx-fifo-size = <275>; 790 g-tx-fifo-size = <256 128 128 64 64 32>; 791 g-use-dma; 792 phys = <&u2phy_otg>; 793 phy-names = "usb2-phy"; 794 status = "disabled"; 795 }; 796 797 usb_host0_ehci: usb@ff340000 { 798 compatible = "generic-ehci"; 799 reg = <0x0 0xff340000 0x0 0x10000>; 800 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 802 <&u2phy>; 803 clock-names = "usbhost", "arbiter", "utmi"; 804 phys = <&u2phy_host>; 805 phy-names = "usb"; 806 status = "disabled"; 807 }; 808 809 usb_host0_ohci: usb@ff350000 { 810 compatible = "generic-ohci"; 811 reg = <0x0 0xff350000 0x0 0x10000>; 812 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 814 <&u2phy>; 815 clock-names = "usbhost", "arbiter", "utmi"; 816 phys = <&u2phy_host>; 817 phy-names = "usb"; 818 }; 819 820 gmac: ethernet@ff360000 { 821 compatible = "rockchip,px30-gmac"; 822 reg = <0x0 0xff360000 0x0 0x10000>; 823 rockchip,grf = <&grf>; 824 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-names = "macirq"; 826 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 827 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 828 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 829 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 830 clock-names = "stmmaceth", "mac_clk_rx", 831 "mac_clk_tx", "clk_mac_ref", 832 "clk_mac_refout", "aclk_mac", 833 "pclk_mac", "clk_mac_speed"; 834 phy-mode = "rmii"; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 837 resets = <&cru SRST_GMAC_A>; 838 reset-names = "stmmaceth"; 839 power-domains = <&power PX30_PD_GMAC>; 840 status = "disabled"; 841 }; 842 843 sdmmc: dwmmc@ff370000 { 844 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 845 reg = <0x0 0xff370000 0x0 0x4000>; 846 max-frequency = <150000000>; 847 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 848 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 849 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 850 fifo-depth = <0x100>; 851 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 852 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 855 status = "disabled"; 856 }; 857 858 sdio: dwmmc@ff380000 { 859 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 860 reg = <0x0 0xff380000 0x0 0x4000>; 861 max-frequency = <150000000>; 862 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 863 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 864 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 865 fifo-depth = <0x100>; 866 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 867 status = "disabled"; 868 }; 869 870 emmc: dwmmc@ff390000 { 871 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 872 reg = <0x0 0xff390000 0x0 0x4000>; 873 max-frequency = <150000000>; 874 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 875 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 876 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 877 fifo-depth = <0x100>; 878 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 879 status = "disabled"; 880 }; 881 882 nandc0: nandc@ff3b0000 { 883 compatible = "rockchip,rk-nandc"; 884 reg = <0x0 0xff3b0000 0x0 0x4000>; 885 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 886 nandc_id = <0>; 887 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 888 clock-names = "clk_nandc", "hclk_nandc"; 889 status = "disabled"; 890 }; 891 892 gpu: gpu@ff400000 { 893 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 894 reg = <0x0 0xff400000 0x0 0x4000>; 895 896 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-names = "GPU", "MMU", "JOB"; 900 901 clocks = <&cru ACLK_GPU>; 902 clock-names = "clk_mali"; 903 904 status = "disabled"; 905 }; 906 907 hevc: hevc_service@ff440000 { 908 compatible = "rockchip,hevc_sub"; 909 iommu_enabled = <1>; 910 reg = <0x0 0xff440000 0x0 0x400>; 911 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 912 interrupt-names = "irq_dec"; 913 dev_mode = <1>; 914 iommus = <&hevc_mmu>; 915 name = "hevc_service"; 916 allocator = <1>; 917 }; 918 919 vpu: vpu_service@ff442000 { 920 compatible = "rockchip,vpu_sub"; 921 iommu_enabled = <1>; 922 reg = <0x0 0xff442000 0x0 0x800>; 923 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 925 interrupt-names = "irq_enc", "irq_dec"; 926 dev_mode = <0>; 927 iommus = <&vpu_mmu>; 928 name = "vpu_service"; 929 allocator = <1>; 930 }; 931 932 vpu_combo: vpu_combo { 933 compatible = "rockchip,vpu_combo"; 934 subcnt = <2>; 935 rockchip,grf = <&grf>; 936 rockchip,sub = <&vpu>, <&hevc>; 937 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 938 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 939 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 940 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 941 <&cru SRST_VPU_CORE>; 942 reset-names = "video_a", "video_h", "niu_a", "niu_h", 943 "video_core"; 944 mode_bit = <15>; 945 mode_ctrl = <0x410>; 946 name = "vpu_combo"; 947 status = "disabled"; 948 }; 949 950 hevc_mmu: iommu@ff440440 { 951 compatible = "rockchip,iommu"; 952 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 953 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 954 interrupt-names = "hevc_mmu"; 955 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 956 clock-names = "aclk", "hclk"; 957 #iommu-cells = <0>; 958 }; 959 960 vpu_mmu: iommu@ff442800 { 961 compatible = "rockchip,iommu"; 962 reg = <0x0 0xff442800 0x0 0x100>; 963 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 964 interrupt-names = "vpu_mmu"; 965 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 966 clock-names = "aclk", "hclk"; 967 #iommu-cells = <0>; 968 }; 969 970 dsi: dsi@ff450000 { 971 compatible = "rockchip,px30-mipi-dsi"; 972 reg = <0x0 0xff450000 0x0 0x10000>; 973 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&cru PCLK_MIPI_DSI>, <&video_phy>; 975 clock-names = "pclk", "hs_clk"; 976 resets = <&cru SRST_MIPIDSI_HOST_P>; 977 reset-names = "apb"; 978 phys = <&video_phy>; 979 phy-names = "mipi_dphy"; 980 power-domains = <&power PX30_PD_VO>; 981 rockchip,grf = <&grf>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 986 ports { 987 #address-cells = <1>; 988 #size-cells = <0>; 989 990 port@0 { 991 reg = <0>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 995 dsi_in_vopl: endpoint@0 { 996 reg = <0>; 997 remote-endpoint = <&vopl_out_dsi>; 998 }; 999 1000 dsi_in_vopb: endpoint@1 { 1001 reg = <1>; 1002 remote-endpoint = <&vopb_out_dsi>; 1003 }; 1004 }; 1005 }; 1006 }; 1007 1008 vopb: vop@ff460000 { 1009 compatible = "rockchip,px30-vop-big"; 1010 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 1011 reg-names = "regs", "gamma_lut"; 1012 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1014 <&cru HCLK_VOPB>; 1015 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1016 iommus = <&vopb_mmu>; 1017 status = "disabled"; 1018 1019 vopb_out: port { 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 1023 vopb_out_lvds: endpoint@0 { 1024 reg = <0>; 1025 remote-endpoint = <&lvds_in_vopb>; 1026 }; 1027 1028 vopb_out_dsi: endpoint@1 { 1029 reg = <1>; 1030 remote-endpoint = <&dsi_in_vopb>; 1031 }; 1032 1033 vopb_out_rgb: endpoint@2 { 1034 reg = <2>; 1035 remote-endpoint = <&rgb_in_vopb>; 1036 }; 1037 }; 1038 }; 1039 1040 vopb_mmu: iommu@ff460f00 { 1041 compatible = "rockchip,iommu"; 1042 reg = <0x0 0xff460f00 0x0 0x100>; 1043 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1044 interrupt-names = "vopb_mmu"; 1045 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1046 clock-names = "aclk", "hclk"; 1047 #iommu-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 vopl: vop@ff470000 { 1052 compatible = "rockchip,px30-vop-lit"; 1053 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 1054 reg-names = "regs", "gamma_lut"; 1055 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1057 <&cru HCLK_VOPL>; 1058 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1059 iommus = <&vopl_mmu>; 1060 status = "disabled"; 1061 1062 vopl_out: port { 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 1066 vopl_out_lvds: endpoint@0 { 1067 reg = <0>; 1068 remote-endpoint = <&lvds_in_vopl>; 1069 }; 1070 1071 vopl_out_dsi: endpoint@1 { 1072 reg = <1>; 1073 remote-endpoint = <&dsi_in_vopl>; 1074 }; 1075 1076 vopl_out_rgb: endpoint@2 { 1077 reg = <2>; 1078 remote-endpoint = <&rgb_in_vopl>; 1079 }; 1080 }; 1081 }; 1082 1083 vopl_mmu: iommu@ff470f00 { 1084 compatible = "rockchip,iommu"; 1085 reg = <0x0 0xff470f00 0x0 0x100>; 1086 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1087 interrupt-names = "vopl_mmu"; 1088 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1089 clock-names = "aclk", "hclk"; 1090 #iommu-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 rk_rga: rk_rga@ff480000 { 1095 compatible = "rockchip,rga2"; 1096 //dev_mode = <1>; 1097 reg = <0x0 0xff480000 0x0 0x1000>; 1098 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1100 clock-names = "aclk_rga", "hclk_rga"; 1101 dma-coherent; 1102 status = "disabled"; 1103 }; 1104 1105 cif: cif@ff490000 { 1106 compatible = "rockchip,cif"; 1107 reg = <0x0 0xff490000 0x0 0x200>; 1108 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1110 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1111 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1112 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1113 pinctrl-names = "cif_pin_all"; 1114 pinctrl-0 = <&dvp_d2d9_m0>; 1115 status = "disabled"; 1116 }; 1117 1118 vip_mmu: iommu@ff490800{ 1119 compatible = "rockchip,iommu"; 1120 reg = <0x0 0xff490800 0x0 0x100>; 1121 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1122 interrupt-names = "vip_mmu"; 1123 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1124 clock-names = "aclk", "hclk"; 1125 rk_iommu,disable_reset_quirk; 1126 #iommu-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 rk_isp: rk_isp@ff4a0000 { 1131 compatible = "rockchip,px30-isp", "rockchip,isp"; 1132 reg = <0x0 0xff4a0000 0x0 0x4000>; 1133 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1135 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1136 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1137 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1138 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1139 reset-names = "rst_isp", "rst_mipicsiphy"; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&cif_clkout_m0>; 1142 rockchip,isp,mipiphy = <0>; 1143 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1144 rockchip,grf = <&grf>; 1145 rockchip,cru = <&cru>; 1146 rockchip,isp,iommu-enable = <1>; 1147 iommus = <&isp_mmu>; 1148 status = "disabled"; 1149 }; 1150 1151 isp_mmu: iommu@ff4a8000 { 1152 compatible = "rockchip,iommu"; 1153 reg = <0x0 0xff4a8000 0x0 0x100>; 1154 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1155 interrupt-names = "isp_mmu"; 1156 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1157 clock-names = "aclk", "hclk"; 1158 rk_iommu,disable_reset_quirk; 1159 #iommu-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 qos_gmac: qos@ff518000 { 1164 compatible = "syscon"; 1165 reg = <0x0 0xff518000 0x0 0x20>; 1166 }; 1167 1168 qos_gpu: qos@ff520000 { 1169 compatible = "syscon"; 1170 reg = <0x0 0xff520000 0x0 0x20>; 1171 }; 1172 1173 qos_sdmmc: qos@ff52c000 { 1174 compatible = "syscon"; 1175 reg = <0x0 0xff52c000 0x0 0x20>; 1176 }; 1177 1178 qos_emmc: qos@ff538000 { 1179 compatible = "syscon"; 1180 reg = <0x0 0xff538000 0x0 0x20>; 1181 }; 1182 1183 qos_nand: qos@ff538080 { 1184 compatible = "syscon"; 1185 reg = <0x0 0xff538080 0x0 0x20>; 1186 }; 1187 1188 qos_sdio: qos@ff538100 { 1189 compatible = "syscon"; 1190 reg = <0x0 0xff538100 0x0 0x20>; 1191 }; 1192 1193 qos_sfc: qos@ff538180 { 1194 compatible = "syscon"; 1195 reg = <0x0 0xff538180 0x0 0x20>; 1196 }; 1197 1198 qos_usb_host: qos@ff540000 { 1199 compatible = "syscon"; 1200 reg = <0x0 0xff540000 0x0 0x20>; 1201 }; 1202 1203 qos_usb_otg: qos@ff540080 { 1204 compatible = "syscon"; 1205 reg = <0x0 0xff540080 0x0 0x20>; 1206 }; 1207 1208 qos_isp_128: qos@ff548000 { 1209 compatible = "syscon"; 1210 reg = <0x0 0xff548000 0x0 0x20>; 1211 }; 1212 1213 qos_isp_rd: qos@ff548080 { 1214 compatible = "syscon"; 1215 reg = <0x0 0xff548080 0x0 0x20>; 1216 }; 1217 1218 qos_isp_wr: qos@ff548100 { 1219 compatible = "syscon"; 1220 reg = <0x0 0xff548100 0x0 0x20>; 1221 }; 1222 1223 qos_isp_m1: qos@ff548180 { 1224 compatible = "syscon"; 1225 reg = <0x0 0xff548180 0x0 0x20>; 1226 }; 1227 1228 qos_vip: qos@ff548200 { 1229 compatible = "syscon"; 1230 reg = <0x0 0xff548200 0x0 0x20>; 1231 }; 1232 1233 qos_rga_rd: qos@ff550000 { 1234 compatible = "syscon"; 1235 reg = <0x0 0xff550000 0x0 0x20>; 1236 }; 1237 1238 qos_rga_wr: qos@ff550080 { 1239 compatible = "syscon"; 1240 reg = <0x0 0xff550080 0x0 0x20>; 1241 }; 1242 1243 qos_vop_m0: qos@ff550100 { 1244 compatible = "syscon"; 1245 reg = <0x0 0xff550100 0x0 0x20>; 1246 }; 1247 1248 qos_vop_m1: qos@ff550180 { 1249 compatible = "syscon"; 1250 reg = <0x0 0xff550180 0x0 0x20>; 1251 }; 1252 1253 qos_vpu: qos@ff558000 { 1254 compatible = "syscon"; 1255 reg = <0x0 0xff558000 0x0 0x20>; 1256 }; 1257 1258 qos_vpu_r128: qos@ff558080 { 1259 compatible = "syscon"; 1260 reg = <0x0 0xff558080 0x0 0x20>; 1261 }; 1262 1263 pinctrl: pinctrl { 1264 compatible = "rockchip,px30-pinctrl"; 1265 rockchip,grf = <&grf>; 1266 rockchip,pmu = <&pmugrf>; 1267 #address-cells = <2>; 1268 #size-cells = <2>; 1269 ranges; 1270 1271 gpio0: gpio0@ff040000 { 1272 compatible = "rockchip,gpio-bank"; 1273 reg = <0x0 0xff040000 0x0 0x100>; 1274 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&cru PCLK_GPIO0_PMU>; 1276 gpio-controller; 1277 #gpio-cells = <2>; 1278 1279 interrupt-controller; 1280 #interrupt-cells = <2>; 1281 }; 1282 1283 gpio1: gpio1@ff250000 { 1284 compatible = "rockchip,gpio-bank"; 1285 reg = <0x0 0xff250000 0x0 0x100>; 1286 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&cru PCLK_GPIO1>; 1288 gpio-controller; 1289 #gpio-cells = <2>; 1290 1291 interrupt-controller; 1292 #interrupt-cells = <2>; 1293 }; 1294 1295 gpio2: gpio2@ff260000 { 1296 compatible = "rockchip,gpio-bank"; 1297 reg = <0x0 0xff260000 0x0 0x100>; 1298 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1299 clocks = <&cru PCLK_GPIO2>; 1300 gpio-controller; 1301 #gpio-cells = <2>; 1302 1303 interrupt-controller; 1304 #interrupt-cells = <2>; 1305 }; 1306 1307 gpio3: gpio3@ff270000 { 1308 compatible = "rockchip,gpio-bank"; 1309 reg = <0x0 0xff270000 0x0 0x100>; 1310 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1311 clocks = <&cru PCLK_GPIO3>; 1312 gpio-controller; 1313 #gpio-cells = <2>; 1314 1315 interrupt-controller; 1316 #interrupt-cells = <2>; 1317 }; 1318 1319 pcfg_pull_up: pcfg-pull-up { 1320 bias-pull-up; 1321 }; 1322 1323 pcfg_pull_down: pcfg-pull-down { 1324 bias-pull-down; 1325 }; 1326 1327 pcfg_pull_none: pcfg-pull-none { 1328 bias-disable; 1329 }; 1330 1331 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1332 bias-disable; 1333 drive-strength = <2>; 1334 }; 1335 1336 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1337 bias-pull-up; 1338 drive-strength = <2>; 1339 }; 1340 1341 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1342 bias-pull-up; 1343 drive-strength = <4>; 1344 }; 1345 1346 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1347 bias-disable; 1348 drive-strength = <4>; 1349 }; 1350 1351 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1352 bias-pull-down; 1353 drive-strength = <4>; 1354 }; 1355 1356 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1357 bias-disable; 1358 drive-strength = <8>; 1359 }; 1360 1361 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1362 bias-pull-up; 1363 drive-strength = <8>; 1364 }; 1365 1366 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1367 bias-disable; 1368 drive-strength = <12>; 1369 }; 1370 1371 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1372 bias-pull-up; 1373 drive-strength = <12>; 1374 }; 1375 1376 pcfg_pull_none_smt: pcfg-pull-none-smt { 1377 bias-disable; 1378 input-schmitt-enable; 1379 }; 1380 1381 pcfg_output_high: pcfg-output-high { 1382 output-high; 1383 }; 1384 1385 pcfg_output_low: pcfg-output-low { 1386 output-low; 1387 }; 1388 1389 pcfg_input_high: pcfg-input-high { 1390 bias-pull-up; 1391 input-enable; 1392 }; 1393 1394 pcfg_input: pcfg-input { 1395 input-enable; 1396 }; 1397 1398 i2c0 { 1399 i2c0_xfer: i2c0-xfer { 1400 rockchip,pins = 1401 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1402 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1403 }; 1404 }; 1405 1406 i2c1 { 1407 i2c1_xfer: i2c1-xfer { 1408 rockchip,pins = 1409 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1410 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1411 }; 1412 }; 1413 1414 i2c2 { 1415 i2c2_xfer: i2c2-xfer { 1416 rockchip,pins = 1417 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1418 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1419 }; 1420 }; 1421 1422 i2c3 { 1423 i2c3_xfer: i2c3-xfer { 1424 rockchip,pins = 1425 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1426 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1427 }; 1428 }; 1429 1430 tsadc { 1431 tsadc_otp_gpio: tsadc-otp-gpio { 1432 rockchip,pins = 1433 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1434 }; 1435 1436 tsadc_otp_out: tsadc-otp-out { 1437 rockchip,pins = 1438 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1439 }; 1440 }; 1441 1442 uart0 { 1443 uart0_xfer: uart0-xfer { 1444 rockchip,pins = 1445 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1446 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1447 }; 1448 1449 uart0_cts: uart0-cts { 1450 rockchip,pins = 1451 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1452 }; 1453 1454 uart0_rts: uart0-rts { 1455 rockchip,pins = 1456 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1457 }; 1458 1459 uart0_rts_gpio: uart0-rts-gpio { 1460 rockchip,pins = 1461 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1462 }; 1463 }; 1464 1465 uart1 { 1466 uart1_xfer: uart1-xfer { 1467 rockchip,pins = 1468 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1469 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1470 }; 1471 1472 uart1_cts: uart1-cts { 1473 rockchip,pins = 1474 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1475 }; 1476 1477 uart1_rts: uart1-rts { 1478 rockchip,pins = 1479 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1480 }; 1481 1482 uart1_rts_gpio: uart1-rts-gpio { 1483 rockchip,pins = 1484 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1485 }; 1486 }; 1487 1488 uart2-m0 { 1489 uart2m0_xfer: uart2m0-xfer { 1490 rockchip,pins = 1491 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1492 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1493 }; 1494 }; 1495 1496 uart2-m1 { 1497 uart2m1_xfer: uart2m1-xfer { 1498 rockchip,pins = 1499 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1500 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1501 }; 1502 }; 1503 1504 uart3-m0 { 1505 uart3m0_xfer: uart3m0-xfer { 1506 rockchip,pins = 1507 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1508 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1509 }; 1510 1511 uart3m0_cts: uart3m0-cts { 1512 rockchip,pins = 1513 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1514 }; 1515 1516 uart3m0_rts: uart3m0-rts { 1517 rockchip,pins = 1518 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1519 }; 1520 1521 uart3m0_rts_gpio: uart3m0-rts-gpio { 1522 rockchip,pins = 1523 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1524 }; 1525 }; 1526 1527 uart3-m1 { 1528 uart3m1_xfer: uart3m1-xfer { 1529 rockchip,pins = 1530 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1531 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1532 }; 1533 1534 uart3m1_cts: uart3m1-cts { 1535 rockchip,pins = 1536 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1537 }; 1538 1539 uart3m1_rts: uart3m1-rts { 1540 rockchip,pins = 1541 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1542 }; 1543 1544 uart3m1_rts_gpio: uart3m1-rts-gpio { 1545 rockchip,pins = 1546 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1547 }; 1548 }; 1549 1550 uart4 { 1551 1552 uart4_xfer: uart4-xfer { 1553 rockchip,pins = 1554 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1555 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1556 }; 1557 1558 uart4_cts: uart4-cts { 1559 rockchip,pins = 1560 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1561 1562 }; 1563 1564 uart4_rts: uart4-rts { 1565 rockchip,pins = 1566 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1567 }; 1568 }; 1569 1570 uart5 { 1571 1572 uart5_xfer: uart5-xfer { 1573 rockchip,pins = 1574 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1575 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1576 }; 1577 1578 uart5_cts: uart5-cts { 1579 rockchip,pins = 1580 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1581 1582 }; 1583 1584 uart5_rts: uart5-rts { 1585 rockchip,pins = 1586 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1587 }; 1588 }; 1589 1590 spi0 { 1591 spi0_clk: spi0-clk { 1592 rockchip,pins = 1593 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1594 }; 1595 1596 spi0_csn: spi0-csn { 1597 rockchip,pins = 1598 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1599 }; 1600 1601 spi0_miso: spi0-miso { 1602 rockchip,pins = 1603 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1604 }; 1605 1606 spi0_mosi: spi0-mosi { 1607 rockchip,pins = 1608 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1609 }; 1610 }; 1611 1612 spi1 { 1613 spi1_clk: spi1-clk { 1614 rockchip,pins = 1615 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1616 }; 1617 1618 spi1_csn: spi1-csn { 1619 rockchip,pins = 1620 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1621 }; 1622 1623 spi1_miso: spi1-miso { 1624 rockchip,pins = 1625 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1626 }; 1627 1628 spi1_mosi: spi1-mosi { 1629 rockchip,pins = 1630 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1631 }; 1632 }; 1633 1634 pdm { 1635 pdm_clk0m0: pdm-clk0m0 { 1636 rockchip,pins = 1637 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1638 }; 1639 1640 pdm_clk0m1: pdm-clk0m1 { 1641 rockchip,pins = 1642 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1643 }; 1644 1645 pdm_clk1: pdm-clk1 { 1646 rockchip,pins = 1647 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1648 }; 1649 1650 pdm_sdi0m0: pdm-sdi0m0 { 1651 rockchip,pins = 1652 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1653 }; 1654 1655 pdm_sdi0m1: pdm-sdi0m1 { 1656 rockchip,pins = 1657 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1658 }; 1659 1660 pdm_sdi1: pdm-sdi1 { 1661 rockchip,pins = 1662 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1663 }; 1664 1665 pdm_sdi2: pdm-sdi2 { 1666 rockchip,pins = 1667 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1668 }; 1669 1670 pdm_sdi3: pdm-sdi3 { 1671 rockchip,pins = 1672 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1673 }; 1674 1675 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1676 rockchip,pins = 1677 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1678 }; 1679 1680 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1681 rockchip,pins = 1682 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1683 }; 1684 1685 pdm_clk1_sleep: pdm-clk1-sleep { 1686 rockchip,pins = 1687 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1688 }; 1689 1690 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1691 rockchip,pins = 1692 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1693 }; 1694 1695 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1696 rockchip,pins = 1697 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1698 }; 1699 1700 pdm_sdi1_sleep: pdm-sdi1-sleep { 1701 rockchip,pins = 1702 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1703 }; 1704 1705 pdm_sdi2_sleep: pdm-sdi2-sleep { 1706 rockchip,pins = 1707 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1708 }; 1709 1710 pdm_sdi3_sleep: pdm-sdi3-sleep { 1711 rockchip,pins = 1712 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1713 }; 1714 }; 1715 1716 i2s0 { 1717 i2s0_8ch_mclk: i2s0-8ch-mclk { 1718 rockchip,pins = 1719 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1720 }; 1721 1722 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1723 rockchip,pins = 1724 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1725 }; 1726 1727 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1728 rockchip,pins = 1729 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1730 }; 1731 1732 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1733 rockchip,pins = 1734 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1735 }; 1736 1737 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1738 rockchip,pins = 1739 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1740 }; 1741 1742 i2s0_8ch_sdo: i2s0-8ch-sdo { 1743 rockchip,pins = 1744 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1745 }; 1746 1747 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1748 rockchip,pins = 1749 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1750 }; 1751 1752 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1753 rockchip,pins = 1754 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1755 }; 1756 1757 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1758 rockchip,pins = 1759 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1760 }; 1761 1762 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1763 rockchip,pins = 1764 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1765 }; 1766 1767 i2s0_8ch_sdi: i2s0-8ch-sdi { 1768 rockchip,pins = 1769 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1770 }; 1771 1772 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1773 rockchip,pins = 1774 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1775 }; 1776 1777 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1778 rockchip,pins = 1779 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1780 }; 1781 1782 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1783 rockchip,pins = 1784 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1785 }; 1786 1787 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1788 rockchip,pins = 1789 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1790 }; 1791 }; 1792 1793 i2s1 { 1794 i2s1_2ch_mclk: i2s1-2ch-mclk { 1795 rockchip,pins = 1796 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1797 }; 1798 1799 i2s1_2ch_sclk: i2s1-2ch-sclk { 1800 rockchip,pins = 1801 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1802 }; 1803 1804 i2s1_2ch_lrck: i2s1-2ch-lrck { 1805 rockchip,pins = 1806 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1807 }; 1808 1809 i2s1_2ch_sdi: i2s1-2ch-sdi { 1810 rockchip,pins = 1811 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1812 }; 1813 1814 i2s1_2ch_sdo: i2s1-2ch-sdo { 1815 rockchip,pins = 1816 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1817 }; 1818 }; 1819 1820 i2s2 { 1821 i2s2_2ch_mclk: i2s2-2ch-mclk { 1822 rockchip,pins = 1823 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1824 }; 1825 1826 i2s2_2ch_sclk: i2s2-2ch-sclk { 1827 rockchip,pins = 1828 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1829 }; 1830 1831 i2s2_2ch_lrck: i2s2-2ch-lrck { 1832 rockchip,pins = 1833 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1834 }; 1835 1836 i2s2_2ch_sdi: i2s2-2ch-sdi { 1837 rockchip,pins = 1838 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1839 }; 1840 1841 i2s2_2ch_sdo: i2s2-2ch-sdo { 1842 rockchip,pins = 1843 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1844 }; 1845 }; 1846 1847 sdmmc { 1848 sdmmc_clk: sdmmc-clk { 1849 rockchip,pins = 1850 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_8ma>; 1851 }; 1852 1853 sdmmc_cmd: sdmmc-cmd { 1854 rockchip,pins = 1855 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_8ma>; 1856 }; 1857 1858 sdmmc_det: sdmmc-det { 1859 rockchip,pins = 1860 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>; 1861 }; 1862 1863 sdmmc_bus1: sdmmc-bus1 { 1864 rockchip,pins = 1865 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>; 1866 }; 1867 1868 sdmmc_bus4: sdmmc-bus4 { 1869 rockchip,pins = 1870 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>, 1871 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_8ma>, 1872 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_8ma>, 1873 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_8ma>; 1874 }; 1875 1876 sdmmc_gpio: sdmmc-gpio { 1877 rockchip,pins = 1878 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1879 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1880 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1881 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1882 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1883 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1884 }; 1885 }; 1886 1887 sdio { 1888 sdio_clk: sdio-clk { 1889 rockchip,pins = 1890 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1891 }; 1892 1893 sdio_cmd: sdio-cmd { 1894 rockchip,pins = 1895 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1896 }; 1897 1898 sdio_bus4: sdio-bus4 { 1899 rockchip,pins = 1900 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1901 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>, 1902 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>, 1903 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>; 1904 }; 1905 1906 sdio_gpio: sdio-gpio { 1907 rockchip,pins = 1908 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 1909 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, 1910 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, 1911 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, 1912 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, 1913 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 1914 }; 1915 }; 1916 1917 emmc { 1918 emmc_clk: emmc-clk { 1919 rockchip,pins = 1920 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1921 }; 1922 1923 emmc_cmd: emmc-cmd { 1924 rockchip,pins = 1925 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1926 }; 1927 1928 emmc_pwren: emmc-pwren { 1929 rockchip,pins = 1930 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1931 }; 1932 1933 emmc_rstnout: emmc-rstnout { 1934 rockchip,pins = 1935 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1936 }; 1937 1938 emmc_bus1: emmc-bus1 { 1939 rockchip,pins = 1940 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1941 }; 1942 1943 emmc_bus4: emmc-bus4 { 1944 rockchip,pins = 1945 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1946 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1947 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1948 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1949 }; 1950 1951 emmc_bus8: emmc-bus8 { 1952 rockchip,pins = 1953 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1954 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1955 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1956 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1957 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1958 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1959 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1960 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1961 }; 1962 }; 1963 1964 flash { 1965 flash_cs0: flash-cs0 { 1966 rockchip,pins = 1967 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1968 }; 1969 1970 flash_rdy: flash-rdy { 1971 rockchip,pins = 1972 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1973 }; 1974 1975 flash_dqs: flash-dqs { 1976 rockchip,pins = 1977 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1978 }; 1979 1980 flash_ale: flash-ale { 1981 rockchip,pins = 1982 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1983 }; 1984 1985 flash_cle: flash-cle { 1986 rockchip,pins = 1987 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1988 }; 1989 1990 flash_wrn: flash-wrn { 1991 rockchip,pins = 1992 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1993 }; 1994 1995 flash_csl: flash-csl { 1996 rockchip,pins = 1997 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 1998 }; 1999 2000 flash_rdn: flash-rdn { 2001 rockchip,pins = 2002 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2003 }; 2004 2005 flash_bus8: flash-bus8 { 2006 rockchip,pins = 2007 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 2008 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 2009 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 2010 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 2011 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 2012 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 2013 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 2014 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 2015 }; 2016 }; 2017 2018 lcdc { 2019 lcdc_m0_rgb_pins: lcdc-m0-rgb-pins { 2020 rockchip,pins = 2021 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 2022 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_HSYNC */ 2023 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_VSYNC */ 2024 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DEN */ 2025 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 2026 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D1 */ 2027 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 2028 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D3 */ 2029 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D4 */ 2030 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D5 */ 2031 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 2032 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 2033 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D8 */ 2034 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 2035 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D10 */ 2036 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D11 */ 2037 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 2038 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 2039 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 2040 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 2041 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 2042 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 2043 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 2044 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 2045 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 2046 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 2047 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 2048 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ 2049 }; 2050 2051 lcdc_m0_sleep_pins: lcdc-m0-sleep-pins { 2052 rockchip,pins = 2053 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 2054 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ 2055 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ 2056 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ 2057 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 2058 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D1 */ 2059 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 2060 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D3 */ 2061 <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D4 */ 2062 <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D5 */ 2063 <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 2064 <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 2065 <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D8 */ 2066 <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 2067 <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ 2068 <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ 2069 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 2070 <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 2071 <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 2072 <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 2073 <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 2074 <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 2075 <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 2076 <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 2077 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 2078 <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 2079 <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 2080 <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ 2081 }; 2082 }; 2083 2084 pwm0 { 2085 pwm0_pin: pwm0-pin { 2086 rockchip,pins = 2087 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2088 }; 2089 }; 2090 2091 pwm1 { 2092 pwm1_pin: pwm1-pin { 2093 rockchip,pins = 2094 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2095 }; 2096 }; 2097 2098 pwm2 { 2099 pwm2_pin: pwm2-pin { 2100 rockchip,pins = 2101 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2102 }; 2103 }; 2104 2105 pwm3 { 2106 pwm3_pin: pwm3-pin { 2107 rockchip,pins = 2108 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2109 }; 2110 }; 2111 2112 pwm4 { 2113 pwm4_pin: pwm4-pin { 2114 rockchip,pins = 2115 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2116 }; 2117 }; 2118 2119 pwm5 { 2120 pwm5_pin: pwm5-pin { 2121 rockchip,pins = 2122 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2123 }; 2124 }; 2125 2126 pwm6 { 2127 pwm6_pin: pwm6-pin { 2128 rockchip,pins = 2129 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2130 }; 2131 }; 2132 2133 pwm7 { 2134 pwm7_pin: pwm7-pin { 2135 rockchip,pins = 2136 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2137 }; 2138 }; 2139 2140 gmac { 2141 rmii_pins: rmii-pins { 2142 rockchip,pins = 2143 /* mac_txen */ 2144 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2145 /* mac_txd1 */ 2146 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2147 /* mac_txd0 */ 2148 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2149 /* mac_rxd0 */ 2150 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2151 /* mac_rxd1 */ 2152 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2153 /* mac_rxer */ 2154 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2155 /* mac_rxdv */ 2156 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2157 /* mac_mdio */ 2158 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2159 /* mac_mdc */ 2160 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2161 }; 2162 2163 mac_refclk_12ma: mac-refclk-12ma { 2164 rockchip,pins = 2165 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none_12ma>; 2166 }; 2167 2168 mac_refclk: mac-refclk { 2169 rockchip,pins = 2170 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2171 }; 2172 }; 2173 2174 cif-m0 { 2175 cif_clkout_m0: cif-clkout-m0 { 2176 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2177 }; 2178 2179 dvp_d2d9_m0: dvp-d2d9-m0 { 2180 rockchip,pins = 2181 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2182 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2183 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2184 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2185 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2186 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2187 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2188 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2189 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2190 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2191 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2192 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2193 }; 2194 2195 dvp_d0d1_m0: dvp-d0d1-m0 { 2196 rockchip,pins = 2197 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2198 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2199 }; 2200 2201 dvp_d10d11_m0:d10-d11-m0 { 2202 rockchip,pins = 2203 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2204 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2205 }; 2206 }; 2207 2208 cif-m1 { 2209 cif_clkout_m1: cif-clkout-m1 { 2210 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2211 }; 2212 2213 dvp_d2d9_m1: dvp-d2d9-m1 { 2214 rockchip,pins = 2215 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2216 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2217 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2218 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2219 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2220 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2221 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2222 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2223 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2224 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2225 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2226 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2227 }; 2228 2229 dvp_d0d1_m1: dvp-d0d1-m1 { 2230 rockchip,pins = 2231 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2232 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2233 }; 2234 2235 dvp_d10d11_m1:d10-d11-m1 { 2236 rockchip,pins = 2237 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2238 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2239 }; 2240 }; 2241 2242 isp { 2243 isp_prelight: isp-prelight { 2244 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2245 }; 2246 }; 2247 }; 2248}; 2249