1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 dmc: dmc { 73 compatible = "rockchip,px30-dmc", "syscon"; 74 reg = <0x0 0xff2a0000 0x0 0x1000>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vopb_out>, <&vopl_out>; 80 status = "disabled"; 81 }; 82 83 firmware { 84 optee { 85 compatible = "linaro,optee-tz"; 86 method = "smc"; 87 }; 88 }; 89 90 psci { 91 compatible = "arm,psci-1.0"; 92 method = "smc"; 93 }; 94 95 timer { 96 compatible = "arm,armv8-timer"; 97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 101 }; 102 103 xin24m: xin24m { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <24000000>; 107 clock-output-names = "xin24m"; 108 }; 109 110 pmu: power-management@ff000000 { 111 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 112 reg = <0x0 0xff000000 0x0 0x1000>; 113 114 power: power-controller { 115 compatible = "rockchip,px30-power-controller"; 116 #power-domain-cells = <1>; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 status = "disabled"; 120 121 /* These power domains are grouped by VD_LOGIC */ 122 pd_usb@PX30_PD_USB { 123 reg = <PX30_PD_USB>; 124 clocks = <&cru HCLK_HOST>, 125 <&cru HCLK_OTG>, 126 <&cru SCLK_OTG_ADP>; 127 }; 128 pd_sdcard@PX30_PD_SDCARD { 129 reg = <PX30_PD_SDCARD>; 130 clocks = <&cru HCLK_SDMMC>, 131 <&cru SCLK_SDMMC>; 132 }; 133 pd_gmac@PX30_PD_GMAC { 134 reg = <PX30_PD_GMAC>; 135 clocks = <&cru ACLK_GMAC>, 136 <&cru PCLK_GMAC>, 137 <&cru SCLK_MAC_REF>, 138 <&cru SCLK_GMAC_RX_TX>; 139 }; 140 pd_mmc_nand@PX30_PD_MMC_NAND { 141 reg = <PX30_PD_MMC_NAND>; 142 clocks = <&cru HCLK_NANDC>, 143 <&cru HCLK_EMMC>, 144 <&cru HCLK_SDIO>, 145 <&cru HCLK_SFC>, 146 <&cru SCLK_EMMC>, 147 <&cru SCLK_NANDC>, 148 <&cru SCLK_SDIO>, 149 <&cru SCLK_SFC>; 150 }; 151 pd_vpu@PX30_PD_VPU { 152 reg = <PX30_PD_VPU>; 153 clocks = <&cru ACLK_VPU>, 154 <&cru HCLK_VPU>, 155 <&cru SCLK_CORE_VPU>; 156 }; 157 pd_vo@PX30_PD_VO { 158 reg = <PX30_PD_VO>; 159 clocks = <&cru ACLK_RGA>, 160 <&cru ACLK_VOPB>, 161 <&cru ACLK_VOPL>, 162 <&cru DCLK_VOPB>, 163 <&cru DCLK_VOPL>, 164 <&cru HCLK_RGA>, 165 <&cru HCLK_VOPB>, 166 <&cru HCLK_VOPL>, 167 <&cru PCLK_MIPI_DSI>, 168 <&cru SCLK_RGA_CORE>, 169 <&cru SCLK_VOPB_PWM>; 170 }; 171 pd_vi@PX30_PD_VI { 172 reg = <PX30_PD_VI>; 173 clocks = <&cru ACLK_CIF>, 174 <&cru ACLK_ISP>, 175 <&cru HCLK_CIF>, 176 <&cru HCLK_ISP>, 177 <&cru SCLK_ISP>; 178 }; 179 pd_gpu@PX30_PD_GPU { 180 reg = <PX30_PD_GPU>; 181 clocks = <&cru ACLK_GPU>; 182 }; 183 }; 184 }; 185 186 pmugrf: syscon@ff010000 { 187 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 188 reg = <0x0 0xff010000 0x0 0x1000>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 192 pmu_io_domains: io-domains { 193 compatible = "rockchip,px30-pmu-io-voltage-domain"; 194 status = "disabled"; 195 }; 196 197 reboot-mode { 198 compatible = "syscon-reboot-mode"; 199 offset = <0x200>; 200 mode-bootloader = <BOOT_BL_DOWNLOAD>; 201 mode-charge = <BOOT_CHARGING>; 202 mode-fastboot = <BOOT_FASTBOOT>; 203 mode-loader = <BOOT_BL_DOWNLOAD>; 204 mode-normal = <BOOT_NORMAL>; 205 mode-recovery = <BOOT_RECOVERY>; 206 mode-ums = <BOOT_UMS>; 207 }; 208 209 pmu_pvtm: pmu-pvtm { 210 compatible = "rockchip,px30-pmu-pvtm"; 211 clocks = <&pmucru SCLK_PVTM_PMU>; 212 clock-names = "pmu"; 213 status = "disabled"; 214 }; 215 }; 216 217 uart0: serial@ff030000 { 218 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 219 reg = <0x0 0xff030000 0x0 0x100>; 220 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 222 clock-names = "baudclk", "apb_pclk"; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 dmas = <&dmac 0>, <&dmac 1>; 226 #dma-cells = <2>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 229 status = "disabled"; 230 }; 231 232 i2s0_8ch: i2s@ff060000 { 233 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 234 reg = <0x0 0xff060000 0x0 0x1000>; 235 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 237 clock-names = "i2s_clk", "i2s_hclk"; 238 dmas = <&dmac 16>, <&dmac 17>; 239 dma-names = "tx", "rx"; 240 status = "disabled"; 241 }; 242 243 i2s1_2ch: i2s@ff070000 { 244 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 245 reg = <0x0 0xff070000 0x0 0x1000>; 246 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 248 clock-names = "i2s_clk", "i2s_hclk"; 249 dmas = <&dmac 18>, <&dmac 19>; 250 dma-names = "tx", "rx"; 251 status = "disabled"; 252 }; 253 254 i2s2_2ch: i2s@ff080000 { 255 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 256 reg = <0x0 0xff080000 0x0 0x1000>; 257 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 259 clock-names = "i2s_clk", "i2s_hclk"; 260 dmas = <&dmac 20>, <&dmac 21>; 261 dma-names = "tx", "rx"; 262 status = "disabled"; 263 }; 264 265 pdm: pdm@ff0a0000 { 266 compatible = "rockchip,pdm"; 267 reg = <0x0 0xff0a0000 0x0 0x1000>; 268 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 269 clock-names = "pdm_clk", "pdm_hclk"; 270 dmas = <&dmac 24>; 271 dma-names = "rx"; 272 status = "disabled"; 273 }; 274 275 gic: interrupt-controller@ff131000 { 276 compatible = "arm,gic-400"; 277 #interrupt-cells = <3>; 278 #address-cells = <0>; 279 interrupt-controller; 280 reg = <0x0 0xff131000 0 0x1000>, 281 <0x0 0xff132000 0 0x2000>, 282 <0x0 0xff134000 0 0x2000>, 283 <0x0 0xff136000 0 0x2000>; 284 interrupts = <GIC_PPI 9 285 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 286 }; 287 288 grf: syscon@ff140000 { 289 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 290 reg = <0x0 0xff140000 0x0 0x1000>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 294 io_domains: io-domains { 295 compatible = "rockchip,px30-io-voltage-domain"; 296 status = "disabled"; 297 }; 298 }; 299 300 core_grf: syscon@ff148000 { 301 compatible = "syscon", "simple-mfd"; 302 reg = <0x0 0xff148000 0x0 0x1000>; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 306 pvtm: pvtm { 307 compatible = "rockchip,px30-pvtm"; 308 clocks = <&cru SCLK_PVTM>; 309 clock-names = "core"; 310 status = "disabled"; 311 }; 312 }; 313 314 uart1: serial@ff158000 { 315 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 316 reg = <0x0 0xff158000 0x0 0x100>; 317 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 319 clock-names = "sclk_uart", "pclk_uart"; 320 reg-shift = <2>; 321 reg-io-width = <4>; 322 dmas = <&dmac 2>, <&dmac 3>; 323 #dma-cells = <2>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 326 status = "disabled"; 327 }; 328 329 uart2: serial@ff160000 { 330 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 331 reg = <0x0 0xff160000 0x0 0x100>; 332 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 334 clock-names = "baudclk", "apb_pclk"; 335 reg-shift = <2>; 336 reg-io-width = <4>; 337 dmas = <&dmac 4>, <&dmac 5>; 338 #dma-cells = <2>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&uart2m0_xfer>; 341 status = "disabled"; 342 }; 343 344 uart3: serial@ff168000 { 345 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 346 reg = <0x0 0xff168000 0x0 0x100>; 347 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 349 clock-names = "baudclk", "apb_pclk"; 350 reg-shift = <2>; 351 reg-io-width = <4>; 352 dmas = <&dmac 6>, <&dmac 7>; 353 #dma-cells = <2>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 356 status = "disabled"; 357 }; 358 359 uart4: serial@ff170000 { 360 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 361 reg = <0x0 0xff170000 0x0 0x100>; 362 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 364 clock-names = "baudclk", "apb_pclk"; 365 reg-shift = <2>; 366 reg-io-width = <4>; 367 dmas = <&dmac 8>, <&dmac 9>; 368 #dma-cells = <2>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 371 status = "disabled"; 372 }; 373 374 uart5: serial@ff178000 { 375 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 376 reg = <0x0 0xff178000 0x0 0x100>; 377 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 379 clock-names = "baudclk", "apb_pclk"; 380 reg-shift = <2>; 381 reg-io-width = <4>; 382 dmas = <&dmac 10>, <&dmac 11>; 383 #dma-cells = <2>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 386 status = "disabled"; 387 }; 388 389 i2c0: i2c@ff180000 { 390 compatible = "rockchip,rk3399-i2c"; 391 reg = <0x0 0xff180000 0x0 0x1000>; 392 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 393 clock-names = "i2c", "pclk"; 394 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&i2c0_xfer>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 status = "disabled"; 400 }; 401 402 i2c1: i2c@ff190000 { 403 compatible = "rockchip,rk3399-i2c"; 404 reg = <0x0 0xff190000 0x0 0x1000>; 405 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 406 clock-names = "i2c", "pclk"; 407 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c1_xfer>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 i2c2: i2c@ff1a0000 { 416 compatible = "rockchip,rk3399-i2c"; 417 reg = <0x0 0xff1a0000 0x0 0x1000>; 418 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 419 clock-names = "i2c", "pclk"; 420 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&i2c2_xfer>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c3: i2c@ff1b0000 { 429 compatible = "rockchip,rk3399-i2c"; 430 reg = <0x0 0xff1b0000 0x0 0x1000>; 431 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 432 clock-names = "i2c", "pclk"; 433 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&i2c3_xfer>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 status = "disabled"; 439 }; 440 441 spi0: spi@ff1d0000 { 442 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 443 reg = <0x0 0xff1d0000 0x0 0x1000>; 444 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 448 clock-names = "spiclk", "apb_pclk"; 449 dmas = <&dmac 12>, <&dmac 13>; 450 #dma-cells = <2>; 451 dma-names = "tx", "rx"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 454 status = "disabled"; 455 }; 456 457 spi1: spi@ff1d8000 { 458 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 459 reg = <0x0 0xff1d8000 0x0 0x1000>; 460 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 464 clock-names = "spiclk", "apb_pclk"; 465 dmas = <&dmac 14>, <&dmac 15>; 466 #dma-cells = <2>; 467 dma-names = "tx", "rx"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 470 status = "disabled"; 471 }; 472 473 wdt: watchdog@ff1e0000 { 474 compatible = "snps,dw-wdt"; 475 reg = <0x0 0xff1e0000 0x0 0x100>; 476 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 477 status = "disabled"; 478 }; 479 480 pwm0: pwm@ff200000 { 481 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 482 reg = <0x0 0xff200000 0x0 0x10>; 483 #pwm-cells = <3>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&pwm0_pin>; 486 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 487 clock-names = "pwm", "pclk"; 488 status = "disabled"; 489 }; 490 491 pwm1: pwm@ff200010 { 492 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 493 reg = <0x0 0xff200010 0x0 0x10>; 494 #pwm-cells = <3>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pwm1_pin>; 497 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 498 clock-names = "pwm", "pclk"; 499 status = "disabled"; 500 }; 501 502 pwm2: pwm@ff200020 { 503 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 504 reg = <0x0 0xff200020 0x0 0x10>; 505 #pwm-cells = <3>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&pwm2_pin>; 508 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 509 clock-names = "pwm", "pclk"; 510 status = "disabled"; 511 }; 512 513 pwm3: pwm@ff200030 { 514 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 515 reg = <0x0 0xff200030 0x0 0x10>; 516 #pwm-cells = <3>; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&pwm3_pin>; 519 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 520 clock-names = "pwm", "pclk"; 521 status = "disabled"; 522 }; 523 524 pwm4: pwm@ff208000 { 525 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 526 reg = <0x0 0xff208000 0x0 0x10>; 527 #pwm-cells = <3>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&pwm4_pin>; 530 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 531 clock-names = "pwm", "pclk"; 532 status = "disabled"; 533 }; 534 535 pwm5: pwm@ff208010 { 536 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 537 reg = <0x0 0xff208010 0x0 0x10>; 538 #pwm-cells = <3>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&pwm5_pin>; 541 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 542 clock-names = "pwm", "pclk"; 543 status = "disabled"; 544 }; 545 546 pwm6: pwm@ff208020 { 547 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 548 reg = <0x0 0xff208020 0x0 0x10>; 549 #pwm-cells = <3>; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pwm6_pin>; 552 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 553 clock-names = "pwm", "pclk"; 554 status = "disabled"; 555 }; 556 557 pwm7: pwm@ff208030 { 558 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 559 reg = <0x0 0xff208030 0x0 0x10>; 560 #pwm-cells = <3>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pwm7_pin>; 563 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 564 clock-names = "pwm", "pclk"; 565 status = "disabled"; 566 }; 567 568 amba { 569 compatible = "simple-bus"; 570 #address-cells = <2>; 571 #size-cells = <2>; 572 ranges; 573 574 dmac: dmac@ff240000 { 575 compatible = "arm,pl330", "arm,primecell"; 576 reg = <0x0 0xff240000 0x0 0x4000>; 577 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&cru ACLK_DMAC>; 580 clock-names = "apb_pclk"; 581 #dma-cells = <1>; 582 peripherals-req-type-burst; 583 }; 584 }; 585 586 tsadc: tsadc@ff280000 { 587 compatible = "rockchip,px30-tsadc"; 588 reg = <0x0 0xff280000 0x0 0x100>; 589 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 590 rockchip,grf = <&grf>; 591 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 592 clock-names = "tsadc", "apb_pclk"; 593 assigned-clocks = <&cru SCLK_TSADC>; 594 assigned-clock-rates = <50000>; 595 resets = <&cru SRST_TSADC_P>; 596 reset-names = "tsadc-apb"; 597 pinctrl-names = "init", "default", "sleep"; 598 pinctrl-0 = <&tsadc_otp_gpio>; 599 pinctrl-1 = <&tsadc_otp_out>; 600 pinctrl-2 = <&tsadc_otp_gpio>; 601 #thermal-sensor-cells = <1>; 602 rockchip,hw-tshut-temp = <100000>; 603 status = "disabled"; 604 }; 605 606 saradc: saradc@ff288000 { 607 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 608 reg = <0x0 0xff288000 0x0 0x100>; 609 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 610 #io-channel-cells = <1>; 611 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 612 clock-names = "saradc", "apb_pclk"; 613 resets = <&cru SRST_SARADC_P>; 614 reset-names = "saradc-apb"; 615 status = "disabled"; 616 }; 617 618 cru: clock-controller@ff2b0000 { 619 compatible = "rockchip,px30-cru"; 620 reg = <0x0 0xff2b0000 0x0 0x9000>; 621 rockchip,grf = <&grf>; 622 #clock-cells = <1>; 623 #reset-cells = <1>; 624 625 assigned-clocks = 626 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 627 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 628 <&cru ARMCLK>; 629 assigned-clock-rates = 630 <1608000000>, <1416000000>, 631 <1188000000>, <1188000000>, 632 <816000000>; 633 }; 634 635 pmucru: pmu-clock-controller@ff2bc000 { 636 compatible = "rockchip,px30-pmucru"; 637 reg = <0x0 0xff2bc000 0x0 0x1000>; 638 rockchip,grf = <&grf>; 639 #clock-cells = <1>; 640 #reset-cells = <1>; 641 642 assigned-clocks = 643 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 644 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 645 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 646 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 647 assigned-clock-rates = 648 <1200000000>, <100000000>, 649 <26000000>, <300000000>, 650 <300000000>, <150000000>, 651 <150000000>, <75000000>; 652 }; 653 654 usb2phy_grf: syscon@ff2c0000 { 655 compatible = "rockchip,px30-usb2phy-grf", "syscon", 656 "simple-mfd"; 657 reg = <0x0 0xff2c0000 0x0 0x10000>; 658 #address-cells = <1>; 659 #size-cells = <1>; 660 661 u2phy: usb2-phy@100 { 662 compatible = "rockchip,px30-usb2phy", 663 "rockchip,rk3328-usb2phy"; 664 reg = <0x100 0x10>; 665 clocks = <&pmucru SCLK_USBPHY_REF>; 666 clock-names = "phyclk"; 667 #clock-cells = <0>; 668 assigned-clocks = <&cru USB480M>; 669 assigned-clock-parents = <&u2phy>; 670 clock-output-names = "usb480m_phy"; 671 status = "disabled"; 672 673 u2phy_host: host-port { 674 #phy-cells = <0>; 675 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 676 interrupt-names = "linestate"; 677 status = "disabled"; 678 }; 679 680 u2phy_otg: otg-port { 681 #phy-cells = <0>; 682 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "otg-bvalid", "otg-id", 686 "linestate"; 687 status = "disabled"; 688 }; 689 }; 690 }; 691 692 mipi_dphy: mipi-dphy@ff2e0000 { 693 compatible = "rockchip,px30-mipi-dphy"; 694 reg = <0x0 0xff2e0000 0x0 0x10000>; 695 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 696 clock-names = "ref", "pclk"; 697 clock-output-names = "mipi_dphy_pll"; 698 #clock-cells = <0>; 699 resets = <&cru SRST_MIPIDSIPHY_P>; 700 reset-names = "apb"; 701 power-domains = <&power PX30_PD_VO>; 702 #phy-cells = <0>; 703 rockchip,grf = <&grf>; 704 status = "disabled"; 705 }; 706 707 lvds: lvds@ff2e0000 { 708 compatible = "rockchip,px30-lvds"; 709 reg = <0x0 0xff2e0000 0x0 0x100>, <0x0 0xff2e0100 0x0 0x100>; 710 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; 711 clocks = <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 712 clock-names = "pclk_lvds", "pclk_lvds_ctl"; 713 power-domains = <&power PX30_PD_VO>; 714 rockchip,grf = <&grf>; 715 status = "disabled"; 716 717 ports { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 port@0 { 722 reg = <0>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 726 lvds_in_vopl: endpoint@0 { 727 reg = <0>; 728 remote-endpoint = <&vopl_out_lvds>; 729 }; 730 731 lvds_in_vopb: endpoint@1 { 732 reg = <1>; 733 remote-endpoint = <&vopb_out_lvds>; 734 }; 735 }; 736 }; 737 }; 738 739 usb20_otg: usb@ff300000 { 740 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 741 "snps,dwc2"; 742 reg = <0x0 0xff300000 0x0 0x40000>; 743 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&cru HCLK_OTG>; 745 clock-names = "otg"; 746 dr_mode = "otg"; 747 g-np-tx-fifo-size = <16>; 748 g-rx-fifo-size = <275>; 749 g-tx-fifo-size = <256 128 128 64 64 32>; 750 g-use-dma; 751 phys = <&u2phy_otg>; 752 phy-names = "usb2-phy"; 753 status = "disabled"; 754 }; 755 756 usb_host0_ehci: usb@ff340000 { 757 compatible = "generic-ehci"; 758 reg = <0x0 0xff340000 0x0 0x10000>; 759 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 761 <&u2phy>; 762 clock-names = "usbhost", "arbiter", "utmi"; 763 phys = <&u2phy_host>; 764 phy-names = "usb"; 765 status = "disabled"; 766 }; 767 768 usb_host0_ohci: usb@ff350000 { 769 compatible = "generic-ohci"; 770 reg = <0x0 0xff350000 0x0 0x10000>; 771 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 773 <&u2phy>; 774 clock-names = "usbhost", "arbiter", "utmi"; 775 phys = <&u2phy_host>; 776 phy-names = "usb"; 777 }; 778 779 gmac: ethernet@ff360000 { 780 compatible = "rockchip,px30-gmac"; 781 reg = <0x0 0xff360000 0x0 0x10000>; 782 rockchip,grf = <&grf>; 783 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 784 interrupt-names = "macirq"; 785 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 786 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 787 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 788 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 789 clock-names = "stmmaceth", "mac_clk_rx", 790 "mac_clk_tx", "clk_mac_ref", 791 "clk_mac_refout", "aclk_mac", 792 "pclk_mac", "clk_mac_speed"; 793 phy-mode = "rmii"; 794 pinctrl-names = "default"; 795 pinctrl-0 = <&rmii_pins>; 796 resets = <&cru SRST_GMAC_A>; 797 reset-names = "stmmaceth"; 798 power-domains = <&power PX30_PD_GMAC>; 799 status = "disabled"; 800 }; 801 802 sdmmc: dwmmc@ff370000 { 803 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 804 reg = <0x0 0xff370000 0x0 0x4000>; 805 max-frequency = <150000000>; 806 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 807 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 808 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 809 fifo-depth = <0x100>; 810 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 813 status = "disabled"; 814 }; 815 816 sdio: dwmmc@ff380000 { 817 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 818 reg = <0x0 0xff380000 0x0 0x4000>; 819 max-frequency = <150000000>; 820 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 821 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 822 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 823 fifo-depth = <0x100>; 824 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 825 status = "disabled"; 826 }; 827 828 emmc: dwmmc@ff390000 { 829 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 830 reg = <0x0 0xff390000 0x0 0x4000>; 831 max-frequency = <150000000>; 832 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 833 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 834 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 835 fifo-depth = <0x100>; 836 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 837 status = "disabled"; 838 }; 839 840 nandc0: nandc@ff3b0000 { 841 compatible = "rockchip,rk-nandc"; 842 reg = <0x0 0xff3b0000 0x0 0x4000>; 843 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 844 nandc_id = <0>; 845 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 846 clock-names = "clk_nandc", "hclk_nandc"; 847 status = "disabled"; 848 }; 849 850 gpu: gpu@ff400000 { 851 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 852 reg = <0x0 0xff400000 0x0 0x4000>; 853 854 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 857 interrupt-names = "GPU", "MMU", "JOB"; 858 859 clocks = <&cru ACLK_GPU>; 860 clock-names = "clk_mali"; 861 862 status = "disabled"; 863 }; 864 865 hevc: hevc_service@ff440000 { 866 compatible = "rockchip,hevc_sub"; 867 iommu_enabled = <1>; 868 reg = <0x0 0xff440000 0x0 0x400>; 869 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "irq_dec"; 871 dev_mode = <1>; 872 iommus = <&hevc_mmu>; 873 name = "hevc_service"; 874 allocator = <1>; 875 }; 876 877 vpu: vpu_service@ff442000 { 878 compatible = "rockchip,vpu_sub"; 879 iommu_enabled = <1>; 880 reg = <0x0 0xff442000 0x0 0x800>; 881 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "irq_enc", "irq_dec"; 884 dev_mode = <0>; 885 iommus = <&vpu_mmu>; 886 name = "vpu_service"; 887 allocator = <1>; 888 }; 889 890 vpu_combo: vpu_combo { 891 compatible = "rockchip,vpu_combo"; 892 subcnt = <2>; 893 rockchip,grf = <&grf>; 894 rockchip,sub = <&vpu>, <&hevc>; 895 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 896 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 897 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 898 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 899 <&cru SRST_VPU_CORE>; 900 reset-names = "video_a", "video_h", "niu_a", "niu_h", 901 "video_core"; 902 mode_bit = <15>; 903 mode_ctrl = <0x410>; 904 name = "vpu_combo"; 905 status = "disabled"; 906 }; 907 908 hevc_mmu: iommu@ff440440 { 909 compatible = "rockchip,iommu"; 910 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 911 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 912 interrupt-names = "hevc_mmu"; 913 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 914 clock-names = "aclk", "hclk"; 915 #iommu-cells = <0>; 916 }; 917 918 vpu_mmu: iommu@ff442800 { 919 compatible = "rockchip,iommu"; 920 reg = <0x0 0xff442800 0x0 0x100>; 921 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 922 interrupt-names = "vpu_mmu"; 923 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 924 clock-names = "aclk", "hclk"; 925 #iommu-cells = <0>; 926 }; 927 928 dsi: dsi@ff450000 { 929 compatible = "rockchip,px30-mipi-dsi"; 930 reg = <0x0 0xff450000 0x0 0x10000>; 931 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&cru PCLK_MIPI_DSI>, <&mipi_dphy>; 933 clock-names = "pclk", "hs_clk"; 934 resets = <&cru SRST_MIPIDSI_HOST_P>; 935 reset-names = "apb"; 936 phys = <&mipi_dphy>; 937 phy-names = "mipi_dphy"; 938 power-domains = <&power PX30_PD_VO>; 939 rockchip,grf = <&grf>; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 status = "disabled"; 943 944 ports { 945 port { 946 #address-cells = <1>; 947 #size-cells = <0>; 948 949 dsi_in_vopl: endpoint@0 { 950 reg = <0>; 951 remote-endpoint = <&vopl_out_dsi>; 952 }; 953 954 dsi_in_vopb: endpoint@1 { 955 reg = <1>; 956 remote-endpoint = <&vopb_out_dsi>; 957 }; 958 }; 959 }; 960 }; 961 962 vopb: vop@ff460000 { 963 compatible = "rockchip,px30-vop-big"; 964 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 965 reg-names = "regs", "gamma_lut"; 966 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 968 <&cru HCLK_VOPB>; 969 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 970 iommus = <&vopb_mmu>; 971 status = "disabled"; 972 973 vopb_out: port { 974 #address-cells = <1>; 975 #size-cells = <0>; 976 977 vopb_out_lvds: endpoint@0 { 978 reg = <0>; 979 remote-endpoint = <&lvds_in_vopb>; 980 }; 981 982 vopb_out_dsi: endpoint@1 { 983 reg = <1>; 984 remote-endpoint = <&dsi_in_vopb>; 985 }; 986 }; 987 }; 988 989 vopb_mmu: iommu@ff460f00 { 990 compatible = "rockchip,iommu"; 991 reg = <0x0 0xff460f00 0x0 0x100>; 992 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "vopb_mmu"; 994 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 995 clock-names = "aclk", "hclk"; 996 #iommu-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 vopl: vop@ff470000 { 1001 compatible = "rockchip,px30-vop-lit"; 1002 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 1003 reg-names = "regs", "gamma_lut"; 1004 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1006 <&cru HCLK_VOPL>; 1007 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1008 iommus = <&vopl_mmu>; 1009 status = "disabled"; 1010 1011 vopl_out: port { 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 1015 vopl_out_lvds: endpoint@0 { 1016 reg = <0>; 1017 remote-endpoint = <&lvds_in_vopl>; 1018 }; 1019 1020 vopl_out_dsi: endpoint@1 { 1021 reg = <1>; 1022 remote-endpoint = <&dsi_in_vopl>; 1023 }; 1024 }; 1025 }; 1026 1027 vopl_mmu: iommu@ff470f00 { 1028 compatible = "rockchip,iommu"; 1029 reg = <0x0 0xff470f00 0x0 0x100>; 1030 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1031 interrupt-names = "vopl_mmu"; 1032 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1033 clock-names = "aclk", "hclk"; 1034 #iommu-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 rk_rga: rk_rga@ff480000 { 1039 compatible = "rockchip,rga2"; 1040 //dev_mode = <1>; 1041 reg = <0x0 0xff480000 0x0 0x1000>; 1042 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1044 clock-names = "aclk_rga", "hclk_rga"; 1045 dma-coherent; 1046 status = "disabled"; 1047 }; 1048 1049 cif: cif@ff490000 { 1050 compatible = "rockchip,cif"; 1051 reg = <0x0 0xff490000 0x0 0x200>; 1052 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1054 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1055 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1056 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1057 pinctrl-names = "cif_pin_all"; 1058 pinctrl-0 = <&dvp_d2d9_m0>; 1059 status = "disabled"; 1060 }; 1061 1062 vip_mmu: iommu@ff490800{ 1063 compatible = "rockchip,iommu"; 1064 reg = <0x0 0xff490800 0x0 0x100>; 1065 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1066 interrupt-names = "vip_mmu"; 1067 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1068 clock-names = "aclk", "hclk"; 1069 rk_iommu,disable_reset_quirk; 1070 #iommu-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 rk_isp: rk_isp@ff4a0000 { 1075 compatible = "rockchip,px30-isp", "rockchip,isp"; 1076 reg = <0x0 0xff4a0000 0x0 0x4000>; 1077 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1079 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1080 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1081 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1082 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1083 reset-names = "rst_isp", "rst_mipicsiphy"; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&cif_clkout_m0>; 1086 rockchip,isp,mipiphy = <0>; 1087 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1088 rockchip,grf = <&grf>; 1089 rockchip,cru = <&cru>; 1090 rockchip,isp,iommu-enable = <1>; 1091 iommus = <&isp_mmu>; 1092 status = "disabled"; 1093 }; 1094 1095 isp_mmu: iommu@ff4a8000 { 1096 compatible = "rockchip,iommu"; 1097 reg = <0x0 0xff4a8000 0x0 0x100>; 1098 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1099 interrupt-names = "isp_mmu"; 1100 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1101 clock-names = "aclk", "hclk"; 1102 rk_iommu,disable_reset_quirk; 1103 #iommu-cells = <0>; 1104 status = "disabled"; 1105 }; 1106 1107 qos_gmac: qos@ff518000 { 1108 compatible = "syscon"; 1109 reg = <0x0 0xff518000 0x0 0x20>; 1110 }; 1111 1112 qos_gpu: qos@ff520000 { 1113 compatible = "syscon"; 1114 reg = <0x0 0xff520000 0x0 0x20>; 1115 }; 1116 1117 qos_sdmmc: qos@ff52c000 { 1118 compatible = "syscon"; 1119 reg = <0x0 0xff52c000 0x0 0x20>; 1120 }; 1121 1122 qos_emmc: qos@ff538000 { 1123 compatible = "syscon"; 1124 reg = <0x0 0xff538000 0x0 0x20>; 1125 }; 1126 1127 qos_nand: qos@ff538080 { 1128 compatible = "syscon"; 1129 reg = <0x0 0xff538080 0x0 0x20>; 1130 }; 1131 1132 qos_sdio: qos@ff538100 { 1133 compatible = "syscon"; 1134 reg = <0x0 0xff538100 0x0 0x20>; 1135 }; 1136 1137 qos_sfc: qos@ff538180 { 1138 compatible = "syscon"; 1139 reg = <0x0 0xff538180 0x0 0x20>; 1140 }; 1141 1142 qos_usb_host: qos@ff540000 { 1143 compatible = "syscon"; 1144 reg = <0x0 0xff540000 0x0 0x20>; 1145 }; 1146 1147 qos_usb_otg: qos@ff540080 { 1148 compatible = "syscon"; 1149 reg = <0x0 0xff540080 0x0 0x20>; 1150 }; 1151 1152 qos_isp_128: qos@ff548000 { 1153 compatible = "syscon"; 1154 reg = <0x0 0xff548000 0x0 0x20>; 1155 }; 1156 1157 qos_isp_rd: qos@ff548080 { 1158 compatible = "syscon"; 1159 reg = <0x0 0xff548080 0x0 0x20>; 1160 }; 1161 1162 qos_isp_wr: qos@ff548100 { 1163 compatible = "syscon"; 1164 reg = <0x0 0xff548100 0x0 0x20>; 1165 }; 1166 1167 qos_isp_m1: qos@ff548180 { 1168 compatible = "syscon"; 1169 reg = <0x0 0xff548180 0x0 0x20>; 1170 }; 1171 1172 qos_vip: qos@ff548200 { 1173 compatible = "syscon"; 1174 reg = <0x0 0xff548200 0x0 0x20>; 1175 }; 1176 1177 qos_rga_rd: qos@ff550000 { 1178 compatible = "syscon"; 1179 reg = <0x0 0xff550000 0x0 0x20>; 1180 }; 1181 1182 qos_rga_wr: qos@ff550080 { 1183 compatible = "syscon"; 1184 reg = <0x0 0xff550080 0x0 0x20>; 1185 }; 1186 1187 qos_vop_m0: qos@ff550100 { 1188 compatible = "syscon"; 1189 reg = <0x0 0xff550100 0x0 0x20>; 1190 }; 1191 1192 qos_vop_m1: qos@ff550180 { 1193 compatible = "syscon"; 1194 reg = <0x0 0xff550180 0x0 0x20>; 1195 }; 1196 1197 qos_vpu: qos@ff558000 { 1198 compatible = "syscon"; 1199 reg = <0x0 0xff558000 0x0 0x20>; 1200 }; 1201 1202 qos_vpu_r128: qos@ff558080 { 1203 compatible = "syscon"; 1204 reg = <0x0 0xff558080 0x0 0x20>; 1205 }; 1206 1207 pinctrl: pinctrl { 1208 compatible = "rockchip,px30-pinctrl"; 1209 rockchip,grf = <&grf>; 1210 rockchip,pmu = <&pmugrf>; 1211 #address-cells = <2>; 1212 #size-cells = <2>; 1213 ranges; 1214 1215 gpio0: gpio0@ff040000 { 1216 compatible = "rockchip,gpio-bank"; 1217 reg = <0x0 0xff040000 0x0 0x100>; 1218 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&cru PCLK_GPIO0_PMU>; 1220 gpio-controller; 1221 #gpio-cells = <2>; 1222 1223 interrupt-controller; 1224 #interrupt-cells = <2>; 1225 }; 1226 1227 gpio1: gpio1@ff250000 { 1228 compatible = "rockchip,gpio-bank"; 1229 reg = <0x0 0xff250000 0x0 0x100>; 1230 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&cru PCLK_GPIO1>; 1232 gpio-controller; 1233 #gpio-cells = <2>; 1234 1235 interrupt-controller; 1236 #interrupt-cells = <2>; 1237 }; 1238 1239 gpio2: gpio2@ff260000 { 1240 compatible = "rockchip,gpio-bank"; 1241 reg = <0x0 0xff260000 0x0 0x100>; 1242 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&cru PCLK_GPIO2>; 1244 gpio-controller; 1245 #gpio-cells = <2>; 1246 1247 interrupt-controller; 1248 #interrupt-cells = <2>; 1249 }; 1250 1251 gpio3: gpio3@ff270000 { 1252 compatible = "rockchip,gpio-bank"; 1253 reg = <0x0 0xff270000 0x0 0x100>; 1254 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&cru PCLK_GPIO3>; 1256 gpio-controller; 1257 #gpio-cells = <2>; 1258 1259 interrupt-controller; 1260 #interrupt-cells = <2>; 1261 }; 1262 1263 pcfg_pull_up: pcfg-pull-up { 1264 bias-pull-up; 1265 }; 1266 1267 pcfg_pull_down: pcfg-pull-down { 1268 bias-pull-down; 1269 }; 1270 1271 pcfg_pull_none: pcfg-pull-none { 1272 bias-disable; 1273 }; 1274 1275 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1276 bias-disable; 1277 drive-strength = <2>; 1278 }; 1279 1280 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1281 bias-pull-up; 1282 drive-strength = <2>; 1283 }; 1284 1285 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1286 bias-pull-up; 1287 drive-strength = <4>; 1288 }; 1289 1290 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1291 bias-disable; 1292 drive-strength = <4>; 1293 }; 1294 1295 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1296 bias-pull-down; 1297 drive-strength = <4>; 1298 }; 1299 1300 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1301 bias-disable; 1302 drive-strength = <8>; 1303 }; 1304 1305 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1306 bias-pull-up; 1307 drive-strength = <8>; 1308 }; 1309 1310 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1311 bias-disable; 1312 drive-strength = <12>; 1313 }; 1314 1315 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1316 bias-pull-up; 1317 drive-strength = <12>; 1318 }; 1319 1320 pcfg_pull_none_smt: pcfg-pull-none-smt { 1321 bias-disable; 1322 input-schmitt-enable; 1323 }; 1324 1325 pcfg_output_high: pcfg-output-high { 1326 output-high; 1327 }; 1328 1329 pcfg_output_low: pcfg-output-low { 1330 output-low; 1331 }; 1332 1333 pcfg_input_high: pcfg-input-high { 1334 bias-pull-up; 1335 input-enable; 1336 }; 1337 1338 pcfg_input: pcfg-input { 1339 input-enable; 1340 }; 1341 1342 i2c0 { 1343 i2c0_xfer: i2c0-xfer { 1344 rockchip,pins = 1345 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1346 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1347 }; 1348 }; 1349 1350 i2c1 { 1351 i2c1_xfer: i2c1-xfer { 1352 rockchip,pins = 1353 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1354 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1355 }; 1356 }; 1357 1358 i2c2 { 1359 i2c2_xfer: i2c2-xfer { 1360 rockchip,pins = 1361 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1362 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1363 }; 1364 }; 1365 1366 i2c3 { 1367 i2c3_xfer: i2c3-xfer { 1368 rockchip,pins = 1369 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1370 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1371 }; 1372 }; 1373 1374 tsadc { 1375 tsadc_otp_gpio: tsadc-otp-gpio { 1376 rockchip,pins = 1377 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1378 }; 1379 1380 tsadc_otp_out: tsadc-otp-out { 1381 rockchip,pins = 1382 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1383 }; 1384 }; 1385 1386 uart0 { 1387 uart0_xfer: uart0-xfer { 1388 rockchip,pins = 1389 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1390 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1391 }; 1392 1393 uart0_cts: uart0-cts { 1394 rockchip,pins = 1395 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1396 }; 1397 1398 uart0_rts: uart0-rts { 1399 rockchip,pins = 1400 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1401 }; 1402 1403 uart0_rts_gpio: uart0-rts-gpio { 1404 rockchip,pins = 1405 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1406 }; 1407 }; 1408 1409 uart1 { 1410 uart1_xfer: uart1-xfer { 1411 rockchip,pins = 1412 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1413 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1414 }; 1415 1416 uart1_cts: uart1-cts { 1417 rockchip,pins = 1418 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1419 }; 1420 1421 uart1_rts: uart1-rts { 1422 rockchip,pins = 1423 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1424 }; 1425 1426 uart1_rts_gpio: uart1-rts-gpio { 1427 rockchip,pins = 1428 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1429 }; 1430 }; 1431 1432 uart2-m0 { 1433 uart2m0_xfer: uart2m0-xfer { 1434 rockchip,pins = 1435 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1436 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1437 }; 1438 }; 1439 1440 uart2-m1 { 1441 uart2m1_xfer: uart2m1-xfer { 1442 rockchip,pins = 1443 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1444 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1445 }; 1446 }; 1447 1448 uart3-m0 { 1449 uart3m0_xfer: uart3m0-xfer { 1450 rockchip,pins = 1451 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1452 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1453 }; 1454 1455 uart3m0_cts: uart3m0-cts { 1456 rockchip,pins = 1457 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1458 }; 1459 1460 uart3m0_rts: uart3m0-rts { 1461 rockchip,pins = 1462 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1463 }; 1464 1465 uart3m0_rts_gpio: uart3m0-rts-gpio { 1466 rockchip,pins = 1467 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1468 }; 1469 }; 1470 1471 uart3-m1 { 1472 uart3m1_xfer: uart3m1-xfer { 1473 rockchip,pins = 1474 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1475 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1476 }; 1477 1478 uart3m1_cts: uart3m1-cts { 1479 rockchip,pins = 1480 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1481 }; 1482 1483 uart3m1_rts: uart3m1-rts { 1484 rockchip,pins = 1485 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1486 }; 1487 1488 uart3m1_rts_gpio: uart3m1-rts-gpio { 1489 rockchip,pins = 1490 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1491 }; 1492 }; 1493 1494 uart4 { 1495 1496 uart4_xfer: uart4-xfer { 1497 rockchip,pins = 1498 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1499 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1500 }; 1501 1502 uart4_cts: uart4-cts { 1503 rockchip,pins = 1504 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1505 1506 }; 1507 1508 uart4_rts: uart4-rts { 1509 rockchip,pins = 1510 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1511 }; 1512 }; 1513 1514 uart5 { 1515 1516 uart5_xfer: uart5-xfer { 1517 rockchip,pins = 1518 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1519 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1520 }; 1521 1522 uart5_cts: uart5-cts { 1523 rockchip,pins = 1524 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1525 1526 }; 1527 1528 uart5_rts: uart5-rts { 1529 rockchip,pins = 1530 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1531 }; 1532 }; 1533 1534 spi0 { 1535 spi0_clk: spi0-clk { 1536 rockchip,pins = 1537 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1538 }; 1539 1540 spi0_csn: spi0-csn { 1541 rockchip,pins = 1542 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1543 }; 1544 1545 spi0_miso: spi0-miso { 1546 rockchip,pins = 1547 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1548 }; 1549 1550 spi0_mosi: spi0-mosi { 1551 rockchip,pins = 1552 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1553 }; 1554 }; 1555 1556 spi1 { 1557 spi1_clk: spi1-clk { 1558 rockchip,pins = 1559 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1560 }; 1561 1562 spi1_csn: spi1-csn { 1563 rockchip,pins = 1564 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1565 }; 1566 1567 spi1_miso: spi1-miso { 1568 rockchip,pins = 1569 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1570 }; 1571 1572 spi1_mosi: spi1-mosi { 1573 rockchip,pins = 1574 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1575 }; 1576 }; 1577 1578 pdm { 1579 pdm_clk0m0: pdm-clk0m0 { 1580 rockchip,pins = 1581 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1582 }; 1583 1584 pdm_clk0m1: pdm-clk0m1 { 1585 rockchip,pins = 1586 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1587 }; 1588 1589 pdm_clk1: pdm-clk1 { 1590 rockchip,pins = 1591 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1592 }; 1593 1594 pdm_sdi0m0: pdm-sdi0m0 { 1595 rockchip,pins = 1596 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1597 }; 1598 1599 pdm_sdi0m1: pdm-sdi0m1 { 1600 rockchip,pins = 1601 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1602 }; 1603 1604 pdm_sdi1: pdm-sdi1 { 1605 rockchip,pins = 1606 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1607 }; 1608 1609 pdm_sdi2: pdm-sdi2 { 1610 rockchip,pins = 1611 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1612 }; 1613 1614 pdm_sdi3: pdm-sdi3 { 1615 rockchip,pins = 1616 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1617 }; 1618 1619 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1620 rockchip,pins = 1621 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1622 }; 1623 1624 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1625 rockchip,pins = 1626 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1627 }; 1628 1629 pdm_clk1_sleep: pdm-clk1-sleep { 1630 rockchip,pins = 1631 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1632 }; 1633 1634 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1635 rockchip,pins = 1636 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1637 }; 1638 1639 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1640 rockchip,pins = 1641 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1642 }; 1643 1644 pdm_sdi1_sleep: pdm-sdi1-sleep { 1645 rockchip,pins = 1646 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1647 }; 1648 1649 pdm_sdi2_sleep: pdm-sdi2-sleep { 1650 rockchip,pins = 1651 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1652 }; 1653 1654 pdm_sdi3_sleep: pdm-sdi3-sleep { 1655 rockchip,pins = 1656 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1657 }; 1658 }; 1659 1660 i2s0 { 1661 i2s0_8ch_mclk: i2s0-8ch-mclk { 1662 rockchip,pins = 1663 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1664 }; 1665 1666 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1667 rockchip,pins = 1668 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1669 }; 1670 1671 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1672 rockchip,pins = 1673 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1674 }; 1675 1676 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1677 rockchip,pins = 1678 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1679 }; 1680 1681 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1682 rockchip,pins = 1683 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1684 }; 1685 1686 i2s0_8ch_sdo: i2s0-8ch-sdo { 1687 rockchip,pins = 1688 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1689 }; 1690 1691 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1692 rockchip,pins = 1693 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1694 }; 1695 1696 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1697 rockchip,pins = 1698 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1699 }; 1700 1701 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1702 rockchip,pins = 1703 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1704 }; 1705 1706 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1707 rockchip,pins = 1708 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1709 }; 1710 1711 i2s0_8ch_sdi: i2s0-8ch-sdi { 1712 rockchip,pins = 1713 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1714 }; 1715 1716 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1717 rockchip,pins = 1718 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1719 }; 1720 1721 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1722 rockchip,pins = 1723 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1724 }; 1725 1726 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1727 rockchip,pins = 1728 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1729 }; 1730 1731 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1732 rockchip,pins = 1733 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1734 }; 1735 }; 1736 1737 i2s1 { 1738 i2s1_2ch_mclk: i2s1-2ch-mclk { 1739 rockchip,pins = 1740 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1741 }; 1742 1743 i2s1_2ch_sclk: i2s1-2ch-sclk { 1744 rockchip,pins = 1745 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1746 }; 1747 1748 i2s1_2ch_lrck: i2s1-2ch-lrck { 1749 rockchip,pins = 1750 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1751 }; 1752 1753 i2s1_2ch_sdi: i2s1-2ch-sdi { 1754 rockchip,pins = 1755 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1756 }; 1757 1758 i2s1_2ch_sdo: i2s1-2ch-sdo { 1759 rockchip,pins = 1760 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1761 }; 1762 }; 1763 1764 i2s2 { 1765 i2s2_2ch_mclk: i2s2-2ch-mclk { 1766 rockchip,pins = 1767 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1768 }; 1769 1770 i2s2_2ch_sclk: i2s2-2ch-sclk { 1771 rockchip,pins = 1772 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1773 }; 1774 1775 i2s2_2ch_lrck: i2s2-2ch-lrck { 1776 rockchip,pins = 1777 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1778 }; 1779 1780 i2s2_2ch_sdi: i2s2-2ch-sdi { 1781 rockchip,pins = 1782 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1783 }; 1784 1785 i2s2_2ch_sdo: i2s2-2ch-sdo { 1786 rockchip,pins = 1787 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1788 }; 1789 }; 1790 1791 sdmmc { 1792 sdmmc_clk: sdmmc-clk { 1793 rockchip,pins = 1794 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_8ma>; 1795 }; 1796 1797 sdmmc_cmd: sdmmc-cmd { 1798 rockchip,pins = 1799 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_8ma>; 1800 }; 1801 1802 sdmmc_det: sdmmc-det { 1803 rockchip,pins = 1804 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>; 1805 }; 1806 1807 sdmmc_bus1: sdmmc-bus1 { 1808 rockchip,pins = 1809 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>; 1810 }; 1811 1812 sdmmc_bus4: sdmmc-bus4 { 1813 rockchip,pins = 1814 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>, 1815 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_8ma>, 1816 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_8ma>, 1817 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_8ma>; 1818 }; 1819 1820 sdmmc_gpio: sdmmc-gpio { 1821 rockchip,pins = 1822 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1823 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1824 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1825 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1826 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1827 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1828 }; 1829 }; 1830 1831 sdio { 1832 sdio_clk: sdio-clk { 1833 rockchip,pins = 1834 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1835 }; 1836 1837 sdio_cmd: sdio-cmd { 1838 rockchip,pins = 1839 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1840 }; 1841 1842 sdio_bus4: sdio-bus4 { 1843 rockchip,pins = 1844 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1845 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>, 1846 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>, 1847 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>; 1848 }; 1849 1850 sdio_gpio: sdio-gpio { 1851 rockchip,pins = 1852 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 1853 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, 1854 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, 1855 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, 1856 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, 1857 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 1858 }; 1859 }; 1860 1861 emmc { 1862 emmc_clk: emmc-clk { 1863 rockchip,pins = 1864 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1865 }; 1866 1867 emmc_cmd: emmc-cmd { 1868 rockchip,pins = 1869 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1870 }; 1871 1872 emmc_pwren: emmc-pwren { 1873 rockchip,pins = 1874 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1875 }; 1876 1877 emmc_rstnout: emmc-rstnout { 1878 rockchip,pins = 1879 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1880 }; 1881 1882 emmc_bus1: emmc-bus1 { 1883 rockchip,pins = 1884 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1885 }; 1886 1887 emmc_bus4: emmc-bus4 { 1888 rockchip,pins = 1889 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1890 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1891 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1892 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1893 }; 1894 1895 emmc_bus8: emmc-bus8 { 1896 rockchip,pins = 1897 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1898 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1899 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1900 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1901 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1902 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1903 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1904 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1905 }; 1906 }; 1907 1908 flash { 1909 flash_cs0: flash-cs0 { 1910 rockchip,pins = 1911 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1912 }; 1913 1914 flash_rdy: flash-rdy { 1915 rockchip,pins = 1916 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1917 }; 1918 1919 flash_dqs: flash-dqs { 1920 rockchip,pins = 1921 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1922 }; 1923 1924 flash_ale: flash-ale { 1925 rockchip,pins = 1926 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1927 }; 1928 1929 flash_cle: flash-cle { 1930 rockchip,pins = 1931 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1932 }; 1933 1934 flash_wrn: flash-wrn { 1935 rockchip,pins = 1936 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1937 }; 1938 1939 flash_csl: flash-csl { 1940 rockchip,pins = 1941 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 1942 }; 1943 1944 flash_rdn: flash-rdn { 1945 rockchip,pins = 1946 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 1947 }; 1948 1949 flash_bus8: flash-bus8 { 1950 rockchip,pins = 1951 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 1952 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 1953 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 1954 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 1955 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 1956 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 1957 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 1958 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 1959 }; 1960 }; 1961 1962 lcdc { 1963 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1964 rockchip,pins = 1965 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1966 }; 1967 1968 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1969 rockchip,pins = 1970 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1971 }; 1972 1973 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1974 rockchip,pins = 1975 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>; 1976 }; 1977 1978 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1979 rockchip,pins = 1980 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 1981 }; 1982 1983 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1984 rockchip,pins = 1985 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 1986 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 1987 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 1988 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 1989 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 1990 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 1991 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 1992 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 1993 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 1994 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 1995 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 1996 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 1997 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 1998 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 1999 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2000 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2001 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 2002 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 2003 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2004 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2005 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2006 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2007 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2008 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2009 }; 2010 2011 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2012 rockchip,pins = 2013 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2014 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2015 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2016 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2017 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2018 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2019 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2020 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2021 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2022 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2023 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2024 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2025 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2026 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2027 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2028 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2029 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2030 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2031 }; 2032 2033 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2034 rockchip,pins = 2035 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d3 */ 2036 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2037 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d1 */ 2038 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2039 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2040 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2041 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d5 */ 2042 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d4 */ 2043 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d11 */ 2044 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d10 */ 2045 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2046 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d8 */ 2047 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2048 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2049 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2050 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2051 }; 2052 2053 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2054 rockchip,pins = 2055 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2056 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2057 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2058 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2059 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2060 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2061 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2062 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2063 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2064 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d19 */ 2065 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d18 */ 2066 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2067 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d16 */ 2068 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d23 */ 2069 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d22 */ 2070 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d21 */ 2071 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d20 */ 2072 }; 2073 2074 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2075 rockchip,pins = 2076 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2077 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2078 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2079 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2080 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2081 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2082 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2083 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2084 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d12 */ 2085 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d17 */ 2086 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d16 */ 2087 }; 2088 2089 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2090 rockchip,pins = 2091 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d2 */ 2092 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d0 */ 2093 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d7 */ 2094 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d6 */ 2095 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d9 */ 2096 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d15 */ 2097 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d14 */ 2098 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* lcdc_d13 */ 2099 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* lcdc_d12 */ 2100 }; 2101 }; 2102 2103 pwm0 { 2104 pwm0_pin: pwm0-pin { 2105 rockchip,pins = 2106 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2107 }; 2108 }; 2109 2110 pwm1 { 2111 pwm1_pin: pwm1-pin { 2112 rockchip,pins = 2113 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2114 }; 2115 }; 2116 2117 pwm2 { 2118 pwm2_pin: pwm2-pin { 2119 rockchip,pins = 2120 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2121 }; 2122 }; 2123 2124 pwm3 { 2125 pwm3_pin: pwm3-pin { 2126 rockchip,pins = 2127 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2128 }; 2129 }; 2130 2131 pwm4 { 2132 pwm4_pin: pwm4-pin { 2133 rockchip,pins = 2134 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2135 }; 2136 }; 2137 2138 pwm5 { 2139 pwm5_pin: pwm5-pin { 2140 rockchip,pins = 2141 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2142 }; 2143 }; 2144 2145 pwm6 { 2146 pwm6_pin: pwm6-pin { 2147 rockchip,pins = 2148 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2149 }; 2150 }; 2151 2152 pwm7 { 2153 pwm7_pin: pwm7-pin { 2154 rockchip,pins = 2155 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2156 }; 2157 }; 2158 2159 gmac { 2160 rmii_pins: rmii-pins { 2161 rockchip,pins = 2162 /* mac_txen */ 2163 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2164 /* mac_txd1 */ 2165 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2166 /* mac_txd0 */ 2167 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2168 /* mac_rxd0 */ 2169 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2170 /* mac_rxd1 */ 2171 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2172 /* mac_rxer */ 2173 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2174 /* mac_rxdv */ 2175 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2176 /* mac_mdio */ 2177 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2178 /* mac_mdc */ 2179 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>, 2180 /* mac_clk */ 2181 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2182 }; 2183 }; 2184 2185 cif-m0 { 2186 cif_clkout_m0: cif-clkout-m0 { 2187 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2188 }; 2189 2190 dvp_d2d9_m0: dvp-d2d9-m0 { 2191 rockchip,pins = 2192 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2193 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2194 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2195 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2196 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2197 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2198 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2199 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2200 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2201 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2202 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2203 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2204 }; 2205 2206 dvp_d0d1_m0: dvp-d0d1-m0 { 2207 rockchip,pins = 2208 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2209 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2210 }; 2211 2212 dvp_d10d11_m0:d10-d11-m0 { 2213 rockchip,pins = 2214 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2215 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2216 }; 2217 }; 2218 2219 cif-m1 { 2220 cif_clkout_m1: cif-clkout-m1 { 2221 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2222 }; 2223 2224 dvp_d2d9_m1: dvp-d2d9-m1 { 2225 rockchip,pins = 2226 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2227 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2228 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2229 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2230 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2231 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2232 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2233 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2234 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2235 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2236 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2237 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2238 }; 2239 2240 dvp_d0d1_m1: dvp-d0d1-m1 { 2241 rockchip,pins = 2242 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2243 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2244 }; 2245 2246 dvp_d10d11_m1:d10-d11-m1 { 2247 rockchip,pins = 2248 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2249 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2250 }; 2251 }; 2252 2253 isp { 2254 isp_prelight: isp-prelight { 2255 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2256 }; 2257 }; 2258 }; 2259}; 2260