1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/px30-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/px30-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35", "arm,armv8"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35", "arm,armv8"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 }; 49 cpu2: cpu@2 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35", "arm,armv8"; 52 reg = <0x0 0x2>; 53 enable-method = "psci"; 54 }; 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35", "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "psci"; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 dmc: dmc { 73 compatible = "rockchip,px30-dmc", "syscon"; 74 reg = <0x0 0xff2a0000 0x0 0x1000>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vopb_out>, <&vopl_out>; 80 status = "disabled"; 81 }; 82 83 firmware { 84 optee { 85 compatible = "linaro,optee-tz"; 86 method = "smc"; 87 }; 88 }; 89 90 gmac_clkin: external-gmac-clock { 91 compatible = "fixed-clock"; 92 clock-frequency = <50000000>; 93 clock-output-names = "gmac_clkin"; 94 #clock-cells = <0>; 95 }; 96 97 psci { 98 compatible = "arm,psci-1.0"; 99 method = "smc"; 100 }; 101 102 timer { 103 compatible = "arm,armv8-timer"; 104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 108 }; 109 110 xin24m: xin24m { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <24000000>; 114 clock-output-names = "xin24m"; 115 }; 116 117 pmu: power-management@ff000000 { 118 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 119 reg = <0x0 0xff000000 0x0 0x1000>; 120 121 power: power-controller { 122 compatible = "rockchip,px30-power-controller"; 123 #power-domain-cells = <1>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 status = "disabled"; 127 128 /* These power domains are grouped by VD_LOGIC */ 129 pd_usb@PX30_PD_USB { 130 reg = <PX30_PD_USB>; 131 clocks = <&cru HCLK_HOST>, 132 <&cru HCLK_OTG>, 133 <&cru SCLK_OTG_ADP>; 134 }; 135 pd_sdcard@PX30_PD_SDCARD { 136 reg = <PX30_PD_SDCARD>; 137 clocks = <&cru HCLK_SDMMC>, 138 <&cru SCLK_SDMMC>; 139 }; 140 pd_gmac@PX30_PD_GMAC { 141 reg = <PX30_PD_GMAC>; 142 clocks = <&cru ACLK_GMAC>, 143 <&cru PCLK_GMAC>, 144 <&cru SCLK_MAC_REF>, 145 <&cru SCLK_GMAC_RX_TX>; 146 }; 147 pd_mmc_nand@PX30_PD_MMC_NAND { 148 reg = <PX30_PD_MMC_NAND>; 149 clocks = <&cru HCLK_NANDC>, 150 <&cru HCLK_EMMC>, 151 <&cru HCLK_SDIO>, 152 <&cru HCLK_SFC>, 153 <&cru SCLK_EMMC>, 154 <&cru SCLK_NANDC>, 155 <&cru SCLK_SDIO>, 156 <&cru SCLK_SFC>; 157 }; 158 pd_vpu@PX30_PD_VPU { 159 reg = <PX30_PD_VPU>; 160 clocks = <&cru ACLK_VPU>, 161 <&cru HCLK_VPU>, 162 <&cru SCLK_CORE_VPU>; 163 }; 164 pd_vo@PX30_PD_VO { 165 reg = <PX30_PD_VO>; 166 clocks = <&cru ACLK_RGA>, 167 <&cru ACLK_VOPB>, 168 <&cru ACLK_VOPL>, 169 <&cru DCLK_VOPB>, 170 <&cru DCLK_VOPL>, 171 <&cru HCLK_RGA>, 172 <&cru HCLK_VOPB>, 173 <&cru HCLK_VOPL>, 174 <&cru PCLK_MIPI_DSI>, 175 <&cru SCLK_RGA_CORE>, 176 <&cru SCLK_VOPB_PWM>; 177 }; 178 pd_vi@PX30_PD_VI { 179 reg = <PX30_PD_VI>; 180 clocks = <&cru ACLK_CIF>, 181 <&cru ACLK_ISP>, 182 <&cru HCLK_CIF>, 183 <&cru HCLK_ISP>, 184 <&cru SCLK_ISP>; 185 }; 186 pd_gpu@PX30_PD_GPU { 187 reg = <PX30_PD_GPU>; 188 clocks = <&cru ACLK_GPU>; 189 }; 190 }; 191 }; 192 193 pmugrf: syscon@ff010000 { 194 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 195 reg = <0x0 0xff010000 0x0 0x1000>; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 199 pmu_io_domains: io-domains { 200 compatible = "rockchip,px30-pmu-io-voltage-domain"; 201 status = "disabled"; 202 }; 203 204 reboot-mode { 205 compatible = "syscon-reboot-mode"; 206 offset = <0x200>; 207 mode-bootloader = <BOOT_BL_DOWNLOAD>; 208 mode-charge = <BOOT_CHARGING>; 209 mode-fastboot = <BOOT_FASTBOOT>; 210 mode-loader = <BOOT_BL_DOWNLOAD>; 211 mode-normal = <BOOT_NORMAL>; 212 mode-recovery = <BOOT_RECOVERY>; 213 mode-ums = <BOOT_UMS>; 214 }; 215 216 pmu_pvtm: pmu-pvtm { 217 compatible = "rockchip,px30-pmu-pvtm"; 218 clocks = <&pmucru SCLK_PVTM_PMU>; 219 clock-names = "pmu"; 220 status = "disabled"; 221 }; 222 }; 223 224 uart0: serial@ff030000 { 225 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 226 reg = <0x0 0xff030000 0x0 0x100>; 227 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 229 clock-names = "baudclk", "apb_pclk"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 dmas = <&dmac 0>, <&dmac 1>; 233 #dma-cells = <2>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 236 status = "disabled"; 237 }; 238 239 i2s0_8ch: i2s@ff060000 { 240 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 241 reg = <0x0 0xff060000 0x0 0x1000>; 242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_I2S0_TX>, <&cru HCLK_I2S0>; 244 clock-names = "i2s_clk", "i2s_hclk"; 245 dmas = <&dmac 16>, <&dmac 17>; 246 dma-names = "tx", "rx"; 247 status = "disabled"; 248 }; 249 250 i2s1_2ch: i2s@ff070000 { 251 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 252 reg = <0x0 0xff070000 0x0 0x1000>; 253 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 255 clock-names = "i2s_clk", "i2s_hclk"; 256 dmas = <&dmac 18>, <&dmac 19>; 257 dma-names = "tx", "rx"; 258 status = "disabled"; 259 }; 260 261 i2s2_2ch: i2s@ff080000 { 262 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 263 reg = <0x0 0xff080000 0x0 0x1000>; 264 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 266 clock-names = "i2s_clk", "i2s_hclk"; 267 dmas = <&dmac 20>, <&dmac 21>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 pdm: pdm@ff0a0000 { 273 compatible = "rockchip,pdm"; 274 reg = <0x0 0xff0a0000 0x0 0x1000>; 275 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 276 clock-names = "pdm_clk", "pdm_hclk"; 277 dmas = <&dmac 24>; 278 dma-names = "rx"; 279 status = "disabled"; 280 }; 281 282 gic: interrupt-controller@ff131000 { 283 compatible = "arm,gic-400"; 284 #interrupt-cells = <3>; 285 #address-cells = <0>; 286 interrupt-controller; 287 reg = <0x0 0xff131000 0 0x1000>, 288 <0x0 0xff132000 0 0x2000>, 289 <0x0 0xff134000 0 0x2000>, 290 <0x0 0xff136000 0 0x2000>; 291 interrupts = <GIC_PPI 9 292 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 293 }; 294 295 grf: syscon@ff140000 { 296 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 297 reg = <0x0 0xff140000 0x0 0x1000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 301 io_domains: io-domains { 302 compatible = "rockchip,px30-io-voltage-domain"; 303 status = "disabled"; 304 }; 305 306 lvds: lvds { 307 compatible = "rockchip,px30-lvds"; 308 phys = <&video_phy>; 309 phy-names = "phy"; 310 status = "disabled"; 311 312 ports { 313 #address-cells = <1>; 314 #size-cells = <0>; 315 316 port@0 { 317 reg = <0>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 321 lvds_in_vopb: endpoint@0 { 322 reg = <0>; 323 remote-endpoint = <&vopb_out_lvds>; 324 }; 325 326 lvds_in_vopl: endpoint@1 { 327 reg = <1>; 328 remote-endpoint = <&vopl_out_lvds>; 329 }; 330 }; 331 }; 332 }; 333 334 rgb: rgb { 335 compatible = "rockchip,px30-rgb"; 336 pinctrl-names = "default", "sleep"; 337 pinctrl-0 = <&lcdc_m0_rgb_pins>; 338 pinctrl-1 = <&lcdc_m0_sleep_pins>; 339 status = "disabled"; 340 341 ports { 342 #address-cells = <1>; 343 #size-cells = <0>; 344 345 port@0 { 346 reg = <0>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 350 rgb_in_vopb: endpoint@0 { 351 reg = <0>; 352 remote-endpoint = <&vopb_out_rgb>; 353 }; 354 355 rgb_in_vopl: endpoint@1 { 356 reg = <1>; 357 remote-endpoint = <&vopl_out_rgb>; 358 }; 359 }; 360 }; 361 }; 362 }; 363 364 core_grf: syscon@ff148000 { 365 compatible = "syscon", "simple-mfd"; 366 reg = <0x0 0xff148000 0x0 0x1000>; 367 #address-cells = <1>; 368 #size-cells = <1>; 369 370 pvtm: pvtm { 371 compatible = "rockchip,px30-pvtm"; 372 clocks = <&cru SCLK_PVTM>; 373 clock-names = "core"; 374 status = "disabled"; 375 }; 376 }; 377 378 uart1: serial@ff158000 { 379 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 380 reg = <0x0 0xff158000 0x0 0x100>; 381 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 383 clock-names = "sclk_uart", "pclk_uart"; 384 reg-shift = <2>; 385 reg-io-width = <4>; 386 dmas = <&dmac 2>, <&dmac 3>; 387 #dma-cells = <2>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 390 status = "disabled"; 391 }; 392 393 uart2: serial@ff160000 { 394 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 395 reg = <0x0 0xff160000 0x0 0x100>; 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 398 clock-names = "baudclk", "apb_pclk"; 399 reg-shift = <2>; 400 reg-io-width = <4>; 401 dmas = <&dmac 4>, <&dmac 5>; 402 #dma-cells = <2>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&uart2m0_xfer>; 405 status = "disabled"; 406 }; 407 408 uart3: serial@ff168000 { 409 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 410 reg = <0x0 0xff168000 0x0 0x100>; 411 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 413 clock-names = "baudclk", "apb_pclk"; 414 reg-shift = <2>; 415 reg-io-width = <4>; 416 dmas = <&dmac 6>, <&dmac 7>; 417 #dma-cells = <2>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 420 status = "disabled"; 421 }; 422 423 uart4: serial@ff170000 { 424 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 425 reg = <0x0 0xff170000 0x0 0x100>; 426 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 428 clock-names = "baudclk", "apb_pclk"; 429 reg-shift = <2>; 430 reg-io-width = <4>; 431 dmas = <&dmac 8>, <&dmac 9>; 432 #dma-cells = <2>; 433 pinctrl-names = "default"; 434 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 435 status = "disabled"; 436 }; 437 438 uart5: serial@ff178000 { 439 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 440 reg = <0x0 0xff178000 0x0 0x100>; 441 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 443 clock-names = "baudclk", "apb_pclk"; 444 reg-shift = <2>; 445 reg-io-width = <4>; 446 dmas = <&dmac 10>, <&dmac 11>; 447 #dma-cells = <2>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 450 status = "disabled"; 451 }; 452 453 i2c0: i2c@ff180000 { 454 compatible = "rockchip,rk3399-i2c"; 455 reg = <0x0 0xff180000 0x0 0x1000>; 456 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 457 clock-names = "i2c", "pclk"; 458 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&i2c0_xfer>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 status = "disabled"; 464 }; 465 466 i2c1: i2c@ff190000 { 467 compatible = "rockchip,rk3399-i2c"; 468 reg = <0x0 0xff190000 0x0 0x1000>; 469 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 470 clock-names = "i2c", "pclk"; 471 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&i2c1_xfer>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 status = "disabled"; 477 }; 478 479 i2c2: i2c@ff1a0000 { 480 compatible = "rockchip,rk3399-i2c"; 481 reg = <0x0 0xff1a0000 0x0 0x1000>; 482 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 483 clock-names = "i2c", "pclk"; 484 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&i2c2_xfer>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 status = "disabled"; 490 }; 491 492 i2c3: i2c@ff1b0000 { 493 compatible = "rockchip,rk3399-i2c"; 494 reg = <0x0 0xff1b0000 0x0 0x1000>; 495 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 496 clock-names = "i2c", "pclk"; 497 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&i2c3_xfer>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 status = "disabled"; 503 }; 504 505 spi0: spi@ff1d0000 { 506 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 507 reg = <0x0 0xff1d0000 0x0 0x1000>; 508 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 512 clock-names = "spiclk", "apb_pclk"; 513 dmas = <&dmac 12>, <&dmac 13>; 514 #dma-cells = <2>; 515 dma-names = "tx", "rx"; 516 pinctrl-names = "default"; 517 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 518 status = "disabled"; 519 }; 520 521 spi1: spi@ff1d8000 { 522 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 523 reg = <0x0 0xff1d8000 0x0 0x1000>; 524 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 528 clock-names = "spiclk", "apb_pclk"; 529 dmas = <&dmac 14>, <&dmac 15>; 530 #dma-cells = <2>; 531 dma-names = "tx", "rx"; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&spi1_clk &spi1_csn &spi1_miso &spi1_mosi>; 534 status = "disabled"; 535 }; 536 537 wdt: watchdog@ff1e0000 { 538 compatible = "snps,dw-wdt"; 539 reg = <0x0 0xff1e0000 0x0 0x100>; 540 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 541 status = "disabled"; 542 }; 543 544 pwm0: pwm@ff200000 { 545 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 546 reg = <0x0 0xff200000 0x0 0x10>; 547 #pwm-cells = <3>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&pwm0_pin>; 550 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 551 clock-names = "pwm", "pclk"; 552 status = "disabled"; 553 }; 554 555 pwm1: pwm@ff200010 { 556 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 557 reg = <0x0 0xff200010 0x0 0x10>; 558 #pwm-cells = <3>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&pwm1_pin>; 561 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 562 clock-names = "pwm", "pclk"; 563 status = "disabled"; 564 }; 565 566 pwm2: pwm@ff200020 { 567 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 568 reg = <0x0 0xff200020 0x0 0x10>; 569 #pwm-cells = <3>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&pwm2_pin>; 572 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 573 clock-names = "pwm", "pclk"; 574 status = "disabled"; 575 }; 576 577 pwm3: pwm@ff200030 { 578 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 579 reg = <0x0 0xff200030 0x0 0x10>; 580 #pwm-cells = <3>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&pwm3_pin>; 583 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 584 clock-names = "pwm", "pclk"; 585 status = "disabled"; 586 }; 587 588 pwm4: pwm@ff208000 { 589 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 590 reg = <0x0 0xff208000 0x0 0x10>; 591 #pwm-cells = <3>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pwm4_pin>; 594 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 595 clock-names = "pwm", "pclk"; 596 status = "disabled"; 597 }; 598 599 pwm5: pwm@ff208010 { 600 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 601 reg = <0x0 0xff208010 0x0 0x10>; 602 #pwm-cells = <3>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&pwm5_pin>; 605 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 606 clock-names = "pwm", "pclk"; 607 status = "disabled"; 608 }; 609 610 pwm6: pwm@ff208020 { 611 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 612 reg = <0x0 0xff208020 0x0 0x10>; 613 #pwm-cells = <3>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&pwm6_pin>; 616 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 617 clock-names = "pwm", "pclk"; 618 status = "disabled"; 619 }; 620 621 pwm7: pwm@ff208030 { 622 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 623 reg = <0x0 0xff208030 0x0 0x10>; 624 #pwm-cells = <3>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&pwm7_pin>; 627 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 628 clock-names = "pwm", "pclk"; 629 status = "disabled"; 630 }; 631 632 amba { 633 compatible = "simple-bus"; 634 #address-cells = <2>; 635 #size-cells = <2>; 636 ranges; 637 638 dmac: dmac@ff240000 { 639 compatible = "arm,pl330", "arm,primecell"; 640 reg = <0x0 0xff240000 0x0 0x4000>; 641 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cru ACLK_DMAC>; 644 clock-names = "apb_pclk"; 645 #dma-cells = <1>; 646 peripherals-req-type-burst; 647 }; 648 }; 649 650 tsadc: tsadc@ff280000 { 651 compatible = "rockchip,px30-tsadc"; 652 reg = <0x0 0xff280000 0x0 0x100>; 653 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 654 rockchip,grf = <&grf>; 655 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 656 clock-names = "tsadc", "apb_pclk"; 657 assigned-clocks = <&cru SCLK_TSADC>; 658 assigned-clock-rates = <50000>; 659 resets = <&cru SRST_TSADC_P>; 660 reset-names = "tsadc-apb"; 661 pinctrl-names = "init", "default", "sleep"; 662 pinctrl-0 = <&tsadc_otp_gpio>; 663 pinctrl-1 = <&tsadc_otp_out>; 664 pinctrl-2 = <&tsadc_otp_gpio>; 665 #thermal-sensor-cells = <1>; 666 rockchip,hw-tshut-temp = <100000>; 667 status = "disabled"; 668 }; 669 670 saradc: saradc@ff288000 { 671 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 672 reg = <0x0 0xff288000 0x0 0x100>; 673 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 674 #io-channel-cells = <1>; 675 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 676 clock-names = "saradc", "apb_pclk"; 677 resets = <&cru SRST_SARADC_P>; 678 reset-names = "saradc-apb"; 679 status = "disabled"; 680 }; 681 682 cru: clock-controller@ff2b0000 { 683 compatible = "rockchip,px30-cru"; 684 reg = <0x0 0xff2b0000 0x0 0x9000>; 685 rockchip,grf = <&grf>; 686 #clock-cells = <1>; 687 #reset-cells = <1>; 688 689 assigned-clocks = 690 <&cru APLL_BOOST_H>, <&cru APLL_BOOST_L>, 691 <&cru PLL_NPLL>, <&cru PLL_CPLL>, 692 <&cru ARMCLK>; 693 assigned-clock-rates = 694 <1608000000>, <1416000000>, 695 <1188000000>, <1188000000>, 696 <816000000>; 697 }; 698 699 pmucru: pmu-clock-controller@ff2bc000 { 700 compatible = "rockchip,px30-pmucru"; 701 reg = <0x0 0xff2bc000 0x0 0x1000>; 702 rockchip,grf = <&grf>; 703 #clock-cells = <1>; 704 #reset-cells = <1>; 705 706 assigned-clocks = 707 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 708 <&pmucru SCLK_WIFI_PMU>, <&cru ACLK_BUS_PRE>, 709 <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, 710 <&cru HCLK_PERI_PRE>, <&cru PCLK_BUS_PRE>; 711 assigned-clock-rates = 712 <1200000000>, <100000000>, 713 <26000000>, <300000000>, 714 <300000000>, <150000000>, 715 <150000000>, <75000000>; 716 }; 717 718 usb2phy_grf: syscon@ff2c0000 { 719 compatible = "rockchip,px30-usb2phy-grf", "syscon", 720 "simple-mfd"; 721 reg = <0x0 0xff2c0000 0x0 0x10000>; 722 #address-cells = <1>; 723 #size-cells = <1>; 724 725 u2phy: usb2-phy@100 { 726 compatible = "rockchip,px30-usb2phy", 727 "rockchip,rk3328-usb2phy"; 728 reg = <0x100 0x10>; 729 clocks = <&pmucru SCLK_USBPHY_REF>; 730 clock-names = "phyclk"; 731 #clock-cells = <0>; 732 assigned-clocks = <&cru USB480M>; 733 assigned-clock-parents = <&u2phy>; 734 clock-output-names = "usb480m_phy"; 735 status = "disabled"; 736 737 u2phy_host: host-port { 738 #phy-cells = <0>; 739 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "linestate"; 741 status = "disabled"; 742 }; 743 744 u2phy_otg: otg-port { 745 #phy-cells = <0>; 746 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 749 interrupt-names = "otg-bvalid", "otg-id", 750 "linestate"; 751 status = "disabled"; 752 }; 753 }; 754 }; 755 756 video_phy: video-phy@ff2e0000 { 757 compatible = "rockchip,px30-video-phy"; 758 reg = <0x0 0xff2e0000 0x0 0x10000>, 759 <0x0 0xff450000 0x0 0x10000>; 760 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, 761 <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 762 clock-names = "ref", "pclk_phy", "pclk_host"; 763 #clock-cells = <0>; 764 resets = <&cru SRST_MIPIDSIPHY_P>; 765 reset-names = "rst"; 766 power-domains = <&power PX30_PD_VO>; 767 #phy-cells = <0>; 768 status = "disabled"; 769 }; 770 771 usb20_otg: usb@ff300000 { 772 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 773 "snps,dwc2"; 774 reg = <0x0 0xff300000 0x0 0x40000>; 775 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cru HCLK_OTG>; 777 clock-names = "otg"; 778 dr_mode = "otg"; 779 g-np-tx-fifo-size = <16>; 780 g-rx-fifo-size = <275>; 781 g-tx-fifo-size = <256 128 128 64 64 32>; 782 g-use-dma; 783 phys = <&u2phy_otg>; 784 phy-names = "usb2-phy"; 785 status = "disabled"; 786 }; 787 788 usb_host0_ehci: usb@ff340000 { 789 compatible = "generic-ehci"; 790 reg = <0x0 0xff340000 0x0 0x10000>; 791 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 793 <&u2phy>; 794 clock-names = "usbhost", "arbiter", "utmi"; 795 phys = <&u2phy_host>; 796 phy-names = "usb"; 797 status = "disabled"; 798 }; 799 800 usb_host0_ohci: usb@ff350000 { 801 compatible = "generic-ohci"; 802 reg = <0x0 0xff350000 0x0 0x10000>; 803 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 805 <&u2phy>; 806 clock-names = "usbhost", "arbiter", "utmi"; 807 phys = <&u2phy_host>; 808 phy-names = "usb"; 809 }; 810 811 gmac: ethernet@ff360000 { 812 compatible = "rockchip,px30-gmac"; 813 reg = <0x0 0xff360000 0x0 0x10000>; 814 rockchip,grf = <&grf>; 815 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "macirq"; 817 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 818 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 819 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 820 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 821 clock-names = "stmmaceth", "mac_clk_rx", 822 "mac_clk_tx", "clk_mac_ref", 823 "clk_mac_refout", "aclk_mac", 824 "pclk_mac", "clk_mac_speed"; 825 phy-mode = "rmii"; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 828 resets = <&cru SRST_GMAC_A>; 829 reset-names = "stmmaceth"; 830 power-domains = <&power PX30_PD_GMAC>; 831 status = "disabled"; 832 }; 833 834 sdmmc: dwmmc@ff370000 { 835 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 836 reg = <0x0 0xff370000 0x0 0x4000>; 837 max-frequency = <150000000>; 838 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 839 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 840 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 841 fifo-depth = <0x100>; 842 cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; 843 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 846 status = "disabled"; 847 }; 848 849 sdio: dwmmc@ff380000 { 850 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 851 reg = <0x0 0xff380000 0x0 0x4000>; 852 max-frequency = <150000000>; 853 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 854 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 855 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 856 fifo-depth = <0x100>; 857 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 858 status = "disabled"; 859 }; 860 861 emmc: dwmmc@ff390000 { 862 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 863 reg = <0x0 0xff390000 0x0 0x4000>; 864 max-frequency = <150000000>; 865 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 866 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 867 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 868 fifo-depth = <0x100>; 869 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 870 status = "disabled"; 871 }; 872 873 nandc0: nandc@ff3b0000 { 874 compatible = "rockchip,rk-nandc"; 875 reg = <0x0 0xff3b0000 0x0 0x4000>; 876 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 877 nandc_id = <0>; 878 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 879 clock-names = "clk_nandc", "hclk_nandc"; 880 status = "disabled"; 881 }; 882 883 gpu: gpu@ff400000 { 884 compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; 885 reg = <0x0 0xff400000 0x0 0x4000>; 886 887 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 890 interrupt-names = "GPU", "MMU", "JOB"; 891 892 clocks = <&cru ACLK_GPU>; 893 clock-names = "clk_mali"; 894 895 status = "disabled"; 896 }; 897 898 hevc: hevc_service@ff440000 { 899 compatible = "rockchip,hevc_sub"; 900 iommu_enabled = <1>; 901 reg = <0x0 0xff440000 0x0 0x400>; 902 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "irq_dec"; 904 dev_mode = <1>; 905 iommus = <&hevc_mmu>; 906 name = "hevc_service"; 907 allocator = <1>; 908 }; 909 910 vpu: vpu_service@ff442000 { 911 compatible = "rockchip,vpu_sub"; 912 iommu_enabled = <1>; 913 reg = <0x0 0xff442000 0x0 0x800>; 914 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "irq_enc", "irq_dec"; 917 dev_mode = <0>; 918 iommus = <&vpu_mmu>; 919 name = "vpu_service"; 920 allocator = <1>; 921 }; 922 923 vpu_combo: vpu_combo { 924 compatible = "rockchip,vpu_combo"; 925 subcnt = <2>; 926 rockchip,grf = <&grf>; 927 rockchip,sub = <&vpu>, <&hevc>; 928 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; 929 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 930 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, 931 <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, 932 <&cru SRST_VPU_CORE>; 933 reset-names = "video_a", "video_h", "niu_a", "niu_h", 934 "video_core"; 935 mode_bit = <15>; 936 mode_ctrl = <0x410>; 937 name = "vpu_combo"; 938 status = "disabled"; 939 }; 940 941 hevc_mmu: iommu@ff440440 { 942 compatible = "rockchip,iommu"; 943 reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; 944 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "hevc_mmu"; 946 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 947 clock-names = "aclk", "hclk"; 948 #iommu-cells = <0>; 949 }; 950 951 vpu_mmu: iommu@ff442800 { 952 compatible = "rockchip,iommu"; 953 reg = <0x0 0xff442800 0x0 0x100>; 954 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 955 interrupt-names = "vpu_mmu"; 956 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 957 clock-names = "aclk", "hclk"; 958 #iommu-cells = <0>; 959 }; 960 961 dsi: dsi@ff450000 { 962 compatible = "rockchip,px30-mipi-dsi"; 963 reg = <0x0 0xff450000 0x0 0x10000>; 964 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&cru PCLK_MIPI_DSI>, <&video_phy>; 966 clock-names = "pclk", "hs_clk"; 967 resets = <&cru SRST_MIPIDSI_HOST_P>; 968 reset-names = "apb"; 969 phys = <&video_phy>; 970 phy-names = "mipi_dphy"; 971 power-domains = <&power PX30_PD_VO>; 972 rockchip,grf = <&grf>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 status = "disabled"; 976 977 ports { 978 #address-cells = <1>; 979 #size-cells = <0>; 980 981 port@0 { 982 reg = <0>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 986 dsi_in_vopl: endpoint@0 { 987 reg = <0>; 988 remote-endpoint = <&vopl_out_dsi>; 989 }; 990 991 dsi_in_vopb: endpoint@1 { 992 reg = <1>; 993 remote-endpoint = <&vopb_out_dsi>; 994 }; 995 }; 996 }; 997 }; 998 999 vopb: vop@ff460000 { 1000 compatible = "rockchip,px30-vop-big"; 1001 reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; 1002 reg-names = "regs", "gamma_lut"; 1003 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1005 <&cru HCLK_VOPB>; 1006 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1007 iommus = <&vopb_mmu>; 1008 status = "disabled"; 1009 1010 vopb_out: port { 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 1014 vopb_out_lvds: endpoint@0 { 1015 reg = <0>; 1016 remote-endpoint = <&lvds_in_vopb>; 1017 }; 1018 1019 vopb_out_dsi: endpoint@1 { 1020 reg = <1>; 1021 remote-endpoint = <&dsi_in_vopb>; 1022 }; 1023 1024 vopb_out_rgb: endpoint@2 { 1025 reg = <2>; 1026 remote-endpoint = <&rgb_in_vopb>; 1027 }; 1028 }; 1029 }; 1030 1031 vopb_mmu: iommu@ff460f00 { 1032 compatible = "rockchip,iommu"; 1033 reg = <0x0 0xff460f00 0x0 0x100>; 1034 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupt-names = "vopb_mmu"; 1036 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1037 clock-names = "aclk", "hclk"; 1038 #iommu-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 vopl: vop@ff470000 { 1043 compatible = "rockchip,px30-vop-lit"; 1044 reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; 1045 reg-names = "regs", "gamma_lut"; 1046 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1048 <&cru HCLK_VOPL>; 1049 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1050 iommus = <&vopl_mmu>; 1051 status = "disabled"; 1052 1053 vopl_out: port { 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 1057 vopl_out_lvds: endpoint@0 { 1058 reg = <0>; 1059 remote-endpoint = <&lvds_in_vopl>; 1060 }; 1061 1062 vopl_out_dsi: endpoint@1 { 1063 reg = <1>; 1064 remote-endpoint = <&dsi_in_vopl>; 1065 }; 1066 1067 vopl_out_rgb: endpoint@2 { 1068 reg = <2>; 1069 remote-endpoint = <&rgb_in_vopl>; 1070 }; 1071 }; 1072 }; 1073 1074 vopl_mmu: iommu@ff470f00 { 1075 compatible = "rockchip,iommu"; 1076 reg = <0x0 0xff470f00 0x0 0x100>; 1077 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1078 interrupt-names = "vopl_mmu"; 1079 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1080 clock-names = "aclk", "hclk"; 1081 #iommu-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 rk_rga: rk_rga@ff480000 { 1086 compatible = "rockchip,rga2"; 1087 //dev_mode = <1>; 1088 reg = <0x0 0xff480000 0x0 0x1000>; 1089 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; 1091 clock-names = "aclk_rga", "hclk_rga"; 1092 dma-coherent; 1093 status = "disabled"; 1094 }; 1095 1096 cif: cif@ff490000 { 1097 compatible = "rockchip,cif"; 1098 reg = <0x0 0xff490000 0x0 0x200>; 1099 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; 1101 clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; 1102 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; 1103 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; 1104 pinctrl-names = "cif_pin_all"; 1105 pinctrl-0 = <&dvp_d2d9_m0>; 1106 status = "disabled"; 1107 }; 1108 1109 vip_mmu: iommu@ff490800{ 1110 compatible = "rockchip,iommu"; 1111 reg = <0x0 0xff490800 0x0 0x100>; 1112 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1113 interrupt-names = "vip_mmu"; 1114 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1115 clock-names = "aclk", "hclk"; 1116 rk_iommu,disable_reset_quirk; 1117 #iommu-cells = <0>; 1118 status = "disabled"; 1119 }; 1120 1121 rk_isp: rk_isp@ff4a0000 { 1122 compatible = "rockchip,px30-isp", "rockchip,isp"; 1123 reg = <0x0 0xff4a0000 0x0 0x4000>; 1124 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, 1126 <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; 1127 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", 1128 "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; 1129 resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; 1130 reset-names = "rst_isp", "rst_mipicsiphy"; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&cif_clkout_m0>; 1133 rockchip,isp,mipiphy = <0>; 1134 rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; 1135 rockchip,grf = <&grf>; 1136 rockchip,cru = <&cru>; 1137 rockchip,isp,iommu-enable = <1>; 1138 iommus = <&isp_mmu>; 1139 status = "disabled"; 1140 }; 1141 1142 isp_mmu: iommu@ff4a8000 { 1143 compatible = "rockchip,iommu"; 1144 reg = <0x0 0xff4a8000 0x0 0x100>; 1145 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1146 interrupt-names = "isp_mmu"; 1147 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1148 clock-names = "aclk", "hclk"; 1149 rk_iommu,disable_reset_quirk; 1150 #iommu-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 qos_gmac: qos@ff518000 { 1155 compatible = "syscon"; 1156 reg = <0x0 0xff518000 0x0 0x20>; 1157 }; 1158 1159 qos_gpu: qos@ff520000 { 1160 compatible = "syscon"; 1161 reg = <0x0 0xff520000 0x0 0x20>; 1162 }; 1163 1164 qos_sdmmc: qos@ff52c000 { 1165 compatible = "syscon"; 1166 reg = <0x0 0xff52c000 0x0 0x20>; 1167 }; 1168 1169 qos_emmc: qos@ff538000 { 1170 compatible = "syscon"; 1171 reg = <0x0 0xff538000 0x0 0x20>; 1172 }; 1173 1174 qos_nand: qos@ff538080 { 1175 compatible = "syscon"; 1176 reg = <0x0 0xff538080 0x0 0x20>; 1177 }; 1178 1179 qos_sdio: qos@ff538100 { 1180 compatible = "syscon"; 1181 reg = <0x0 0xff538100 0x0 0x20>; 1182 }; 1183 1184 qos_sfc: qos@ff538180 { 1185 compatible = "syscon"; 1186 reg = <0x0 0xff538180 0x0 0x20>; 1187 }; 1188 1189 qos_usb_host: qos@ff540000 { 1190 compatible = "syscon"; 1191 reg = <0x0 0xff540000 0x0 0x20>; 1192 }; 1193 1194 qos_usb_otg: qos@ff540080 { 1195 compatible = "syscon"; 1196 reg = <0x0 0xff540080 0x0 0x20>; 1197 }; 1198 1199 qos_isp_128: qos@ff548000 { 1200 compatible = "syscon"; 1201 reg = <0x0 0xff548000 0x0 0x20>; 1202 }; 1203 1204 qos_isp_rd: qos@ff548080 { 1205 compatible = "syscon"; 1206 reg = <0x0 0xff548080 0x0 0x20>; 1207 }; 1208 1209 qos_isp_wr: qos@ff548100 { 1210 compatible = "syscon"; 1211 reg = <0x0 0xff548100 0x0 0x20>; 1212 }; 1213 1214 qos_isp_m1: qos@ff548180 { 1215 compatible = "syscon"; 1216 reg = <0x0 0xff548180 0x0 0x20>; 1217 }; 1218 1219 qos_vip: qos@ff548200 { 1220 compatible = "syscon"; 1221 reg = <0x0 0xff548200 0x0 0x20>; 1222 }; 1223 1224 qos_rga_rd: qos@ff550000 { 1225 compatible = "syscon"; 1226 reg = <0x0 0xff550000 0x0 0x20>; 1227 }; 1228 1229 qos_rga_wr: qos@ff550080 { 1230 compatible = "syscon"; 1231 reg = <0x0 0xff550080 0x0 0x20>; 1232 }; 1233 1234 qos_vop_m0: qos@ff550100 { 1235 compatible = "syscon"; 1236 reg = <0x0 0xff550100 0x0 0x20>; 1237 }; 1238 1239 qos_vop_m1: qos@ff550180 { 1240 compatible = "syscon"; 1241 reg = <0x0 0xff550180 0x0 0x20>; 1242 }; 1243 1244 qos_vpu: qos@ff558000 { 1245 compatible = "syscon"; 1246 reg = <0x0 0xff558000 0x0 0x20>; 1247 }; 1248 1249 qos_vpu_r128: qos@ff558080 { 1250 compatible = "syscon"; 1251 reg = <0x0 0xff558080 0x0 0x20>; 1252 }; 1253 1254 pinctrl: pinctrl { 1255 compatible = "rockchip,px30-pinctrl"; 1256 rockchip,grf = <&grf>; 1257 rockchip,pmu = <&pmugrf>; 1258 #address-cells = <2>; 1259 #size-cells = <2>; 1260 ranges; 1261 1262 gpio0: gpio0@ff040000 { 1263 compatible = "rockchip,gpio-bank"; 1264 reg = <0x0 0xff040000 0x0 0x100>; 1265 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&cru PCLK_GPIO0_PMU>; 1267 gpio-controller; 1268 #gpio-cells = <2>; 1269 1270 interrupt-controller; 1271 #interrupt-cells = <2>; 1272 }; 1273 1274 gpio1: gpio1@ff250000 { 1275 compatible = "rockchip,gpio-bank"; 1276 reg = <0x0 0xff250000 0x0 0x100>; 1277 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&cru PCLK_GPIO1>; 1279 gpio-controller; 1280 #gpio-cells = <2>; 1281 1282 interrupt-controller; 1283 #interrupt-cells = <2>; 1284 }; 1285 1286 gpio2: gpio2@ff260000 { 1287 compatible = "rockchip,gpio-bank"; 1288 reg = <0x0 0xff260000 0x0 0x100>; 1289 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1290 clocks = <&cru PCLK_GPIO2>; 1291 gpio-controller; 1292 #gpio-cells = <2>; 1293 1294 interrupt-controller; 1295 #interrupt-cells = <2>; 1296 }; 1297 1298 gpio3: gpio3@ff270000 { 1299 compatible = "rockchip,gpio-bank"; 1300 reg = <0x0 0xff270000 0x0 0x100>; 1301 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1302 clocks = <&cru PCLK_GPIO3>; 1303 gpio-controller; 1304 #gpio-cells = <2>; 1305 1306 interrupt-controller; 1307 #interrupt-cells = <2>; 1308 }; 1309 1310 pcfg_pull_up: pcfg-pull-up { 1311 bias-pull-up; 1312 }; 1313 1314 pcfg_pull_down: pcfg-pull-down { 1315 bias-pull-down; 1316 }; 1317 1318 pcfg_pull_none: pcfg-pull-none { 1319 bias-disable; 1320 }; 1321 1322 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1323 bias-disable; 1324 drive-strength = <2>; 1325 }; 1326 1327 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1328 bias-pull-up; 1329 drive-strength = <2>; 1330 }; 1331 1332 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1333 bias-pull-up; 1334 drive-strength = <4>; 1335 }; 1336 1337 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1338 bias-disable; 1339 drive-strength = <4>; 1340 }; 1341 1342 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1343 bias-pull-down; 1344 drive-strength = <4>; 1345 }; 1346 1347 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1348 bias-disable; 1349 drive-strength = <8>; 1350 }; 1351 1352 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1353 bias-pull-up; 1354 drive-strength = <8>; 1355 }; 1356 1357 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1358 bias-disable; 1359 drive-strength = <12>; 1360 }; 1361 1362 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1363 bias-pull-up; 1364 drive-strength = <12>; 1365 }; 1366 1367 pcfg_pull_none_smt: pcfg-pull-none-smt { 1368 bias-disable; 1369 input-schmitt-enable; 1370 }; 1371 1372 pcfg_output_high: pcfg-output-high { 1373 output-high; 1374 }; 1375 1376 pcfg_output_low: pcfg-output-low { 1377 output-low; 1378 }; 1379 1380 pcfg_input_high: pcfg-input-high { 1381 bias-pull-up; 1382 input-enable; 1383 }; 1384 1385 pcfg_input: pcfg-input { 1386 input-enable; 1387 }; 1388 1389 i2c0 { 1390 i2c0_xfer: i2c0-xfer { 1391 rockchip,pins = 1392 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none_smt>, 1393 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>; 1394 }; 1395 }; 1396 1397 i2c1 { 1398 i2c1_xfer: i2c1-xfer { 1399 rockchip,pins = 1400 <0 RK_PC2 RK_FUNC_1 &pcfg_pull_none_smt>, 1401 <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none_smt>; 1402 }; 1403 }; 1404 1405 i2c2 { 1406 i2c2_xfer: i2c2-xfer { 1407 rockchip,pins = 1408 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none_smt>, 1409 <2 RK_PC0 RK_FUNC_2 &pcfg_pull_none_smt>; 1410 }; 1411 }; 1412 1413 i2c3 { 1414 i2c3_xfer: i2c3-xfer { 1415 rockchip,pins = 1416 <1 RK_PB4 RK_FUNC_4 &pcfg_pull_none_smt>, 1417 <1 RK_PB5 RK_FUNC_4 &pcfg_pull_none_smt>; 1418 }; 1419 }; 1420 1421 tsadc { 1422 tsadc_otp_gpio: tsadc-otp-gpio { 1423 rockchip,pins = 1424 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1425 }; 1426 1427 tsadc_otp_out: tsadc-otp-out { 1428 rockchip,pins = 1429 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 1430 }; 1431 }; 1432 1433 uart0 { 1434 uart0_xfer: uart0-xfer { 1435 rockchip,pins = 1436 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1437 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1438 }; 1439 1440 uart0_cts: uart0-cts { 1441 rockchip,pins = 1442 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1443 }; 1444 1445 uart0_rts: uart0-rts { 1446 rockchip,pins = 1447 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1448 }; 1449 1450 uart0_rts_gpio: uart0-rts-gpio { 1451 rockchip,pins = 1452 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1453 }; 1454 }; 1455 1456 uart1 { 1457 uart1_xfer: uart1-xfer { 1458 rockchip,pins = 1459 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>, 1460 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1461 }; 1462 1463 uart1_cts: uart1-cts { 1464 rockchip,pins = 1465 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1466 }; 1467 1468 uart1_rts: uart1-rts { 1469 rockchip,pins = 1470 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1471 }; 1472 1473 uart1_rts_gpio: uart1-rts-gpio { 1474 rockchip,pins = 1475 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1476 }; 1477 }; 1478 1479 uart2-m0 { 1480 uart2m0_xfer: uart2m0-xfer { 1481 rockchip,pins = 1482 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>, 1483 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>; 1484 }; 1485 }; 1486 1487 uart2-m1 { 1488 uart2m1_xfer: uart2m1-xfer { 1489 rockchip,pins = 1490 <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 1491 <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1492 }; 1493 }; 1494 1495 uart3-m0 { 1496 uart3m0_xfer: uart3m0-xfer { 1497 rockchip,pins = 1498 <0 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 1499 <0 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1500 }; 1501 1502 uart3m0_cts: uart3m0-cts { 1503 rockchip,pins = 1504 <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1505 }; 1506 1507 uart3m0_rts: uart3m0-rts { 1508 rockchip,pins = 1509 <0 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1510 }; 1511 1512 uart3m0_rts_gpio: uart3m0-rts-gpio { 1513 rockchip,pins = 1514 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 1515 }; 1516 }; 1517 1518 uart3-m1 { 1519 uart3m1_xfer: uart3m1-xfer { 1520 rockchip,pins = 1521 <1 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 1522 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1523 }; 1524 1525 uart3m1_cts: uart3m1-cts { 1526 rockchip,pins = 1527 <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1528 }; 1529 1530 uart3m1_rts: uart3m1-rts { 1531 rockchip,pins = 1532 <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1533 }; 1534 1535 uart3m1_rts_gpio: uart3m1-rts-gpio { 1536 rockchip,pins = 1537 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1538 }; 1539 }; 1540 1541 uart4 { 1542 1543 uart4_xfer: uart4-xfer { 1544 rockchip,pins = 1545 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_up>, 1546 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>; 1547 }; 1548 1549 uart4_cts: uart4-cts { 1550 rockchip,pins = 1551 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 1552 1553 }; 1554 1555 uart4_rts: uart4-rts { 1556 rockchip,pins = 1557 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 1558 }; 1559 }; 1560 1561 uart5 { 1562 1563 uart5_xfer: uart5-xfer { 1564 rockchip,pins = 1565 <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>, 1566 <3 RK_PA1 RK_FUNC_4 &pcfg_pull_none>; 1567 }; 1568 1569 uart5_cts: uart5-cts { 1570 rockchip,pins = 1571 <3 RK_PA3 RK_FUNC_4 &pcfg_pull_none>; 1572 1573 }; 1574 1575 uart5_rts: uart5-rts { 1576 rockchip,pins = 1577 <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>; 1578 }; 1579 }; 1580 1581 spi0 { 1582 spi0_clk: spi0-clk { 1583 rockchip,pins = 1584 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_up>; 1585 }; 1586 1587 spi0_csn: spi0-csn { 1588 rockchip,pins = 1589 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_up>; 1590 }; 1591 1592 spi0_miso: spi0-miso { 1593 rockchip,pins = 1594 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_up>; 1595 }; 1596 1597 spi0_mosi: spi0-mosi { 1598 rockchip,pins = 1599 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_up>; 1600 }; 1601 }; 1602 1603 spi1 { 1604 spi1_clk: spi1-clk { 1605 rockchip,pins = 1606 <3 RK_PB7 RK_FUNC_4 &pcfg_pull_up>; 1607 }; 1608 1609 spi1_csn: spi1-csn { 1610 rockchip,pins = 1611 <3 RK_PB1 RK_FUNC_4 &pcfg_pull_up>; 1612 }; 1613 1614 spi1_miso: spi1-miso { 1615 rockchip,pins = 1616 <3 RK_PB6 RK_FUNC_4 &pcfg_pull_up>; 1617 }; 1618 1619 spi1_mosi: spi1-mosi { 1620 rockchip,pins = 1621 <3 RK_PB4 RK_FUNC_4 &pcfg_pull_up>; 1622 }; 1623 }; 1624 1625 pdm { 1626 pdm_clk0m0: pdm-clk0m0 { 1627 rockchip,pins = 1628 <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 1629 }; 1630 1631 pdm_clk0m1: pdm-clk0m1 { 1632 rockchip,pins = 1633 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 1634 }; 1635 1636 pdm_clk1: pdm-clk1 { 1637 rockchip,pins = 1638 <3 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1639 }; 1640 1641 pdm_sdi0m0: pdm-sdi0m0 { 1642 rockchip,pins = 1643 <3 RK_PD3 RK_FUNC_4 &pcfg_pull_none>; 1644 }; 1645 1646 pdm_sdi0m1: pdm-sdi0m1 { 1647 rockchip,pins = 1648 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1649 }; 1650 1651 pdm_sdi1: pdm-sdi1 { 1652 rockchip,pins = 1653 <3 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 1654 }; 1655 1656 pdm_sdi2: pdm-sdi2 { 1657 rockchip,pins = 1658 <3 RK_PD1 RK_FUNC_2 &pcfg_pull_none>; 1659 }; 1660 1661 pdm_sdi3: pdm-sdi3 { 1662 rockchip,pins = 1663 <3 RK_PD2 RK_FUNC_4 &pcfg_pull_none>; 1664 }; 1665 1666 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1667 rockchip,pins = 1668 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1669 }; 1670 1671 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1672 rockchip,pins = 1673 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1674 }; 1675 1676 pdm_clk1_sleep: pdm-clk1-sleep { 1677 rockchip,pins = 1678 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1679 }; 1680 1681 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1682 rockchip,pins = 1683 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1684 }; 1685 1686 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1687 rockchip,pins = 1688 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1689 }; 1690 1691 pdm_sdi1_sleep: pdm-sdi1-sleep { 1692 rockchip,pins = 1693 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1694 }; 1695 1696 pdm_sdi2_sleep: pdm-sdi2-sleep { 1697 rockchip,pins = 1698 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1699 }; 1700 1701 pdm_sdi3_sleep: pdm-sdi3-sleep { 1702 rockchip,pins = 1703 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1704 }; 1705 }; 1706 1707 i2s0 { 1708 i2s0_8ch_mclk: i2s0-8ch-mclk { 1709 rockchip,pins = 1710 <3 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 1711 }; 1712 1713 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1714 rockchip,pins = 1715 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 1716 }; 1717 1718 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1719 rockchip,pins = 1720 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 1721 }; 1722 1723 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1724 rockchip,pins = 1725 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 1726 }; 1727 1728 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1729 rockchip,pins = 1730 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 1731 }; 1732 1733 i2s0_8ch_sdo: i2s0-8ch-sdo { 1734 rockchip,pins = 1735 <3 RK_PD2 RK_FUNC_3 &pcfg_pull_none>; 1736 }; 1737 1738 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1739 rockchip,pins = 1740 <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; 1741 }; 1742 1743 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1744 rockchip,pins = 1745 <3 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1746 }; 1747 1748 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1749 rockchip,pins = 1750 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 1751 }; 1752 1753 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1754 rockchip,pins = 1755 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_none>; 1756 }; 1757 1758 i2s0_8ch_sdi: i2s0-8ch-sdi { 1759 rockchip,pins = 1760 <3 RK_PD3 RK_FUNC_3 &pcfg_pull_none>; 1761 }; 1762 1763 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1764 rockchip,pins = 1765 <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none>; 1766 }; 1767 1768 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1769 rockchip,pins = 1770 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1771 }; 1772 1773 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1774 rockchip,pins = 1775 <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1776 }; 1777 1778 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1779 rockchip,pins = 1780 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1781 }; 1782 }; 1783 1784 i2s1 { 1785 i2s1_2ch_mclk: i2s1-2ch-mclk { 1786 rockchip,pins = 1787 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 1788 }; 1789 1790 i2s1_2ch_sclk: i2s1-2ch-sclk { 1791 rockchip,pins = 1792 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 1793 }; 1794 1795 i2s1_2ch_lrck: i2s1-2ch-lrck { 1796 rockchip,pins = 1797 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 1798 }; 1799 1800 i2s1_2ch_sdi: i2s1-2ch-sdi { 1801 rockchip,pins = 1802 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1803 }; 1804 1805 i2s1_2ch_sdo: i2s1-2ch-sdo { 1806 rockchip,pins = 1807 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1808 }; 1809 }; 1810 1811 i2s2 { 1812 i2s2_2ch_mclk: i2s2-2ch-mclk { 1813 rockchip,pins = 1814 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>; 1815 }; 1816 1817 i2s2_2ch_sclk: i2s2-2ch-sclk { 1818 rockchip,pins = 1819 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; 1820 }; 1821 1822 i2s2_2ch_lrck: i2s2-2ch-lrck { 1823 rockchip,pins = 1824 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>; 1825 }; 1826 1827 i2s2_2ch_sdi: i2s2-2ch-sdi { 1828 rockchip,pins = 1829 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>; 1830 }; 1831 1832 i2s2_2ch_sdo: i2s2-2ch-sdo { 1833 rockchip,pins = 1834 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1835 }; 1836 }; 1837 1838 sdmmc { 1839 sdmmc_clk: sdmmc-clk { 1840 rockchip,pins = 1841 <1 RK_PD6 RK_FUNC_1 &pcfg_pull_none_8ma>; 1842 }; 1843 1844 sdmmc_cmd: sdmmc-cmd { 1845 rockchip,pins = 1846 <1 RK_PD7 RK_FUNC_1 &pcfg_pull_up_8ma>; 1847 }; 1848 1849 sdmmc_det: sdmmc-det { 1850 rockchip,pins = 1851 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up_8ma>; 1852 }; 1853 1854 sdmmc_bus1: sdmmc-bus1 { 1855 rockchip,pins = 1856 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>; 1857 }; 1858 1859 sdmmc_bus4: sdmmc-bus4 { 1860 rockchip,pins = 1861 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_up_8ma>, 1862 <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up_8ma>, 1863 <1 RK_PD4 RK_FUNC_1 &pcfg_pull_up_8ma>, 1864 <1 RK_PD5 RK_FUNC_1 &pcfg_pull_up_8ma>; 1865 }; 1866 1867 sdmmc_gpio: sdmmc-gpio { 1868 rockchip,pins = 1869 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1870 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1871 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1872 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1873 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1874 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1875 }; 1876 }; 1877 1878 sdio { 1879 sdio_clk: sdio-clk { 1880 rockchip,pins = 1881 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1882 }; 1883 1884 sdio_cmd: sdio-cmd { 1885 rockchip,pins = 1886 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1887 }; 1888 1889 sdio_bus4: sdio-bus4 { 1890 rockchip,pins = 1891 <1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1892 <1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>, 1893 <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>, 1894 <1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>; 1895 }; 1896 1897 sdio_gpio: sdio-gpio { 1898 rockchip,pins = 1899 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 1900 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, 1901 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, 1902 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, 1903 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, 1904 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 1905 }; 1906 }; 1907 1908 emmc { 1909 emmc_clk: emmc-clk { 1910 rockchip,pins = 1911 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_8ma>; 1912 }; 1913 1914 emmc_cmd: emmc-cmd { 1915 rockchip,pins = 1916 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up_8ma>; 1917 }; 1918 1919 emmc_pwren: emmc-pwren { 1920 rockchip,pins = 1921 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 1922 }; 1923 1924 emmc_rstnout: emmc-rstnout { 1925 rockchip,pins = 1926 <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 1927 }; 1928 1929 emmc_bus1: emmc-bus1 { 1930 rockchip,pins = 1931 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>; 1932 }; 1933 1934 emmc_bus4: emmc-bus4 { 1935 rockchip,pins = 1936 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1937 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1938 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1939 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>; 1940 }; 1941 1942 emmc_bus8: emmc-bus8 { 1943 rockchip,pins = 1944 <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up_8ma>, 1945 <1 RK_PA1 RK_FUNC_2 &pcfg_pull_up_8ma>, 1946 <1 RK_PA2 RK_FUNC_2 &pcfg_pull_up_8ma>, 1947 <1 RK_PA3 RK_FUNC_2 &pcfg_pull_up_8ma>, 1948 <1 RK_PA4 RK_FUNC_2 &pcfg_pull_up_8ma>, 1949 <1 RK_PA5 RK_FUNC_2 &pcfg_pull_up_8ma>, 1950 <1 RK_PA6 RK_FUNC_2 &pcfg_pull_up_8ma>, 1951 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up_8ma>; 1952 }; 1953 }; 1954 1955 flash { 1956 flash_cs0: flash-cs0 { 1957 rockchip,pins = 1958 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 1959 }; 1960 1961 flash_rdy: flash-rdy { 1962 rockchip,pins = 1963 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>; 1964 }; 1965 1966 flash_dqs: flash-dqs { 1967 rockchip,pins = 1968 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 1969 }; 1970 1971 flash_ale: flash-ale { 1972 rockchip,pins = 1973 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1974 }; 1975 1976 flash_cle: flash-cle { 1977 rockchip,pins = 1978 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1979 }; 1980 1981 flash_wrn: flash-wrn { 1982 rockchip,pins = 1983 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 1984 }; 1985 1986 flash_csl: flash-csl { 1987 rockchip,pins = 1988 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 1989 }; 1990 1991 flash_rdn: flash-rdn { 1992 rockchip,pins = 1993 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 1994 }; 1995 1996 flash_bus8: flash-bus8 { 1997 rockchip,pins = 1998 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_12ma>, 1999 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_12ma>, 2000 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_12ma>, 2001 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_12ma>, 2002 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_12ma>, 2003 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_12ma>, 2004 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_up_12ma>, 2005 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_12ma>; 2006 }; 2007 }; 2008 2009 lcdc { 2010 lcdc_m0_rgb_pins: lcdc-m0-rgb-pins { 2011 rockchip,pins = 2012 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 2013 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_HSYNC */ 2014 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_VSYNC */ 2015 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DEN */ 2016 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 2017 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D1 */ 2018 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 2019 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D3 */ 2020 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D4 */ 2021 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D5 */ 2022 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 2023 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 2024 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D8 */ 2025 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 2026 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D10 */ 2027 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D11 */ 2028 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 2029 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 2030 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 2031 <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 2032 <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 2033 <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 2034 <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 2035 <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 2036 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 2037 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 2038 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 2039 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ 2040 }; 2041 2042 lcdc_m0_sleep_pins: lcdc-m0-sleep-pins { 2043 rockchip,pins = 2044 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 2045 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ 2046 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ 2047 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ 2048 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 2049 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D1 */ 2050 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 2051 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D3 */ 2052 <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D4 */ 2053 <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D5 */ 2054 <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 2055 <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 2056 <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D8 */ 2057 <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 2058 <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ 2059 <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ 2060 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 2061 <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 2062 <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 2063 <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 2064 <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 2065 <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 2066 <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 2067 <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 2068 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 2069 <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 2070 <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 2071 <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ 2072 }; 2073 }; 2074 2075 pwm0 { 2076 pwm0_pin: pwm0-pin { 2077 rockchip,pins = 2078 <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 2079 }; 2080 }; 2081 2082 pwm1 { 2083 pwm1_pin: pwm1-pin { 2084 rockchip,pins = 2085 <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2086 }; 2087 }; 2088 2089 pwm2 { 2090 pwm2_pin: pwm2-pin { 2091 rockchip,pins = 2092 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>; 2093 }; 2094 }; 2095 2096 pwm3 { 2097 pwm3_pin: pwm3-pin { 2098 rockchip,pins = 2099 <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2100 }; 2101 }; 2102 2103 pwm4 { 2104 pwm4_pin: pwm4-pin { 2105 rockchip,pins = 2106 <3 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2107 }; 2108 }; 2109 2110 pwm5 { 2111 pwm5_pin: pwm5-pin { 2112 rockchip,pins = 2113 <3 RK_PC3 RK_FUNC_3 &pcfg_pull_none>; 2114 }; 2115 }; 2116 2117 pwm6 { 2118 pwm6_pin: pwm6-pin { 2119 rockchip,pins = 2120 <3 RK_PC4 RK_FUNC_3 &pcfg_pull_none>; 2121 }; 2122 }; 2123 2124 pwm7 { 2125 pwm7_pin: pwm7-pin { 2126 rockchip,pins = 2127 <3 RK_PC5 RK_FUNC_3 &pcfg_pull_none>; 2128 }; 2129 }; 2130 2131 gmac { 2132 rmii_pins: rmii-pins { 2133 rockchip,pins = 2134 /* mac_txen */ 2135 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>, 2136 /* mac_txd1 */ 2137 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2138 /* mac_txd0 */ 2139 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_none_12ma>, 2140 /* mac_rxd0 */ 2141 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_none>, 2142 /* mac_rxd1 */ 2143 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>, 2144 /* mac_rxer */ 2145 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>, 2146 /* mac_rxdv */ 2147 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_none>, 2148 /* mac_mdio */ 2149 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, 2150 /* mac_mdc */ 2151 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2152 }; 2153 2154 mac_refclk_12ma: mac-refclk-12ma { 2155 rockchip,pins = 2156 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none_12ma>; 2157 }; 2158 2159 mac_refclk: mac-refclk { 2160 rockchip,pins = 2161 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2162 }; 2163 }; 2164 2165 cif-m0 { 2166 cif_clkout_m0: cif-clkout-m0 { 2167 rockchip,pins = <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2168 }; 2169 2170 dvp_d2d9_m0: dvp-d2d9-m0 { 2171 rockchip,pins = 2172 <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2173 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2174 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2175 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2176 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2177 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2178 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2179 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2180 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_sync */ 2181 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */ 2182 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,/* cif_clkin */ 2183 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkout */ 2184 }; 2185 2186 dvp_d0d1_m0: dvp-d0d1-m0 { 2187 rockchip,pins = 2188 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data0 */ 2189 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;/* cif_data1 */ 2190 }; 2191 2192 dvp_d10d11_m0:d10-d11-m0 { 2193 rockchip,pins = 2194 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data10 */ 2195 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;/* cif_data11 */ 2196 }; 2197 }; 2198 2199 cif-m1 { 2200 cif_clkout_m1: cif-clkout-m1 { 2201 rockchip,pins = <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2202 }; 2203 2204 dvp_d2d9_m1: dvp-d2d9-m1 { 2205 rockchip,pins = 2206 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */ 2207 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */ 2208 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */ 2209 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */ 2210 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */ 2211 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */ 2212 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */ 2213 <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */ 2214 <3 RK_PD1 RK_FUNC_3 &pcfg_pull_none>,/* cif_sync */ 2215 <3 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,/* cif_href */ 2216 <3 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,/* cif_clkin */ 2217 <3 RK_PD0 RK_FUNC_3 &pcfg_pull_none>;/* cif_clkout */ 2218 }; 2219 2220 dvp_d0d1_m1: dvp-d0d1-m1 { 2221 rockchip,pins = 2222 <3 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,/* cif_data0 */ 2223 <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none>;/* cif_data1 */ 2224 }; 2225 2226 dvp_d10d11_m1:d10-d11-m1 { 2227 rockchip,pins = 2228 <3 RK_PC6 RK_FUNC_3 &pcfg_pull_none>,/* cif_data10 */ 2229 <3 RK_PC7 RK_FUNC_3 &pcfg_pull_none>;/* cif_data11 */ 2230 }; 2231 }; 2232 2233 isp { 2234 isp_prelight: isp-prelight { 2235 rockchip,pins = <3 RK_PD1 RK_FUNC_4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */ 2236 }; 2237 }; 2238 }; 2239}; 2240