xref: /rk3399_rockchip-uboot/arch/arm/dts/px30-u-boot.dtsi (revision d0ff3d454829105c81afe7f5d8c79e0d3d18c1a2) 
1/*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &emmc;
10		mmc1 = &sdmmc;
11	};
12
13	chosen {
14		u-boot,spl-boot-order = &emmc, &sdmmc;
15		stdout-path = &uart2;
16	};
17};
18
19&dmc {
20	u-boot,dm-pre-reloc;
21};
22
23&uart2 {
24	clock-frequency = <24000000>;
25	u-boot,dm-pre-reloc;
26};
27
28&nandc0 {
29	u-boot,dm-spl;
30	status = "okay";
31};
32
33&sdmmc {
34	u-boot,dm-spl;
35};
36
37&emmc {
38	u-boot,dm-spl;
39};
40
41&pmugrf {
42	u-boot,dm-pre-reloc;
43};
44
45&cru {
46	u-boot,dm-pre-reloc;
47};
48
49&crypto {
50	u-boot,dm-pre-reloc;
51};
52
53&pmucru {
54	u-boot,dm-pre-reloc;
55};
56
57&saradc {
58	u-boot,dm-spl;
59	status = "okay";
60};
61
62&gpio0 {
63	u-boot,dm-spl;
64	status = "disabled";
65};
66
67&gpio1 {
68	u-boot,dm-spl;
69	status = "disabled";
70};
71
72&gpio2 {
73	u-boot,dm-spl;
74	status = "disabled";
75};
76
77&gpio3 {
78	u-boot,dm-spl;
79	status = "disabled";
80};
81
82&usb20_otg {
83	u-boot,dm-spl;
84};
85
86&usb2phy_grf {
87	u-boot,dm-spl;
88	status = "okay";
89};
90
91&u2phy {
92	u-boot,dm-spl;
93	status = "okay";
94};
95
96&u2phy_otg {
97	u-boot,dm-spl;
98	status = "okay";
99};
100