xref: /rk3399_rockchip-uboot/arch/arm/dts/px30-u-boot.dtsi (revision 73b4df6a98d2d973cbf1e2b18947abbdbdb82bc1) 
1/*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &emmc;
10		mmc1 = &sdmmc;
11	};
12
13	chosen {
14		u-boot,spl-boot-order = &emmc, &sdmmc;
15		stdout-path = &uart2;
16	};
17};
18
19&dmc {
20	u-boot,dm-pre-reloc;
21};
22
23&uart5 {
24	clock-frequency = <24000000>;
25	u-boot,dm-pre-reloc;
26};
27
28&uart2 {
29	clock-frequency = <24000000>;
30	u-boot,dm-pre-reloc;
31};
32
33&nandc0 {
34	u-boot,dm-spl;
35	status = "okay";
36};
37
38&sdmmc {
39	u-boot,dm-spl;
40};
41
42&emmc {
43	u-boot,dm-spl;
44};
45
46&pmugrf {
47	u-boot,dm-pre-reloc;
48};
49
50&cru {
51	u-boot,dm-pre-reloc;
52};
53
54&crypto {
55	u-boot,dm-pre-reloc;
56};
57
58&pmucru {
59	u-boot,dm-pre-reloc;
60};
61
62&saradc {
63	u-boot,dm-spl;
64	status = "okay";
65};
66
67&gpio0 {
68	u-boot,dm-spl;
69	status = "disabled";
70};
71
72&gpio1 {
73	u-boot,dm-spl;
74	status = "disabled";
75};
76
77&gpio2 {
78	u-boot,dm-spl;
79	status = "disabled";
80};
81
82&gpio3 {
83	u-boot,dm-spl;
84	status = "disabled";
85};
86
87&usb20_otg {
88	u-boot,dm-spl;
89};
90
91&usb2phy_grf {
92	u-boot,dm-spl;
93	status = "okay";
94};
95
96&u2phy {
97	u-boot,dm-spl;
98	status = "okay";
99};
100
101&u2phy_otg {
102	u-boot,dm-spl;
103	status = "okay";
104};
105