xref: /rk3399_rockchip-uboot/arch/arm/dts/px30-u-boot.dtsi (revision 2bcebb1a79550117e5474bb586bdc094e4fe0576)
1/*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc0 = &emmc;
10		mmc1 = &sdmmc;
11	};
12
13	chosen {
14		u-boot,spl-boot-order = &emmc, &sdmmc;
15		stdout-path = &uart2;
16	};
17};
18
19&psci {
20	u-boot,dm-pre-reloc;
21};
22
23&dmc {
24	u-boot,dm-pre-reloc;
25};
26
27&uart5 {
28	clock-frequency = <24000000>;
29	u-boot,dm-pre-reloc;
30};
31
32&uart2 {
33	clock-frequency = <24000000>;
34	u-boot,dm-pre-reloc;
35};
36
37&nandc0 {
38	u-boot,dm-pre-reloc;
39	status = "okay";
40};
41
42&sdmmc {
43	u-boot,dm-spl;
44};
45
46&emmc {
47	u-boot,dm-spl;
48};
49
50&pmugrf {
51	u-boot,dm-spl;
52};
53
54&cru {
55	u-boot,dm-spl;
56};
57
58&crypto {
59	u-boot,dm-spl;
60};
61
62&pmucru {
63	u-boot,dm-spl;
64};
65
66&saradc {
67	u-boot,dm-spl;
68	status = "okay";
69};
70
71&gpio0 {
72	u-boot,dm-pre-reloc;
73	status = "disabled";
74};
75
76&gpio1 {
77	u-boot,dm-pre-reloc;
78	status = "disabled";
79};
80
81&gpio2 {
82	u-boot,dm-pre-reloc;
83	status = "disabled";
84};
85
86&gpio3 {
87	u-boot,dm-pre-reloc;
88	status = "disabled";
89};
90
91&usb20_otg {
92	u-boot,dm-pre-reloc;
93};
94
95&usb2phy_grf {
96	u-boot,dm-pre-reloc;
97	status = "okay";
98};
99
100&u2phy {
101	u-boot,dm-pre-reloc;
102	status = "okay";
103};
104
105&u2phy_otg {
106	u-boot,dm-pre-reloc;
107	status = "okay";
108};
109
110&sfc {
111	u-boot,dm-spl;
112	/delete-property/ pinctrl-names;
113	/delete-property/ pinctrl-0;
114	/delete-property/ assigned-clocks;
115	/delete-property/ assigned-clock-rates;
116	status = "okay";
117
118	#address-cells = <1>;
119	#size-cells = <0>;
120	spi_nand: flash@0 {
121		u-boot,dm-spl;
122		compatible = "spi-nand";
123		reg = <0>;
124		spi-tx-bus-width = <1>;
125		spi-rx-bus-width = <4>;
126		spi-max-frequency = <75000000>;
127	};
128
129	spi_nor: flash@1 {
130		u-boot,dm-spl;
131		compatible = "jedec,spi-nor";
132		label = "sfc_nor";
133		reg = <0>;
134		spi-tx-bus-width = <1>;
135		spi-rx-bus-width = <4>;
136		spi-max-frequency = <100000000>;
137	};
138};
139
140&nandc0 {
141	u-boot,dm-pre-reloc;
142	status = "okay";
143	#address-cells = <1>;
144	#size-cells = <0>;
145
146	nand@0 {
147		u-boot,dm-pre-reloc;
148		reg = <0>;
149		nand-ecc-mode = "hw_syndrome";
150		nand-ecc-strength = <16>;
151		nand-ecc-step-size = <1024>;
152	};
153};
154