1*8b677614SBin Meng/* 2*8b677614SBin Meng * Freescale ls1021a TWR board common device tree source 3*8b677614SBin Meng * 4*8b677614SBin Meng * Copyright 2013-2015 Freescale Semiconductor, Inc. 5*8b677614SBin Meng * 6*8b677614SBin Meng * SPDX-License-Identifier: GPL-2.0+ 7*8b677614SBin Meng */ 8*8b677614SBin Meng 9*8b677614SBin Meng#include "ls1021a.dtsi" 10*8b677614SBin Meng 11*8b677614SBin Meng/ { 12*8b677614SBin Meng model = "LS1021A TWR Board"; 13*8b677614SBin Meng 14*8b677614SBin Meng aliases { 15*8b677614SBin Meng enet2_rgmii_phy = &rgmii_phy1; 16*8b677614SBin Meng enet0_sgmii_phy = &sgmii_phy2; 17*8b677614SBin Meng enet1_sgmii_phy = &sgmii_phy0; 18*8b677614SBin Meng spi0 = &qspi; 19*8b677614SBin Meng spi1 = &dspi1; 20*8b677614SBin Meng }; 21*8b677614SBin Meng 22*8b677614SBin Meng chosen { 23*8b677614SBin Meng stdout-path = &uart0; 24*8b677614SBin Meng }; 25*8b677614SBin Meng}; 26*8b677614SBin Meng 27*8b677614SBin Meng&qspi { 28*8b677614SBin Meng bus-num = <0>; 29*8b677614SBin Meng status = "okay"; 30*8b677614SBin Meng 31*8b677614SBin Meng qflash0: n25q128a13@0 { 32*8b677614SBin Meng #address-cells = <1>; 33*8b677614SBin Meng #size-cells = <1>; 34*8b677614SBin Meng compatible = "spi-flash"; 35*8b677614SBin Meng spi-max-frequency = <20000000>; 36*8b677614SBin Meng reg = <0>; 37*8b677614SBin Meng }; 38*8b677614SBin Meng}; 39*8b677614SBin Meng 40*8b677614SBin Meng&dspi1 { 41*8b677614SBin Meng bus-num = <0>; 42*8b677614SBin Meng status = "okay"; 43*8b677614SBin Meng 44*8b677614SBin Meng dspiflash: at26df081a@0 { 45*8b677614SBin Meng #address-cells = <1>; 46*8b677614SBin Meng #size-cells = <1>; 47*8b677614SBin Meng compatible = "spi-flash"; 48*8b677614SBin Meng spi-max-frequency = <16000000>; 49*8b677614SBin Meng spi-cpol; 50*8b677614SBin Meng spi-cpha; 51*8b677614SBin Meng reg = <0>; 52*8b677614SBin Meng }; 53*8b677614SBin Meng}; 54*8b677614SBin Meng 55*8b677614SBin Meng&i2c0 { 56*8b677614SBin Meng status = "okay"; 57*8b677614SBin Meng}; 58*8b677614SBin Meng 59*8b677614SBin Meng&i2c1 { 60*8b677614SBin Meng status = "okay"; 61*8b677614SBin Meng}; 62*8b677614SBin Meng 63*8b677614SBin Meng&ifc { 64*8b677614SBin Meng #address-cells = <2>; 65*8b677614SBin Meng #size-cells = <1>; 66*8b677614SBin Meng /* NOR Flash on board */ 67*8b677614SBin Meng ranges = <0x0 0x0 0x60000000 0x08000000>; 68*8b677614SBin Meng status = "okay"; 69*8b677614SBin Meng 70*8b677614SBin Meng nor@0,0 { 71*8b677614SBin Meng #address-cells = <1>; 72*8b677614SBin Meng #size-cells = <1>; 73*8b677614SBin Meng compatible = "cfi-flash"; 74*8b677614SBin Meng reg = <0x0 0x0 0x8000000>; 75*8b677614SBin Meng bank-width = <2>; 76*8b677614SBin Meng device-width = <1>; 77*8b677614SBin Meng }; 78*8b677614SBin Meng}; 79*8b677614SBin Meng 80*8b677614SBin Meng&lpuart0 { 81*8b677614SBin Meng status = "okay"; 82*8b677614SBin Meng}; 83*8b677614SBin Meng 84*8b677614SBin Meng&mdio0 { 85*8b677614SBin Meng sgmii_phy0: ethernet-phy@0 { 86*8b677614SBin Meng reg = <0x0>; 87*8b677614SBin Meng }; 88*8b677614SBin Meng rgmii_phy1: ethernet-phy@1 { 89*8b677614SBin Meng reg = <0x1>; 90*8b677614SBin Meng }; 91*8b677614SBin Meng sgmii_phy2: ethernet-phy@2 { 92*8b677614SBin Meng reg = <0x2>; 93*8b677614SBin Meng }; 94*8b677614SBin Meng tbi1: tbi-phy@1f { 95*8b677614SBin Meng reg = <0x1f>; 96*8b677614SBin Meng device_type = "tbi-phy"; 97*8b677614SBin Meng }; 98*8b677614SBin Meng}; 99*8b677614SBin Meng 100*8b677614SBin Meng&uart0 { 101*8b677614SBin Meng status = "okay"; 102*8b677614SBin Meng}; 103*8b677614SBin Meng 104*8b677614SBin Meng&uart1 { 105*8b677614SBin Meng status = "okay"; 106*8b677614SBin Meng}; 107