xref: /rk3399_rockchip-uboot/arch/arm/dts/ls1021a-iot.dtsi (revision 2d221489df021393654805536be7effcb9d39702)
1*20c700f8SFeng Li/*
2*20c700f8SFeng Li * Freescale ls1021a IOT board device tree source
3*20c700f8SFeng Li *
4*20c700f8SFeng Li * Copyright 2016 Freescale Semiconductor, Inc.
5*20c700f8SFeng Li *
6*20c700f8SFeng Li * SPDX-License-Identifier:	GPL-2.0+
7*20c700f8SFeng Li */
8*20c700f8SFeng Li
9*20c700f8SFeng Li
10*20c700f8SFeng Li#include "ls1021a.dtsi"
11*20c700f8SFeng Li
12*20c700f8SFeng Li/ {
13*20c700f8SFeng Li	model = "LS1021A IOT Board";
14*20c700f8SFeng Li
15*20c700f8SFeng Li	aliases {
16*20c700f8SFeng Li		enet2_rgmii_phy = &rgmii_phy1;
17*20c700f8SFeng Li		enet0_sgmii_phy = &sgmii_phy2;
18*20c700f8SFeng Li		enet1_sgmii_phy = &sgmii_phy0;
19*20c700f8SFeng Li		spi0 = &qspi;
20*20c700f8SFeng Li		spi1 = &dspi1;
21*20c700f8SFeng Li	};
22*20c700f8SFeng Li};
23*20c700f8SFeng Li
24*20c700f8SFeng Li&qspi {
25*20c700f8SFeng Li	bus-num = <0>;
26*20c700f8SFeng Li	status = "okay";
27*20c700f8SFeng Li
28*20c700f8SFeng Li	qflash0: n25q128a13@0 {
29*20c700f8SFeng Li		#address-cells = <1>;
30*20c700f8SFeng Li		#size-cells = <1>;
31*20c700f8SFeng Li		compatible = "spi-flash";
32*20c700f8SFeng Li		spi-max-frequency = <20000000>;
33*20c700f8SFeng Li		reg = <0>;
34*20c700f8SFeng Li	};
35*20c700f8SFeng Li};
36*20c700f8SFeng Li
37*20c700f8SFeng Li&dspi1 {
38*20c700f8SFeng Li	bus-num = <0>;
39*20c700f8SFeng Li	status = "okay";
40*20c700f8SFeng Li
41*20c700f8SFeng Li	dspiflash: at26df081a@0 {
42*20c700f8SFeng Li		#address-cells = <1>;
43*20c700f8SFeng Li		#size-cells = <1>;
44*20c700f8SFeng Li		compatible = "spi-flash";
45*20c700f8SFeng Li		spi-max-frequency = <16000000>;
46*20c700f8SFeng Li		spi-cpol;
47*20c700f8SFeng Li		spi-cpha;
48*20c700f8SFeng Li		reg = <0>;
49*20c700f8SFeng Li	};
50*20c700f8SFeng Li};
51*20c700f8SFeng Li
52*20c700f8SFeng Li&i2c0 {
53*20c700f8SFeng Li	status = "okay";
54*20c700f8SFeng Li};
55*20c700f8SFeng Li
56*20c700f8SFeng Li&i2c1 {
57*20c700f8SFeng Li	status = "okay";
58*20c700f8SFeng Li};
59*20c700f8SFeng Li
60*20c700f8SFeng Li&ifc {
61*20c700f8SFeng Li	#address-cells = <2>;
62*20c700f8SFeng Li	#size-cells = <1>;
63*20c700f8SFeng Li	/* NOR Flash on board */
64*20c700f8SFeng Li	ranges = <0x0 0x0 0x60000000 0x08000000>;
65*20c700f8SFeng Li	status = "okay";
66*20c700f8SFeng Li
67*20c700f8SFeng Li	nor@0,0 {
68*20c700f8SFeng Li		#address-cells = <1>;
69*20c700f8SFeng Li		#size-cells = <1>;
70*20c700f8SFeng Li		compatible = "cfi-flash";
71*20c700f8SFeng Li		reg = <0x0 0x0 0x8000000>;
72*20c700f8SFeng Li		bank-width = <2>;
73*20c700f8SFeng Li		device-width = <1>;
74*20c700f8SFeng Li	};
75*20c700f8SFeng Li};
76*20c700f8SFeng Li
77*20c700f8SFeng Li&lpuart0 {
78*20c700f8SFeng Li	status = "okay";
79*20c700f8SFeng Li};
80*20c700f8SFeng Li
81*20c700f8SFeng Li&mdio0 {
82*20c700f8SFeng Li	sgmii_phy0: ethernet-phy@0 {
83*20c700f8SFeng Li		reg = <0x0>;
84*20c700f8SFeng Li	};
85*20c700f8SFeng Li	rgmii_phy1: ethernet-phy@1 {
86*20c700f8SFeng Li		reg = <0x1>;
87*20c700f8SFeng Li	};
88*20c700f8SFeng Li	sgmii_phy2: ethernet-phy@2 {
89*20c700f8SFeng Li		reg = <0x2>;
90*20c700f8SFeng Li	};
91*20c700f8SFeng Li	tbi1: tbi-phy@1f {
92*20c700f8SFeng Li		reg = <0x1f>;
93*20c700f8SFeng Li		device_type = "tbi-phy";
94*20c700f8SFeng Li	};
95*20c700f8SFeng Li};
96*20c700f8SFeng Li
97*20c700f8SFeng Li&uart0 {
98*20c700f8SFeng Li	status = "okay";
99*20c700f8SFeng Li};
100*20c700f8SFeng Li
101*20c700f8SFeng Li&uart1 {
102*20c700f8SFeng Li	status = "okay";
103*20c700f8SFeng Li};
104