1/* 2 * Copyright 2013 Texas Instruments, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/gpio/gpio.h> 11 12#include "skeleton.dtsi" 13 14/ { 15 model = "Texas Instruments Keystone 2 SoC"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 }; 23 24 memory { 25 reg = <0x80000000 0x40000000>; 26 }; 27 28 gic: interrupt-controller { 29 compatible = "arm,cortex-a15-gic"; 30 #interrupt-cells = <3>; 31 interrupt-controller; 32 reg = <0x02561000 0x1000>, 33 <0x02562000 0x2000>, 34 <0x02564000 0x1000>, 35 <0x02566000 0x2000>; 36 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 37 IRQ_TYPE_LEVEL_HIGH)>; 38 }; 39 40 timer { 41 compatible = "arm,armv7-timer"; 42 interrupts = 43 <GIC_PPI 13 44 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 45 <GIC_PPI 14 46 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 47 <GIC_PPI 11 48 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 10 50 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 51 }; 52 53 pmu { 54 compatible = "arm,cortex-a15-pmu"; 55 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, 56 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 57 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, 58 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 59 }; 60 61 soc { 62 #address-cells = <1>; 63 #size-cells = <1>; 64 compatible = "ti,keystone","simple-bus"; 65 interrupt-parent = <&gic>; 66 ranges; 67 68 pllctrl: pll-controller@02310000 { 69 compatible = "ti,keystone-pllctrl", "syscon"; 70 reg = <0x02310000 0x200>; 71 }; 72 73 devctrl: device-state-control@02620000 { 74 compatible = "ti,keystone-devctrl", "syscon"; 75 reg = <0x02620000 0x1000>; 76 }; 77 78 rstctrl: reset-controller { 79 compatible = "ti,keystone-reset"; 80 ti,syscon-pll = <&pllctrl 0xe4>; 81 ti,syscon-dev = <&devctrl 0x328>; 82 ti,wdt-list = <0>; 83 }; 84 85 /include/ "keystone-clocks.dtsi" 86 87 uart0: serial@02530c00 { 88 compatible = "ns16550a"; 89 current-speed = <115200>; 90 reg-shift = <2>; 91 reg-io-width = <4>; 92 reg = <0x02530c00 0x100>; 93 clocks = <&clkuart0>; 94 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 95 }; 96 97 uart1: serial@02531000 { 98 compatible = "ns16550a"; 99 current-speed = <115200>; 100 reg-shift = <2>; 101 reg-io-width = <4>; 102 reg = <0x02531000 0x100>; 103 clocks = <&clkuart1>; 104 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 105 }; 106 107 i2c0: i2c@2530000 { 108 compatible = "ti,davinci-i2c"; 109 reg = <0x02530000 0x400>; 110 clock-frequency = <100000>; 111 clocks = <&clki2c>; 112 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 }; 116 117 i2c1: i2c@2530400 { 118 compatible = "ti,davinci-i2c"; 119 reg = <0x02530400 0x400>; 120 clock-frequency = <100000>; 121 clocks = <&clki2c>; 122 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; 123 #address-cells = <1>; 124 #size-cells = <0>; 125 }; 126 127 i2c2: i2c@2530800 { 128 compatible = "ti,davinci-i2c"; 129 reg = <0x02530800 0x400>; 130 clock-frequency = <100000>; 131 clocks = <&clki2c>; 132 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 }; 136 137 spi0: spi@21000400 { 138 compatible = "ti,dm6441-spi"; 139 reg = <0x21000400 0x200>; 140 num-cs = <4>; 141 ti,davinci-spi-intr-line = <0>; 142 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; 143 clocks = <&clkspi>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 }; 147 148 spi1: spi@21000600 { 149 compatible = "ti,dm6441-spi"; 150 reg = <0x21000600 0x200>; 151 num-cs = <4>; 152 ti,davinci-spi-intr-line = <0>; 153 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; 154 clocks = <&clkspi>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 }; 158 159 spi2: spi@21000800 { 160 compatible = "ti,dm6441-spi"; 161 reg = <0x21000800 0x200>; 162 num-cs = <4>; 163 ti,davinci-spi-intr-line = <0>; 164 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; 165 clocks = <&clkspi>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 }; 169 170 usb_phy: usb_phy@2620738 { 171 compatible = "ti,keystone-usbphy"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 reg = <0x2620738 24>; 175 status = "disabled"; 176 }; 177 178 usb: usb@2680000 { 179 compatible = "ti,keystone-dwc3"; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 reg = <0x2680000 0x10000>; 183 clocks = <&clkusb>; 184 clock-names = "usb"; 185 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; 186 ranges; 187 dma-coherent; 188 dma-ranges; 189 status = "disabled"; 190 191 dwc3@2690000 { 192 compatible = "synopsys,dwc3"; 193 reg = <0x2690000 0x70000>; 194 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; 195 usb-phy = <&usb_phy>, <&usb_phy>; 196 }; 197 }; 198 199 wdt: wdt@022f0080 { 200 compatible = "ti,keystone-wdt","ti,davinci-wdt"; 201 reg = <0x022f0080 0x80>; 202 clocks = <&clkwdtimer0>; 203 }; 204 205 clock_event: timer@22f0000 { 206 compatible = "ti,keystone-timer"; 207 reg = <0x022f0000 0x80>; 208 interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; 209 clocks = <&clktimer15>; 210 }; 211 212 gpio0: gpio@260bf00 { 213 compatible = "ti,keystone-gpio"; 214 reg = <0x0260bf00 0x100>; 215 gpio-controller; 216 #gpio-cells = <2>; 217 /* HW Interrupts mapped to GPIO pins */ 218 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 223 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 224 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 225 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 226 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 227 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 228 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 229 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 230 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 231 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 232 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 233 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 235 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 236 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 237 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 238 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, 239 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 240 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, 241 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>, 242 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>, 243 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 244 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, 245 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>, 246 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, 247 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 248 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>, 249 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 250 clocks = <&clkgpio>; 251 clock-names = "gpio"; 252 ti,ngpio = <32>; 253 ti,davinci-gpio-unbanked = <32>; 254 }; 255 256 aemif: aemif@21000A00 { 257 compatible = "ti,keystone-aemif", "ti,davinci-aemif"; 258 #address-cells = <2>; 259 #size-cells = <1>; 260 clocks = <&clkaemif>; 261 clock-names = "aemif"; 262 clock-ranges; 263 264 reg = <0x21000A00 0x00000100>; 265 ranges = <0 0 0x30000000 0x10000000 266 1 0 0x21000A00 0x00000100>; 267 }; 268 269 kirq0: keystone_irq@26202a0 { 270 compatible = "ti,keystone-irq"; 271 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 272 interrupt-controller; 273 #interrupt-cells = <1>; 274 ti,syscon-dev = <&devctrl 0x2a0>; 275 }; 276 277 pcie0: pcie@21800000 { 278 compatible = "ti,keystone-pcie", "snps,dw-pcie"; 279 clocks = <&clkpcie>; 280 clock-names = "pcie"; 281 #address-cells = <3>; 282 #size-cells = <2>; 283 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; 284 ranges = <0x81000000 0 0 0x23250000 0 0x4000 285 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; 286 287 status = "disabled"; 288 device_type = "pci"; 289 num-lanes = <2>; 290 291 #interrupt-cells = <1>; 292 interrupt-map-mask = <0 0 0 7>; 293 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ 294 <0 0 0 2 &pcie_intc0 1>, /* INT B */ 295 <0 0 0 3 &pcie_intc0 2>, /* INT C */ 296 <0 0 0 4 &pcie_intc0 3>; /* INT D */ 297 298 pcie_msi_intc0: msi-interrupt-controller { 299 interrupt-controller; 300 #interrupt-cells = <1>; 301 interrupt-parent = <&gic>; 302 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 303 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 306 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 307 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; 310 }; 311 312 pcie_intc0: legacy-interrupt-controller { 313 interrupt-controller; 314 #interrupt-cells = <1>; 315 interrupt-parent = <&gic>; 316 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; 320 }; 321 }; 322 }; 323}; 324