1*5ec1f560SSimon Glass/* 2*5ec1f560SSimon Glass * Copyright 2013 CompuLab Ltd. 3*5ec1f560SSimon Glass * 4*5ec1f560SSimon Glass * Author: Valentin Raevsky <valentin@compulab.co.il> 5*5ec1f560SSimon Glass * 6*5ec1f560SSimon Glass * The code contained herein is licensed under the GNU General Public 7*5ec1f560SSimon Glass * License. You may obtain a copy of the GNU General Public License 8*5ec1f560SSimon Glass * Version 2 or later at the following locations: 9*5ec1f560SSimon Glass * 10*5ec1f560SSimon Glass * http://www.opensource.org/licenses/gpl-license.html 11*5ec1f560SSimon Glass * http://www.gnu.org/copyleft/gpl.html 12*5ec1f560SSimon Glass */ 13*5ec1f560SSimon Glass 14*5ec1f560SSimon Glass/dts-v1/; 15*5ec1f560SSimon Glass#include "imx6q.dtsi" 16*5ec1f560SSimon Glass 17*5ec1f560SSimon Glass/ { 18*5ec1f560SSimon Glass model = "CompuLab CM-FX6"; 19*5ec1f560SSimon Glass compatible = "compulab,cm-fx6", "fsl,imx6q"; 20*5ec1f560SSimon Glass 21*5ec1f560SSimon Glass memory { 22*5ec1f560SSimon Glass reg = <0x10000000 0x80000000>; 23*5ec1f560SSimon Glass }; 24*5ec1f560SSimon Glass 25*5ec1f560SSimon Glass leds { 26*5ec1f560SSimon Glass compatible = "gpio-leds"; 27*5ec1f560SSimon Glass 28*5ec1f560SSimon Glass heartbeat-led { 29*5ec1f560SSimon Glass label = "Heartbeat"; 30*5ec1f560SSimon Glass gpios = <&gpio2 31 0>; 31*5ec1f560SSimon Glass linux,default-trigger = "heartbeat"; 32*5ec1f560SSimon Glass }; 33*5ec1f560SSimon Glass }; 34*5ec1f560SSimon Glass}; 35*5ec1f560SSimon Glass 36*5ec1f560SSimon Glass&fec { 37*5ec1f560SSimon Glass pinctrl-names = "default"; 38*5ec1f560SSimon Glass pinctrl-0 = <&pinctrl_enet>; 39*5ec1f560SSimon Glass phy-mode = "rgmii"; 40*5ec1f560SSimon Glass status = "okay"; 41*5ec1f560SSimon Glass}; 42*5ec1f560SSimon Glass 43*5ec1f560SSimon Glass&gpmi { 44*5ec1f560SSimon Glass pinctrl-names = "default"; 45*5ec1f560SSimon Glass pinctrl-0 = <&pinctrl_gpmi_nand>; 46*5ec1f560SSimon Glass status = "okay"; 47*5ec1f560SSimon Glass}; 48*5ec1f560SSimon Glass 49*5ec1f560SSimon Glass&iomuxc { 50*5ec1f560SSimon Glass imx6q-cm-fx6 { 51*5ec1f560SSimon Glass pinctrl_enet: enetgrp { 52*5ec1f560SSimon Glass fsl,pins = < 53*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 54*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 55*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 56*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 57*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 58*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 59*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 60*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 61*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 62*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 63*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 64*5ec1f560SSimon Glass MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 65*5ec1f560SSimon Glass MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 66*5ec1f560SSimon Glass MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 67*5ec1f560SSimon Glass MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 68*5ec1f560SSimon Glass MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 69*5ec1f560SSimon Glass >; 70*5ec1f560SSimon Glass }; 71*5ec1f560SSimon Glass 72*5ec1f560SSimon Glass pinctrl_gpmi_nand: gpminandgrp { 73*5ec1f560SSimon Glass fsl,pins = < 74*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 75*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 76*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 77*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 78*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 79*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 80*5ec1f560SSimon Glass MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 81*5ec1f560SSimon Glass MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 82*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 83*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 84*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 85*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 86*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 87*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 88*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 89*5ec1f560SSimon Glass MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 90*5ec1f560SSimon Glass MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 91*5ec1f560SSimon Glass >; 92*5ec1f560SSimon Glass }; 93*5ec1f560SSimon Glass 94*5ec1f560SSimon Glass pinctrl_uart4: uart4grp { 95*5ec1f560SSimon Glass fsl,pins = < 96*5ec1f560SSimon Glass MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 97*5ec1f560SSimon Glass MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 98*5ec1f560SSimon Glass >; 99*5ec1f560SSimon Glass }; 100*5ec1f560SSimon Glass }; 101*5ec1f560SSimon Glass}; 102*5ec1f560SSimon Glass 103*5ec1f560SSimon Glass&uart4 { 104*5ec1f560SSimon Glass pinctrl-names = "default"; 105*5ec1f560SSimon Glass pinctrl-0 = <&pinctrl_uart4>; 106*5ec1f560SSimon Glass status = "okay"; 107*5ec1f560SSimon Glass}; 108*5ec1f560SSimon Glass 109*5ec1f560SSimon Glass&sata { 110*5ec1f560SSimon Glass status = "okay"; 111*5ec1f560SSimon Glass}; 112*5ec1f560SSimon Glass 113*5ec1f560SSimon Glass&usdhc3 { 114*5ec1f560SSimon Glass status = "okay"; 115*5ec1f560SSimon Glass}; 116